xref: /qemu/target/tricore/cpu.c (revision ce32a9e9) 
1 /*
2  *  TriCore emulation for qemu: main translation routines.
3  *
4  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "qemu/error-report.h"
25 #include "tcg/debug-assert.h"
26 
27 static inline void set_feature(CPUTriCoreState *env, int feature)
28 {
29     env->features |= 1ULL << feature;
30 }
31 
32 static const gchar *tricore_gdb_arch_name(CPUState *cs)
33 {
34     return "tricore";
35 }
36 
37 static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
38 {
39     TriCoreCPU *cpu = TRICORE_CPU(cs);
40     CPUTriCoreState *env = &cpu->env;
41 
42     env->PC = value & ~(target_ulong)1;
43 }
44 
45 static vaddr tricore_cpu_get_pc(CPUState *cs)
46 {
47     TriCoreCPU *cpu = TRICORE_CPU(cs);
48     CPUTriCoreState *env = &cpu->env;
49 
50     return env->PC;
51 }
52 
53 static void tricore_cpu_synchronize_from_tb(CPUState *cs,
54                                             const TranslationBlock *tb)
55 {
56     TriCoreCPU *cpu = TRICORE_CPU(cs);
57     CPUTriCoreState *env = &cpu->env;
58 
59     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
60     env->PC = tb->pc;
61 }
62 
63 static void tricore_restore_state_to_opc(CPUState *cs,
64                                          const TranslationBlock *tb,
65                                          const uint64_t *data)
66 {
67     TriCoreCPU *cpu = TRICORE_CPU(cs);
68     CPUTriCoreState *env = &cpu->env;
69 
70     env->PC = data[0];
71 }
72 
73 static void tricore_cpu_reset_hold(Object *obj)
74 {
75     CPUState *s = CPU(obj);
76     TriCoreCPU *cpu = TRICORE_CPU(s);
77     TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu);
78     CPUTriCoreState *env = &cpu->env;
79 
80     if (tcc->parent_phases.hold) {
81         tcc->parent_phases.hold(obj);
82     }
83 
84     cpu_state_reset(env);
85 }
86 
87 static bool tricore_cpu_has_work(CPUState *cs)
88 {
89     return true;
90 }
91 
92 static void tricore_cpu_realizefn(DeviceState *dev, Error **errp)
93 {
94     CPUState *cs = CPU(dev);
95     TriCoreCPU *cpu = TRICORE_CPU(dev);
96     TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(dev);
97     CPUTriCoreState *env = &cpu->env;
98     Error *local_err = NULL;
99 
100     cpu_exec_realizefn(cs, &local_err);
101     if (local_err != NULL) {
102         error_propagate(errp, local_err);
103         return;
104     }
105 
106     /* Some features automatically imply others */
107     if (tricore_has_feature(env, TRICORE_FEATURE_162)) {
108         set_feature(env, TRICORE_FEATURE_161);
109     }
110 
111     if (tricore_has_feature(env, TRICORE_FEATURE_161)) {
112         set_feature(env, TRICORE_FEATURE_16);
113     }
114 
115     if (tricore_has_feature(env, TRICORE_FEATURE_16)) {
116         set_feature(env, TRICORE_FEATURE_131);
117     }
118     if (tricore_has_feature(env, TRICORE_FEATURE_131)) {
119         set_feature(env, TRICORE_FEATURE_13);
120     }
121     cpu_reset(cs);
122     qemu_init_vcpu(cs);
123 
124     tcc->parent_realize(dev, errp);
125 }
126 
127 static ObjectClass *tricore_cpu_class_by_name(const char *cpu_model)
128 {
129     ObjectClass *oc;
130     char *typename;
131 
132     typename = g_strdup_printf(TRICORE_CPU_TYPE_NAME("%s"), cpu_model);
133     oc = object_class_by_name(typename);
134     g_free(typename);
135     if (!oc || !object_class_dynamic_cast(oc, TYPE_TRICORE_CPU) ||
136         object_class_is_abstract(oc)) {
137         return NULL;
138     }
139     return oc;
140 }
141 
142 static void tc1796_initfn(Object *obj)
143 {
144     TriCoreCPU *cpu = TRICORE_CPU(obj);
145 
146     set_feature(&cpu->env, TRICORE_FEATURE_13);
147 }
148 
149 static void tc1797_initfn(Object *obj)
150 {
151     TriCoreCPU *cpu = TRICORE_CPU(obj);
152 
153     set_feature(&cpu->env, TRICORE_FEATURE_131);
154 }
155 
156 static void tc27x_initfn(Object *obj)
157 {
158     TriCoreCPU *cpu = TRICORE_CPU(obj);
159 
160     set_feature(&cpu->env, TRICORE_FEATURE_161);
161 }
162 
163 static void tc37x_initfn(Object *obj)
164 {
165     TriCoreCPU *cpu = TRICORE_CPU(obj);
166 
167     set_feature(&cpu->env, TRICORE_FEATURE_162);
168 }
169 
170 
171 #include "hw/core/sysemu-cpu-ops.h"
172 
173 static const struct SysemuCPUOps tricore_sysemu_ops = {
174     .get_phys_page_debug = tricore_cpu_get_phys_page_debug,
175 };
176 
177 #include "hw/core/tcg-cpu-ops.h"
178 
179 static const struct TCGCPUOps tricore_tcg_ops = {
180     .initialize = tricore_tcg_init,
181     .synchronize_from_tb = tricore_cpu_synchronize_from_tb,
182     .restore_state_to_opc = tricore_restore_state_to_opc,
183     .tlb_fill = tricore_cpu_tlb_fill,
184 };
185 
186 static void tricore_cpu_class_init(ObjectClass *c, void *data)
187 {
188     TriCoreCPUClass *mcc = TRICORE_CPU_CLASS(c);
189     CPUClass *cc = CPU_CLASS(c);
190     DeviceClass *dc = DEVICE_CLASS(c);
191     ResettableClass *rc = RESETTABLE_CLASS(c);
192 
193     device_class_set_parent_realize(dc, tricore_cpu_realizefn,
194                                     &mcc->parent_realize);
195 
196     resettable_class_set_parent_phases(rc, NULL, tricore_cpu_reset_hold, NULL,
197                                        &mcc->parent_phases);
198     cc->class_by_name = tricore_cpu_class_by_name;
199     cc->has_work = tricore_cpu_has_work;
200 
201     cc->gdb_read_register = tricore_cpu_gdb_read_register;
202     cc->gdb_write_register = tricore_cpu_gdb_write_register;
203     cc->gdb_num_core_regs = 44;
204     cc->gdb_arch_name = tricore_gdb_arch_name;
205 
206     cc->dump_state = tricore_cpu_dump_state;
207     cc->set_pc = tricore_cpu_set_pc;
208     cc->get_pc = tricore_cpu_get_pc;
209     cc->sysemu_ops = &tricore_sysemu_ops;
210     cc->tcg_ops = &tricore_tcg_ops;
211 }
212 
213 #define DEFINE_TRICORE_CPU_TYPE(cpu_model, initfn) \
214     {                                              \
215         .parent = TYPE_TRICORE_CPU,                \
216         .instance_init = initfn,                   \
217         .name = TRICORE_CPU_TYPE_NAME(cpu_model),  \
218     }
219 
220 static const TypeInfo tricore_cpu_type_infos[] = {
221     {
222         .name = TYPE_TRICORE_CPU,
223         .parent = TYPE_CPU,
224         .instance_size = sizeof(TriCoreCPU),
225         .instance_align = __alignof(TriCoreCPU),
226         .abstract = true,
227         .class_size = sizeof(TriCoreCPUClass),
228         .class_init = tricore_cpu_class_init,
229     },
230     DEFINE_TRICORE_CPU_TYPE("tc1796", tc1796_initfn),
231     DEFINE_TRICORE_CPU_TYPE("tc1797", tc1797_initfn),
232     DEFINE_TRICORE_CPU_TYPE("tc27x", tc27x_initfn),
233     DEFINE_TRICORE_CPU_TYPE("tc37x", tc37x_initfn),
234 };
235 
236 DEFINE_TYPES(tricore_cpu_type_infos)
237