1 /* 2 * TriCore emulation for qemu: main CPU struct. 3 * 4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef TRICORE_CPU_H 21 #define TRICORE_CPU_H 22 23 #include "cpu-qom.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "tricore-defs.h" 28 29 typedef struct CPUArchState { 30 /* GPR Register */ 31 uint32_t gpr_a[16]; 32 uint32_t gpr_d[16]; 33 /* CSFR Register */ 34 uint32_t PCXI; 35 /* Frequently accessed PSW_USB bits are stored separately for efficiency. 36 This contains all the other bits. Use psw_{read,write} to access 37 the whole PSW. */ 38 uint32_t PSW; 39 40 /* PSW flag cache for faster execution 41 */ 42 uint32_t PSW_USB_C; 43 uint32_t PSW_USB_V; /* Only if bit 31 set, then flag is set */ 44 uint32_t PSW_USB_SV; /* Only if bit 31 set, then flag is set */ 45 uint32_t PSW_USB_AV; /* Only if bit 31 set, then flag is set. */ 46 uint32_t PSW_USB_SAV; /* Only if bit 31 set, then flag is set. */ 47 48 uint32_t PC; 49 uint32_t SYSCON; 50 uint32_t CPU_ID; 51 uint32_t CORE_ID; 52 uint32_t BIV; 53 uint32_t BTV; 54 uint32_t ISP; 55 uint32_t ICR; 56 uint32_t FCX; 57 uint32_t LCX; 58 uint32_t COMPAT; 59 60 /* Mem Protection Register */ 61 uint32_t DPR0_0L; 62 uint32_t DPR0_0U; 63 uint32_t DPR0_1L; 64 uint32_t DPR0_1U; 65 uint32_t DPR0_2L; 66 uint32_t DPR0_2U; 67 uint32_t DPR0_3L; 68 uint32_t DPR0_3U; 69 70 uint32_t DPR1_0L; 71 uint32_t DPR1_0U; 72 uint32_t DPR1_1L; 73 uint32_t DPR1_1U; 74 uint32_t DPR1_2L; 75 uint32_t DPR1_2U; 76 uint32_t DPR1_3L; 77 uint32_t DPR1_3U; 78 79 uint32_t DPR2_0L; 80 uint32_t DPR2_0U; 81 uint32_t DPR2_1L; 82 uint32_t DPR2_1U; 83 uint32_t DPR2_2L; 84 uint32_t DPR2_2U; 85 uint32_t DPR2_3L; 86 uint32_t DPR2_3U; 87 88 uint32_t DPR3_0L; 89 uint32_t DPR3_0U; 90 uint32_t DPR3_1L; 91 uint32_t DPR3_1U; 92 uint32_t DPR3_2L; 93 uint32_t DPR3_2U; 94 uint32_t DPR3_3L; 95 uint32_t DPR3_3U; 96 97 uint32_t CPR0_0L; 98 uint32_t CPR0_0U; 99 uint32_t CPR0_1L; 100 uint32_t CPR0_1U; 101 uint32_t CPR0_2L; 102 uint32_t CPR0_2U; 103 uint32_t CPR0_3L; 104 uint32_t CPR0_3U; 105 106 uint32_t CPR1_0L; 107 uint32_t CPR1_0U; 108 uint32_t CPR1_1L; 109 uint32_t CPR1_1U; 110 uint32_t CPR1_2L; 111 uint32_t CPR1_2U; 112 uint32_t CPR1_3L; 113 uint32_t CPR1_3U; 114 115 uint32_t CPR2_0L; 116 uint32_t CPR2_0U; 117 uint32_t CPR2_1L; 118 uint32_t CPR2_1U; 119 uint32_t CPR2_2L; 120 uint32_t CPR2_2U; 121 uint32_t CPR2_3L; 122 uint32_t CPR2_3U; 123 124 uint32_t CPR3_0L; 125 uint32_t CPR3_0U; 126 uint32_t CPR3_1L; 127 uint32_t CPR3_1U; 128 uint32_t CPR3_2L; 129 uint32_t CPR3_2U; 130 uint32_t CPR3_3L; 131 uint32_t CPR3_3U; 132 133 uint32_t DPM0; 134 uint32_t DPM1; 135 uint32_t DPM2; 136 uint32_t DPM3; 137 138 uint32_t CPM0; 139 uint32_t CPM1; 140 uint32_t CPM2; 141 uint32_t CPM3; 142 143 /* Memory Management Registers */ 144 uint32_t MMU_CON; 145 uint32_t MMU_ASI; 146 uint32_t MMU_TVA; 147 uint32_t MMU_TPA; 148 uint32_t MMU_TPX; 149 uint32_t MMU_TFA; 150 /* {1.3.1 only */ 151 uint32_t BMACON; 152 uint32_t SMACON; 153 uint32_t DIEAR; 154 uint32_t DIETR; 155 uint32_t CCDIER; 156 uint32_t MIECON; 157 uint32_t PIEAR; 158 uint32_t PIETR; 159 uint32_t CCPIER; 160 /*} */ 161 /* Debug Registers */ 162 uint32_t DBGSR; 163 uint32_t EXEVT; 164 uint32_t CREVT; 165 uint32_t SWEVT; 166 uint32_t TR0EVT; 167 uint32_t TR1EVT; 168 uint32_t DMS; 169 uint32_t DCX; 170 uint32_t DBGTCR; 171 uint32_t CCTRL; 172 uint32_t CCNT; 173 uint32_t ICNT; 174 uint32_t M1CNT; 175 uint32_t M2CNT; 176 uint32_t M3CNT; 177 /* Floating Point Registers */ 178 float_status fp_status; 179 180 /* Internal CPU feature flags. */ 181 uint64_t features; 182 } CPUTriCoreState; 183 184 /** 185 * TriCoreCPU: 186 * @env: #CPUTriCoreState 187 * 188 * A TriCore CPU. 189 */ 190 struct ArchCPU { 191 /*< private >*/ 192 CPUState parent_obj; 193 /*< public >*/ 194 195 CPUNegativeOffsetState neg; 196 CPUTriCoreState env; 197 }; 198 199 200 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 201 void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 202 203 FIELD(PCXI, PCPN_13, 24, 8) 204 FIELD(PCXI, PCPN_161, 22, 8) 205 FIELD(PCXI, PIE_13, 23, 1) 206 FIELD(PCXI, PIE_161, 21, 1) 207 FIELD(PCXI, UL_13, 22, 1) 208 FIELD(PCXI, UL_161, 20, 1) 209 FIELD(PCXI, PCXS, 16, 4) 210 FIELD(PCXI, PCXO, 0, 16) 211 uint32_t pcxi_get_ul(CPUTriCoreState *env); 212 uint32_t pcxi_get_pie(CPUTriCoreState *env); 213 uint32_t pcxi_get_pcpn(CPUTriCoreState *env); 214 uint32_t pcxi_get_pcxs(CPUTriCoreState *env); 215 uint32_t pcxi_get_pcxo(CPUTriCoreState *env); 216 void pcxi_set_ul(CPUTriCoreState *env, uint32_t val); 217 void pcxi_set_pie(CPUTriCoreState *env, uint32_t val); 218 void pcxi_set_pcpn(CPUTriCoreState *env, uint32_t val); 219 220 FIELD(ICR, IE_161, 15, 1) 221 FIELD(ICR, IE_13, 8, 1) 222 FIELD(ICR, PIPN, 16, 8) 223 FIELD(ICR, CCPN, 0, 8) 224 225 uint32_t icr_get_ie(CPUTriCoreState *env); 226 uint32_t icr_get_ccpn(CPUTriCoreState *env); 227 228 void icr_set_ccpn(CPUTriCoreState *env, uint32_t val); 229 void icr_set_ie(CPUTriCoreState *env, uint32_t val); 230 231 #define MASK_PSW_USB 0xff000000 232 #define MASK_USB_C 0x80000000 233 #define MASK_USB_V 0x40000000 234 #define MASK_USB_SV 0x20000000 235 #define MASK_USB_AV 0x10000000 236 #define MASK_USB_SAV 0x08000000 237 #define MASK_PSW_PRS 0x00003000 238 #define MASK_PSW_IO 0x00000c00 239 #define MASK_PSW_IS 0x00000200 240 #define MASK_PSW_GW 0x00000100 241 #define MASK_PSW_CDE 0x00000080 242 #define MASK_PSW_CDC 0x0000007f 243 #define MASK_PSW_FPU_RM 0x3000000 244 245 #define MASK_SYSCON_PRO_TEN 0x2 246 #define MASK_SYSCON_FCD_SF 0x1 247 248 #define MASK_CPUID_MOD 0xffff0000 249 #define MASK_CPUID_MOD_32B 0x0000ff00 250 #define MASK_CPUID_REV 0x000000ff 251 252 253 #define MASK_FCX_FCXS 0x000f0000 254 #define MASK_FCX_FCXO 0x0000ffff 255 256 #define MASK_LCX_LCXS 0x000f0000 257 #define MASK_LCX_LCX0 0x0000ffff 258 259 #define MASK_DBGSR_DE 0x1 260 #define MASK_DBGSR_HALT 0x6 261 #define MASK_DBGSR_SUSP 0x10 262 #define MASK_DBGSR_PREVSUSP 0x20 263 #define MASK_DBGSR_PEVT 0x40 264 #define MASK_DBGSR_EVTSRC 0x1f00 265 266 enum tricore_priv_levels { 267 TRICORE_PRIV_UM0 = 0x0, /* user mode-0 flag */ 268 TRICORE_PRIV_UM1 = 0x1, /* user mode-1 flag */ 269 TRICORE_PRIV_SM = 0x2, /* kernel mode flag */ 270 }; 271 272 enum tricore_features { 273 TRICORE_FEATURE_13, 274 TRICORE_FEATURE_131, 275 TRICORE_FEATURE_16, 276 TRICORE_FEATURE_161, 277 TRICORE_FEATURE_162, 278 }; 279 280 static inline int tricore_feature(CPUTriCoreState *env, int feature) 281 { 282 return (env->features & (1ULL << feature)) != 0; 283 } 284 285 /* TriCore Traps Classes*/ 286 enum { 287 TRAPC_NONE = -1, 288 TRAPC_MMU = 0, 289 TRAPC_PROT = 1, 290 TRAPC_INSN_ERR = 2, 291 TRAPC_CTX_MNG = 3, 292 TRAPC_SYSBUS = 4, 293 TRAPC_ASSERT = 5, 294 TRAPC_SYSCALL = 6, 295 TRAPC_NMI = 7, 296 TRAPC_IRQ = 8 297 }; 298 299 /* Class 0 TIN */ 300 enum { 301 TIN0_VAF = 0, 302 TIN0_VAP = 1, 303 }; 304 305 /* Class 1 TIN */ 306 enum { 307 TIN1_PRIV = 1, 308 TIN1_MPR = 2, 309 TIN1_MPW = 3, 310 TIN1_MPX = 4, 311 TIN1_MPP = 5, 312 TIN1_MPN = 6, 313 TIN1_GRWP = 7, 314 }; 315 316 /* Class 2 TIN */ 317 enum { 318 TIN2_IOPC = 1, 319 TIN2_UOPC = 2, 320 TIN2_OPD = 3, 321 TIN2_ALN = 4, 322 TIN2_MEM = 5, 323 }; 324 325 /* Class 3 TIN */ 326 enum { 327 TIN3_FCD = 1, 328 TIN3_CDO = 2, 329 TIN3_CDU = 3, 330 TIN3_FCU = 4, 331 TIN3_CSU = 5, 332 TIN3_CTYP = 6, 333 TIN3_NEST = 7, 334 }; 335 336 /* Class 4 TIN */ 337 enum { 338 TIN4_PSE = 1, 339 TIN4_DSE = 2, 340 TIN4_DAE = 3, 341 TIN4_CAE = 4, 342 TIN4_PIE = 5, 343 TIN4_DIE = 6, 344 }; 345 346 /* Class 5 TIN */ 347 enum { 348 TIN5_OVF = 1, 349 TIN5_SOVF = 1, 350 }; 351 352 /* Class 6 TIN 353 * 354 * Is always TIN6_SYS 355 */ 356 357 /* Class 7 TIN */ 358 enum { 359 TIN7_NMI = 0, 360 }; 361 362 uint32_t psw_read(CPUTriCoreState *env); 363 void psw_write(CPUTriCoreState *env, uint32_t val); 364 int tricore_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n); 365 int tricore_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n); 366 367 void fpu_set_state(CPUTriCoreState *env); 368 369 #define MMU_USER_IDX 2 370 371 void tricore_cpu_list(void); 372 373 #define cpu_list tricore_cpu_list 374 375 static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) 376 { 377 return 0; 378 } 379 380 #include "exec/cpu-all.h" 381 382 FIELD(TB_FLAGS, PRIV, 0, 2) 383 384 void cpu_state_reset(CPUTriCoreState *s); 385 void tricore_tcg_init(void); 386 387 static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, target_ulong *pc, 388 target_ulong *cs_base, uint32_t *flags) 389 { 390 uint32_t new_flags = 0; 391 *pc = env->PC; 392 *cs_base = 0; 393 394 new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV, 395 extract32(env->PSW, 10, 2)); 396 *flags = new_flags; 397 } 398 399 #define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU 400 #define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX 401 #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU 402 403 /* helpers.c */ 404 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 405 MMUAccessType access_type, int mmu_idx, 406 bool probe, uintptr_t retaddr); 407 408 #endif /* TRICORE_CPU_H */ 409