1 /* 2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn 3 * 4 * This library is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU Lesser General Public 6 * License as published by the Free Software Foundation; either 7 * version 2.1 of the License, or (at your option) any later version. 8 * 9 * This library is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 * Lesser General Public License for more details. 13 * 14 * You should have received a copy of the GNU Lesser General Public 15 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/log.h" 20 #include "hw/registerfields.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "fpu/softfloat-helpers.h" 24 #include "qemu/qemu-print.h" 25 26 enum { 27 TLBRET_DIRTY = -4, 28 TLBRET_INVALID = -3, 29 TLBRET_NOMATCH = -2, 30 TLBRET_BADADDR = -1, 31 TLBRET_MATCH = 0 32 }; 33 34 static int get_physical_address(CPUTriCoreState *env, hwaddr *physical, 35 int *prot, target_ulong address, 36 MMUAccessType access_type, int mmu_idx) 37 { 38 int ret = TLBRET_MATCH; 39 40 *physical = address & 0xFFFFFFFF; 41 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 42 43 return ret; 44 } 45 46 hwaddr tricore_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 47 { 48 TriCoreCPU *cpu = TRICORE_CPU(cs); 49 hwaddr phys_addr; 50 int prot; 51 int mmu_idx = cpu_mmu_index(&cpu->env, false); 52 53 if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 54 MMU_DATA_LOAD, mmu_idx)) { 55 return -1; 56 } 57 return phys_addr; 58 } 59 60 /* TODO: Add exception support */ 61 static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address, 62 int rw, int tlb_error) 63 { 64 } 65 66 bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 67 MMUAccessType rw, int mmu_idx, 68 bool probe, uintptr_t retaddr) 69 { 70 TriCoreCPU *cpu = TRICORE_CPU(cs); 71 CPUTriCoreState *env = &cpu->env; 72 hwaddr physical; 73 int prot; 74 int ret = 0; 75 76 rw &= 1; 77 ret = get_physical_address(env, &physical, &prot, 78 address, rw, mmu_idx); 79 80 qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " 81 HWADDR_FMT_plx " prot %d\n", 82 __func__, (target_ulong)address, ret, physical, prot); 83 84 if (ret == TLBRET_MATCH) { 85 tlb_set_page(cs, address & TARGET_PAGE_MASK, 86 physical & TARGET_PAGE_MASK, prot | PAGE_EXEC, 87 mmu_idx, TARGET_PAGE_SIZE); 88 return true; 89 } else { 90 assert(ret < 0); 91 if (probe) { 92 return false; 93 } 94 raise_mmu_exception(env, address, rw, ret); 95 cpu_loop_exit_restore(cs, retaddr); 96 } 97 } 98 99 static void tricore_cpu_list_entry(gpointer data, gpointer user_data) 100 { 101 ObjectClass *oc = data; 102 const char *typename; 103 char *name; 104 105 typename = object_class_get_name(oc); 106 name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU)); 107 qemu_printf(" %s\n", name); 108 g_free(name); 109 } 110 111 void tricore_cpu_list(void) 112 { 113 GSList *list; 114 115 list = object_class_get_list_sorted(TYPE_TRICORE_CPU, false); 116 qemu_printf("Available CPUs:\n"); 117 g_slist_foreach(list, tricore_cpu_list_entry, NULL); 118 g_slist_free(list); 119 } 120 121 void fpu_set_state(CPUTriCoreState *env) 122 { 123 set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status); 124 set_flush_inputs_to_zero(1, &env->fp_status); 125 set_flush_to_zero(1, &env->fp_status); 126 set_default_nan_mode(1, &env->fp_status); 127 } 128 129 uint32_t psw_read(CPUTriCoreState *env) 130 { 131 /* clear all USB bits */ 132 env->PSW &= 0x6ffffff; 133 /* now set them from the cache */ 134 env->PSW |= ((env->PSW_USB_C != 0) << 31); 135 env->PSW |= ((env->PSW_USB_V & (1 << 31)) >> 1); 136 env->PSW |= ((env->PSW_USB_SV & (1 << 31)) >> 2); 137 env->PSW |= ((env->PSW_USB_AV & (1 << 31)) >> 3); 138 env->PSW |= ((env->PSW_USB_SAV & (1 << 31)) >> 4); 139 140 return env->PSW; 141 } 142 143 void psw_write(CPUTriCoreState *env, uint32_t val) 144 { 145 env->PSW_USB_C = (val & MASK_USB_C); 146 env->PSW_USB_V = (val & MASK_USB_V) << 1; 147 env->PSW_USB_SV = (val & MASK_USB_SV) << 2; 148 env->PSW_USB_AV = (val & MASK_USB_AV) << 3; 149 env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4; 150 env->PSW = val; 151 152 fpu_set_state(env); 153 } 154 155 #define FIELD_GETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ 156 uint32_t NAME(CPUTriCoreState *env) \ 157 { \ 158 if (tricore_has_feature(env, TRICORE_FEATURE_##FEATURE)) { \ 159 return FIELD_EX32(env->REG, REG, FIELD ## _ ## FEATURE); \ 160 } \ 161 return FIELD_EX32(env->REG, REG, FIELD ## _13); \ 162 } 163 164 #define FIELD_GETTER(NAME, REG, FIELD) \ 165 uint32_t NAME(CPUTriCoreState *env) \ 166 { \ 167 return FIELD_EX32(env->REG, REG, FIELD); \ 168 } 169 170 #define FIELD_SETTER_WITH_FEATURE(NAME, REG, FIELD, FEATURE) \ 171 void NAME(CPUTriCoreState *env, uint32_t val) \ 172 { \ 173 if (tricore_has_feature(env, TRICORE_FEATURE_##FEATURE)) { \ 174 env->REG = FIELD_DP32(env->REG, REG, FIELD ## _ ## FEATURE, val); \ 175 } \ 176 env->REG = FIELD_DP32(env->REG, REG, FIELD ## _13, val); \ 177 } 178 179 #define FIELD_SETTER(NAME, REG, FIELD) \ 180 void NAME(CPUTriCoreState *env, uint32_t val) \ 181 { \ 182 env->REG = FIELD_DP32(env->REG, REG, FIELD, val); \ 183 } 184 185 FIELD_GETTER_WITH_FEATURE(pcxi_get_pcpn, PCXI, PCPN, 161) 186 FIELD_SETTER_WITH_FEATURE(pcxi_set_pcpn, PCXI, PCPN, 161) 187 FIELD_GETTER_WITH_FEATURE(pcxi_get_pie, PCXI, PIE, 161) 188 FIELD_SETTER_WITH_FEATURE(pcxi_set_pie, PCXI, PIE, 161) 189 FIELD_GETTER_WITH_FEATURE(pcxi_get_ul, PCXI, UL, 161) 190 FIELD_SETTER_WITH_FEATURE(pcxi_set_ul, PCXI, UL, 161) 191 FIELD_GETTER(pcxi_get_pcxs, PCXI, PCXS) 192 FIELD_GETTER(pcxi_get_pcxo, PCXI, PCXO) 193 194 FIELD_GETTER_WITH_FEATURE(icr_get_ie, ICR, IE, 161) 195 FIELD_SETTER_WITH_FEATURE(icr_set_ie, ICR, IE, 161) 196 FIELD_GETTER(icr_get_ccpn, ICR, CCPN) 197 FIELD_SETTER(icr_set_ccpn, ICR, CCPN) 198