1 /* 2 * TriCore emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "disas/disas.h" 24 #include "exec/exec-all.h" 25 #include "tcg-op.h" 26 #include "exec/cpu_ldst.h" 27 #include "qemu/qemu-print.h" 28 29 #include "exec/helper-proto.h" 30 #include "exec/helper-gen.h" 31 32 #include "tricore-opcodes.h" 33 #include "exec/log.h" 34 35 /* 36 * TCG registers 37 */ 38 static TCGv cpu_PC; 39 static TCGv cpu_PCXI; 40 static TCGv cpu_PSW; 41 static TCGv cpu_ICR; 42 /* GPR registers */ 43 static TCGv cpu_gpr_a[16]; 44 static TCGv cpu_gpr_d[16]; 45 /* PSW Flag cache */ 46 static TCGv cpu_PSW_C; 47 static TCGv cpu_PSW_V; 48 static TCGv cpu_PSW_SV; 49 static TCGv cpu_PSW_AV; 50 static TCGv cpu_PSW_SAV; 51 52 #include "exec/gen-icount.h" 53 54 static const char *regnames_a[] = { 55 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , 56 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , 57 "a12" , "a13" , "a14" , "a15", 58 }; 59 60 static const char *regnames_d[] = { 61 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" , 62 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" , 63 "d12" , "d13" , "d14" , "d15", 64 }; 65 66 typedef struct DisasContext { 67 struct TranslationBlock *tb; 68 target_ulong pc, saved_pc, next_pc; 69 uint32_t opcode; 70 int singlestep_enabled; 71 /* Routine used to access memory */ 72 int mem_idx; 73 uint32_t hflags, saved_hflags; 74 int bstate; 75 } DisasContext; 76 77 enum { 78 79 BS_NONE = 0, 80 BS_STOP = 1, 81 BS_BRANCH = 2, 82 BS_EXCP = 3, 83 }; 84 85 enum { 86 MODE_LL = 0, 87 MODE_LU = 1, 88 MODE_UL = 2, 89 MODE_UU = 3, 90 }; 91 92 void tricore_cpu_dump_state(CPUState *cs, FILE *f, int flags) 93 { 94 TriCoreCPU *cpu = TRICORE_CPU(cs); 95 CPUTriCoreState *env = &cpu->env; 96 uint32_t psw; 97 int i; 98 99 psw = psw_read(env); 100 101 qemu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC); 102 qemu_fprintf(f, " PSW: " TARGET_FMT_lx, psw); 103 qemu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR); 104 qemu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI); 105 qemu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX); 106 qemu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX); 107 108 for (i = 0; i < 16; ++i) { 109 if ((i & 3) == 0) { 110 qemu_fprintf(f, "\nGPR A%02d:", i); 111 } 112 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]); 113 } 114 for (i = 0; i < 16; ++i) { 115 if ((i & 3) == 0) { 116 qemu_fprintf(f, "\nGPR D%02d:", i); 117 } 118 qemu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]); 119 } 120 qemu_fprintf(f, "\n"); 121 } 122 123 /* 124 * Functions to generate micro-ops 125 */ 126 127 /* Makros for generating helpers */ 128 129 #define gen_helper_1arg(name, arg) do { \ 130 TCGv_i32 helper_tmp = tcg_const_i32(arg); \ 131 gen_helper_##name(cpu_env, helper_tmp); \ 132 tcg_temp_free_i32(helper_tmp); \ 133 } while (0) 134 135 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \ 136 TCGv arg00 = tcg_temp_new(); \ 137 TCGv arg01 = tcg_temp_new(); \ 138 TCGv arg11 = tcg_temp_new(); \ 139 tcg_gen_sari_tl(arg00, arg0, 16); \ 140 tcg_gen_ext16s_tl(arg01, arg0); \ 141 tcg_gen_ext16s_tl(arg11, arg1); \ 142 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 143 tcg_temp_free(arg00); \ 144 tcg_temp_free(arg01); \ 145 tcg_temp_free(arg11); \ 146 } while (0) 147 148 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \ 149 TCGv arg00 = tcg_temp_new(); \ 150 TCGv arg01 = tcg_temp_new(); \ 151 TCGv arg10 = tcg_temp_new(); \ 152 TCGv arg11 = tcg_temp_new(); \ 153 tcg_gen_sari_tl(arg00, arg0, 16); \ 154 tcg_gen_ext16s_tl(arg01, arg0); \ 155 tcg_gen_sari_tl(arg11, arg1, 16); \ 156 tcg_gen_ext16s_tl(arg10, arg1); \ 157 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 158 tcg_temp_free(arg00); \ 159 tcg_temp_free(arg01); \ 160 tcg_temp_free(arg10); \ 161 tcg_temp_free(arg11); \ 162 } while (0) 163 164 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \ 165 TCGv arg00 = tcg_temp_new(); \ 166 TCGv arg01 = tcg_temp_new(); \ 167 TCGv arg10 = tcg_temp_new(); \ 168 TCGv arg11 = tcg_temp_new(); \ 169 tcg_gen_sari_tl(arg00, arg0, 16); \ 170 tcg_gen_ext16s_tl(arg01, arg0); \ 171 tcg_gen_sari_tl(arg10, arg1, 16); \ 172 tcg_gen_ext16s_tl(arg11, arg1); \ 173 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \ 174 tcg_temp_free(arg00); \ 175 tcg_temp_free(arg01); \ 176 tcg_temp_free(arg10); \ 177 tcg_temp_free(arg11); \ 178 } while (0) 179 180 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \ 181 TCGv arg00 = tcg_temp_new(); \ 182 TCGv arg01 = tcg_temp_new(); \ 183 TCGv arg11 = tcg_temp_new(); \ 184 tcg_gen_sari_tl(arg01, arg0, 16); \ 185 tcg_gen_ext16s_tl(arg00, arg0); \ 186 tcg_gen_sari_tl(arg11, arg1, 16); \ 187 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \ 188 tcg_temp_free(arg00); \ 189 tcg_temp_free(arg01); \ 190 tcg_temp_free(arg11); \ 191 } while (0) 192 193 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \ 194 TCGv_i64 ret = tcg_temp_new_i64(); \ 195 TCGv_i64 arg1 = tcg_temp_new_i64(); \ 196 \ 197 tcg_gen_concat_i32_i64(arg1, al1, ah1); \ 198 gen_helper_##name(ret, arg1, arg2); \ 199 tcg_gen_extr_i64_i32(rl, rh, ret); \ 200 \ 201 tcg_temp_free_i64(ret); \ 202 tcg_temp_free_i64(arg1); \ 203 } while (0) 204 205 #define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do { \ 206 TCGv_i64 ret = tcg_temp_new_i64(); \ 207 \ 208 gen_helper_##name(ret, cpu_env, arg1, arg2); \ 209 tcg_gen_extr_i64_i32(rl, rh, ret); \ 210 \ 211 tcg_temp_free_i64(ret); \ 212 } while (0) 213 214 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF)) 215 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \ 216 ((offset & 0x0fffff) << 1)) 217 218 /* For two 32-bit registers used a 64-bit register, the first 219 registernumber needs to be even. Otherwise we trap. */ 220 static inline void generate_trap(DisasContext *ctx, int class, int tin); 221 #define CHECK_REG_PAIR(reg) do { \ 222 if (reg & 0x1) { \ 223 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \ 224 } \ 225 } while (0) 226 227 /* Functions for load/save to/from memory */ 228 229 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2, 230 int16_t con, TCGMemOp mop) 231 { 232 TCGv temp = tcg_temp_new(); 233 tcg_gen_addi_tl(temp, r2, con); 234 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 235 tcg_temp_free(temp); 236 } 237 238 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2, 239 int16_t con, TCGMemOp mop) 240 { 241 TCGv temp = tcg_temp_new(); 242 tcg_gen_addi_tl(temp, r2, con); 243 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 244 tcg_temp_free(temp); 245 } 246 247 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 248 { 249 TCGv_i64 temp = tcg_temp_new_i64(); 250 251 tcg_gen_concat_i32_i64(temp, rl, rh); 252 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ); 253 254 tcg_temp_free_i64(temp); 255 } 256 257 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 258 DisasContext *ctx) 259 { 260 TCGv temp = tcg_temp_new(); 261 tcg_gen_addi_tl(temp, base, con); 262 gen_st_2regs_64(rh, rl, temp, ctx); 263 tcg_temp_free(temp); 264 } 265 266 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx) 267 { 268 TCGv_i64 temp = tcg_temp_new_i64(); 269 270 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ); 271 /* write back to two 32 bit regs */ 272 tcg_gen_extr_i64_i32(rl, rh, temp); 273 274 tcg_temp_free_i64(temp); 275 } 276 277 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con, 278 DisasContext *ctx) 279 { 280 TCGv temp = tcg_temp_new(); 281 tcg_gen_addi_tl(temp, base, con); 282 gen_ld_2regs_64(rh, rl, temp, ctx); 283 tcg_temp_free(temp); 284 } 285 286 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 287 TCGMemOp mop) 288 { 289 TCGv temp = tcg_temp_new(); 290 tcg_gen_addi_tl(temp, r2, off); 291 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop); 292 tcg_gen_mov_tl(r2, temp); 293 tcg_temp_free(temp); 294 } 295 296 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off, 297 TCGMemOp mop) 298 { 299 TCGv temp = tcg_temp_new(); 300 tcg_gen_addi_tl(temp, r2, off); 301 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop); 302 tcg_gen_mov_tl(r2, temp); 303 tcg_temp_free(temp); 304 } 305 306 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */ 307 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea) 308 { 309 TCGv temp = tcg_temp_new(); 310 TCGv temp2 = tcg_temp_new(); 311 312 CHECK_REG_PAIR(ereg); 313 /* temp = (M(EA, word) */ 314 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 315 /* temp = temp & ~E[a][63:32]) */ 316 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]); 317 /* temp2 = (E[a][31:0] & E[a][63:32]); */ 318 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]); 319 /* temp = temp | temp2; */ 320 tcg_gen_or_tl(temp, temp, temp2); 321 /* M(EA, word) = temp; */ 322 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL); 323 324 tcg_temp_free(temp); 325 tcg_temp_free(temp2); 326 } 327 328 /* tmp = M(EA, word); 329 M(EA, word) = D[a]; 330 D[a] = tmp[31:0];*/ 331 static void gen_swap(DisasContext *ctx, int reg, TCGv ea) 332 { 333 TCGv temp = tcg_temp_new(); 334 335 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 336 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL); 337 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 338 339 tcg_temp_free(temp); 340 } 341 342 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea) 343 { 344 TCGv temp = tcg_temp_new(); 345 TCGv temp2 = tcg_temp_new(); 346 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 347 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp, 348 cpu_gpr_d[reg], temp); 349 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 350 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 351 352 tcg_temp_free(temp); 353 tcg_temp_free(temp2); 354 } 355 356 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea) 357 { 358 TCGv temp = tcg_temp_new(); 359 TCGv temp2 = tcg_temp_new(); 360 TCGv temp3 = tcg_temp_new(); 361 362 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL); 363 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]); 364 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]); 365 tcg_gen_or_tl(temp2, temp2, temp3); 366 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL); 367 tcg_gen_mov_tl(cpu_gpr_d[reg], temp); 368 369 tcg_temp_free(temp); 370 tcg_temp_free(temp2); 371 tcg_temp_free(temp3); 372 } 373 374 375 /* We generate loads and store to core special function register (csfr) through 376 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3 377 makros R, A and E, which allow read-only, all and endinit protected access. 378 These makros also specify in which ISA version the csfr was introduced. */ 379 #define R(ADDRESS, REG, FEATURE) \ 380 case ADDRESS: \ 381 if (tricore_feature(env, FEATURE)) { \ 382 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \ 383 } \ 384 break; 385 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 386 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) 387 static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset) 388 { 389 /* since we're caching PSW make this a special case */ 390 if (offset == 0xfe04) { 391 gen_helper_psw_read(ret, cpu_env); 392 } else { 393 switch (offset) { 394 #include "csfr.def" 395 } 396 } 397 } 398 #undef R 399 #undef A 400 #undef E 401 402 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, 403 since no execption occurs */ 404 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ 405 case ADDRESS: \ 406 if (tricore_feature(env, FEATURE)) { \ 407 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \ 408 } \ 409 break; 410 /* Endinit protected registers 411 TODO: Since the endinit bit is in a register of a not yet implemented 412 watchdog device, we handle endinit protected registers like 413 all-access registers for now. */ 414 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE) 415 static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1, 416 int32_t offset) 417 { 418 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { 419 /* since we're caching PSW make this a special case */ 420 if (offset == 0xfe04) { 421 gen_helper_psw_write(cpu_env, r1); 422 } else { 423 switch (offset) { 424 #include "csfr.def" 425 } 426 } 427 } else { 428 /* generate privilege trap */ 429 } 430 } 431 432 /* Functions for arithmetic instructions */ 433 434 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2) 435 { 436 TCGv t0 = tcg_temp_new_i32(); 437 TCGv result = tcg_temp_new_i32(); 438 /* Addition and set V/SV bits */ 439 tcg_gen_add_tl(result, r1, r2); 440 /* calc V bit */ 441 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 442 tcg_gen_xor_tl(t0, r1, r2); 443 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 444 /* Calc SV bit */ 445 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 446 /* Calc AV/SAV bits */ 447 tcg_gen_add_tl(cpu_PSW_AV, result, result); 448 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 449 /* calc SAV */ 450 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 451 /* write back result */ 452 tcg_gen_mov_tl(ret, result); 453 454 tcg_temp_free(result); 455 tcg_temp_free(t0); 456 } 457 458 static inline void 459 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 460 { 461 TCGv temp = tcg_temp_new(); 462 TCGv_i64 t0 = tcg_temp_new_i64(); 463 TCGv_i64 t1 = tcg_temp_new_i64(); 464 TCGv_i64 result = tcg_temp_new_i64(); 465 466 tcg_gen_add_i64(result, r1, r2); 467 /* calc v bit */ 468 tcg_gen_xor_i64(t1, result, r1); 469 tcg_gen_xor_i64(t0, r1, r2); 470 tcg_gen_andc_i64(t1, t1, t0); 471 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 472 /* calc SV bit */ 473 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 474 /* calc AV/SAV bits */ 475 tcg_gen_extrh_i64_i32(temp, result); 476 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 477 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 478 /* calc SAV */ 479 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 480 /* write back result */ 481 tcg_gen_mov_i64(ret, result); 482 483 tcg_temp_free(temp); 484 tcg_temp_free_i64(result); 485 tcg_temp_free_i64(t0); 486 tcg_temp_free_i64(t1); 487 } 488 489 static inline void 490 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 491 TCGv r3, void(*op1)(TCGv, TCGv, TCGv), 492 void(*op2)(TCGv, TCGv, TCGv)) 493 { 494 TCGv temp = tcg_temp_new(); 495 TCGv temp2 = tcg_temp_new(); 496 TCGv temp3 = tcg_temp_new(); 497 TCGv temp4 = tcg_temp_new(); 498 499 (*op1)(temp, r1_low, r2); 500 /* calc V0 bit */ 501 tcg_gen_xor_tl(temp2, temp, r1_low); 502 tcg_gen_xor_tl(temp3, r1_low, r2); 503 if (op1 == tcg_gen_add_tl) { 504 tcg_gen_andc_tl(temp2, temp2, temp3); 505 } else { 506 tcg_gen_and_tl(temp2, temp2, temp3); 507 } 508 509 (*op2)(temp3, r1_high, r3); 510 /* calc V1 bit */ 511 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high); 512 tcg_gen_xor_tl(temp4, r1_high, r3); 513 if (op2 == tcg_gen_add_tl) { 514 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4); 515 } else { 516 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4); 517 } 518 /* combine V0/V1 bits */ 519 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2); 520 /* calc sv bit */ 521 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 522 /* write result */ 523 tcg_gen_mov_tl(ret_low, temp); 524 tcg_gen_mov_tl(ret_high, temp3); 525 /* calc AV bit */ 526 tcg_gen_add_tl(temp, ret_low, ret_low); 527 tcg_gen_xor_tl(temp, temp, ret_low); 528 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 529 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high); 530 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 531 /* calc SAV bit */ 532 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 533 534 tcg_temp_free(temp); 535 tcg_temp_free(temp2); 536 tcg_temp_free(temp3); 537 tcg_temp_free(temp4); 538 } 539 540 /* ret = r2 + (r1 * r3); */ 541 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 542 { 543 TCGv_i64 t1 = tcg_temp_new_i64(); 544 TCGv_i64 t2 = tcg_temp_new_i64(); 545 TCGv_i64 t3 = tcg_temp_new_i64(); 546 547 tcg_gen_ext_i32_i64(t1, r1); 548 tcg_gen_ext_i32_i64(t2, r2); 549 tcg_gen_ext_i32_i64(t3, r3); 550 551 tcg_gen_mul_i64(t1, t1, t3); 552 tcg_gen_add_i64(t1, t2, t1); 553 554 tcg_gen_extrl_i64_i32(ret, t1); 555 /* calc V 556 t1 > 0x7fffffff */ 557 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 558 /* t1 < -0x80000000 */ 559 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 560 tcg_gen_or_i64(t2, t2, t3); 561 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 562 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 563 /* Calc SV bit */ 564 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 565 /* Calc AV/SAV bits */ 566 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 567 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 568 /* calc SAV */ 569 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 570 571 tcg_temp_free_i64(t1); 572 tcg_temp_free_i64(t2); 573 tcg_temp_free_i64(t3); 574 } 575 576 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 577 { 578 TCGv temp = tcg_const_i32(con); 579 gen_madd32_d(ret, r1, r2, temp); 580 tcg_temp_free(temp); 581 } 582 583 static inline void 584 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 585 TCGv r3) 586 { 587 TCGv t1 = tcg_temp_new(); 588 TCGv t2 = tcg_temp_new(); 589 TCGv t3 = tcg_temp_new(); 590 TCGv t4 = tcg_temp_new(); 591 592 tcg_gen_muls2_tl(t1, t2, r1, r3); 593 /* only the add can overflow */ 594 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2); 595 /* calc V bit */ 596 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 597 tcg_gen_xor_tl(t1, r2_high, t2); 598 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1); 599 /* Calc SV bit */ 600 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 601 /* Calc AV/SAV bits */ 602 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 603 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 604 /* calc SAV */ 605 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 606 /* write back the result */ 607 tcg_gen_mov_tl(ret_low, t3); 608 tcg_gen_mov_tl(ret_high, t4); 609 610 tcg_temp_free(t1); 611 tcg_temp_free(t2); 612 tcg_temp_free(t3); 613 tcg_temp_free(t4); 614 } 615 616 static inline void 617 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 618 TCGv r3) 619 { 620 TCGv_i64 t1 = tcg_temp_new_i64(); 621 TCGv_i64 t2 = tcg_temp_new_i64(); 622 TCGv_i64 t3 = tcg_temp_new_i64(); 623 624 tcg_gen_extu_i32_i64(t1, r1); 625 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 626 tcg_gen_extu_i32_i64(t3, r3); 627 628 tcg_gen_mul_i64(t1, t1, t3); 629 tcg_gen_add_i64(t2, t2, t1); 630 /* write back result */ 631 tcg_gen_extr_i64_i32(ret_low, ret_high, t2); 632 /* only the add overflows, if t2 < t1 633 calc V bit */ 634 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1); 635 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 636 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 637 /* Calc SV bit */ 638 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 639 /* Calc AV/SAV bits */ 640 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 641 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 642 /* calc SAV */ 643 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 644 645 tcg_temp_free_i64(t1); 646 tcg_temp_free_i64(t2); 647 tcg_temp_free_i64(t3); 648 } 649 650 static inline void 651 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 652 int32_t con) 653 { 654 TCGv temp = tcg_const_i32(con); 655 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 656 tcg_temp_free(temp); 657 } 658 659 static inline void 660 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 661 int32_t con) 662 { 663 TCGv temp = tcg_const_i32(con); 664 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 665 tcg_temp_free(temp); 666 } 667 668 static inline void 669 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 670 TCGv r3, uint32_t n, uint32_t mode) 671 { 672 TCGv temp = tcg_const_i32(n); 673 TCGv temp2 = tcg_temp_new(); 674 TCGv_i64 temp64 = tcg_temp_new_i64(); 675 switch (mode) { 676 case MODE_LL: 677 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 678 break; 679 case MODE_LU: 680 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 681 break; 682 case MODE_UL: 683 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 684 break; 685 case MODE_UU: 686 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 687 break; 688 } 689 tcg_gen_extr_i64_i32(temp, temp2, temp64); 690 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 691 tcg_gen_add_tl, tcg_gen_add_tl); 692 tcg_temp_free(temp); 693 tcg_temp_free(temp2); 694 tcg_temp_free_i64(temp64); 695 } 696 697 static inline void 698 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 699 TCGv r3, uint32_t n, uint32_t mode) 700 { 701 TCGv temp = tcg_const_i32(n); 702 TCGv temp2 = tcg_temp_new(); 703 TCGv_i64 temp64 = tcg_temp_new_i64(); 704 switch (mode) { 705 case MODE_LL: 706 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 707 break; 708 case MODE_LU: 709 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 710 break; 711 case MODE_UL: 712 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 713 break; 714 case MODE_UU: 715 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 716 break; 717 } 718 tcg_gen_extr_i64_i32(temp, temp2, temp64); 719 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 720 tcg_gen_sub_tl, tcg_gen_add_tl); 721 tcg_temp_free(temp); 722 tcg_temp_free(temp2); 723 tcg_temp_free_i64(temp64); 724 } 725 726 static inline void 727 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 728 TCGv r3, uint32_t n, uint32_t mode) 729 { 730 TCGv temp = tcg_const_i32(n); 731 TCGv_i64 temp64 = tcg_temp_new_i64(); 732 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 733 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 734 switch (mode) { 735 case MODE_LL: 736 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 737 break; 738 case MODE_LU: 739 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 740 break; 741 case MODE_UL: 742 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 743 break; 744 case MODE_UU: 745 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 746 break; 747 } 748 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 749 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 750 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 751 tcg_gen_sub_i64(temp64, temp64_2, temp64); 752 tcg_gen_shli_i64(temp64, temp64, 16); 753 754 gen_add64_d(temp64_2, temp64_3, temp64); 755 /* write back result */ 756 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 757 758 tcg_temp_free(temp); 759 tcg_temp_free_i64(temp64); 760 tcg_temp_free_i64(temp64_2); 761 tcg_temp_free_i64(temp64_3); 762 } 763 764 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2); 765 766 static inline void 767 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 768 TCGv r3, uint32_t n, uint32_t mode) 769 { 770 TCGv temp = tcg_const_i32(n); 771 TCGv temp2 = tcg_temp_new(); 772 TCGv temp3 = tcg_temp_new(); 773 TCGv_i64 temp64 = tcg_temp_new_i64(); 774 775 switch (mode) { 776 case MODE_LL: 777 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 778 break; 779 case MODE_LU: 780 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 781 break; 782 case MODE_UL: 783 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 784 break; 785 case MODE_UU: 786 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 787 break; 788 } 789 tcg_gen_extr_i64_i32(temp, temp2, temp64); 790 gen_adds(ret_low, r1_low, temp); 791 tcg_gen_mov_tl(temp, cpu_PSW_V); 792 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 793 gen_adds(ret_high, r1_high, temp2); 794 /* combine v bits */ 795 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 796 /* combine av bits */ 797 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 798 799 tcg_temp_free(temp); 800 tcg_temp_free(temp2); 801 tcg_temp_free(temp3); 802 tcg_temp_free_i64(temp64); 803 804 } 805 806 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2); 807 808 static inline void 809 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 810 TCGv r3, uint32_t n, uint32_t mode) 811 { 812 TCGv temp = tcg_const_i32(n); 813 TCGv temp2 = tcg_temp_new(); 814 TCGv temp3 = tcg_temp_new(); 815 TCGv_i64 temp64 = tcg_temp_new_i64(); 816 817 switch (mode) { 818 case MODE_LL: 819 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 820 break; 821 case MODE_LU: 822 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 823 break; 824 case MODE_UL: 825 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 826 break; 827 case MODE_UU: 828 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 829 break; 830 } 831 tcg_gen_extr_i64_i32(temp, temp2, temp64); 832 gen_subs(ret_low, r1_low, temp); 833 tcg_gen_mov_tl(temp, cpu_PSW_V); 834 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 835 gen_adds(ret_high, r1_high, temp2); 836 /* combine v bits */ 837 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 838 /* combine av bits */ 839 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 840 841 tcg_temp_free(temp); 842 tcg_temp_free(temp2); 843 tcg_temp_free(temp3); 844 tcg_temp_free_i64(temp64); 845 846 } 847 848 static inline void 849 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 850 TCGv r3, uint32_t n, uint32_t mode) 851 { 852 TCGv temp = tcg_const_i32(n); 853 TCGv_i64 temp64 = tcg_temp_new_i64(); 854 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 855 856 switch (mode) { 857 case MODE_LL: 858 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 859 break; 860 case MODE_LU: 861 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 862 break; 863 case MODE_UL: 864 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 865 break; 866 case MODE_UU: 867 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 868 break; 869 } 870 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 871 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 872 tcg_gen_sub_i64(temp64, temp64_2, temp64); 873 tcg_gen_shli_i64(temp64, temp64, 16); 874 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 875 876 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 877 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 878 879 tcg_temp_free(temp); 880 tcg_temp_free_i64(temp64); 881 tcg_temp_free_i64(temp64_2); 882 } 883 884 885 static inline void 886 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 887 TCGv r3, uint32_t n, uint32_t mode) 888 { 889 TCGv temp = tcg_const_i32(n); 890 TCGv_i64 temp64 = tcg_temp_new_i64(); 891 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 892 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 893 switch (mode) { 894 case MODE_LL: 895 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 896 break; 897 case MODE_LU: 898 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 899 break; 900 case MODE_UL: 901 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 902 break; 903 case MODE_UU: 904 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 905 break; 906 } 907 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 908 gen_add64_d(temp64_3, temp64_2, temp64); 909 /* write back result */ 910 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 911 912 tcg_temp_free(temp); 913 tcg_temp_free_i64(temp64); 914 tcg_temp_free_i64(temp64_2); 915 tcg_temp_free_i64(temp64_3); 916 } 917 918 static inline void 919 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 920 TCGv r3, uint32_t n, uint32_t mode) 921 { 922 TCGv temp = tcg_const_i32(n); 923 TCGv_i64 temp64 = tcg_temp_new_i64(); 924 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 925 switch (mode) { 926 case MODE_LL: 927 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 928 break; 929 case MODE_LU: 930 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 931 break; 932 case MODE_UL: 933 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 934 break; 935 case MODE_UU: 936 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 937 break; 938 } 939 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 940 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64); 941 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 942 943 tcg_temp_free(temp); 944 tcg_temp_free_i64(temp64); 945 tcg_temp_free_i64(temp64_2); 946 } 947 948 static inline void 949 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 950 uint32_t mode) 951 { 952 TCGv temp = tcg_const_i32(n); 953 TCGv_i64 temp64 = tcg_temp_new_i64(); 954 switch (mode) { 955 case MODE_LL: 956 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 957 break; 958 case MODE_LU: 959 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 960 break; 961 case MODE_UL: 962 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 963 break; 964 case MODE_UU: 965 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 966 break; 967 } 968 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high); 969 970 tcg_temp_free(temp); 971 tcg_temp_free_i64(temp64); 972 } 973 974 static inline void 975 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 976 { 977 TCGv temp = tcg_temp_new(); 978 TCGv temp2 = tcg_temp_new(); 979 980 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 981 tcg_gen_shli_tl(temp, r1, 16); 982 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode); 983 984 tcg_temp_free(temp); 985 tcg_temp_free(temp2); 986 } 987 988 static inline void 989 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 990 { 991 TCGv temp = tcg_const_i32(n); 992 TCGv temp2 = tcg_temp_new(); 993 TCGv_i64 temp64 = tcg_temp_new_i64(); 994 switch (mode) { 995 case MODE_LL: 996 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 997 break; 998 case MODE_LU: 999 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1000 break; 1001 case MODE_UL: 1002 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1003 break; 1004 case MODE_UU: 1005 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1006 break; 1007 } 1008 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1009 tcg_gen_shli_tl(temp, r1, 16); 1010 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2); 1011 1012 tcg_temp_free(temp); 1013 tcg_temp_free(temp2); 1014 tcg_temp_free_i64(temp64); 1015 } 1016 1017 1018 static inline void 1019 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1020 uint32_t n, uint32_t mode) 1021 { 1022 TCGv temp = tcg_const_i32(n); 1023 TCGv_i64 temp64 = tcg_temp_new_i64(); 1024 switch (mode) { 1025 case MODE_LL: 1026 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1027 break; 1028 case MODE_LU: 1029 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1030 break; 1031 case MODE_UL: 1032 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1033 break; 1034 case MODE_UU: 1035 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1036 break; 1037 } 1038 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 1039 1040 tcg_temp_free(temp); 1041 tcg_temp_free_i64(temp64); 1042 } 1043 1044 static inline void 1045 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1046 { 1047 TCGv temp = tcg_temp_new(); 1048 TCGv temp2 = tcg_temp_new(); 1049 1050 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1051 tcg_gen_shli_tl(temp, r1, 16); 1052 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode); 1053 1054 tcg_temp_free(temp); 1055 tcg_temp_free(temp2); 1056 } 1057 1058 static inline void 1059 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1060 { 1061 TCGv temp = tcg_const_i32(n); 1062 TCGv temp2 = tcg_temp_new(); 1063 TCGv_i64 temp64 = tcg_temp_new_i64(); 1064 switch (mode) { 1065 case MODE_LL: 1066 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1067 break; 1068 case MODE_LU: 1069 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1070 break; 1071 case MODE_UL: 1072 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1073 break; 1074 case MODE_UU: 1075 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1076 break; 1077 } 1078 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1079 tcg_gen_shli_tl(temp, r1, 16); 1080 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2); 1081 1082 tcg_temp_free(temp); 1083 tcg_temp_free(temp2); 1084 tcg_temp_free_i64(temp64); 1085 } 1086 1087 static inline void 1088 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1089 { 1090 TCGv temp = tcg_const_i32(n); 1091 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp); 1092 tcg_temp_free(temp); 1093 } 1094 1095 static inline void 1096 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1097 { 1098 TCGv temp = tcg_const_i32(n); 1099 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp); 1100 tcg_temp_free(temp); 1101 } 1102 1103 static inline void 1104 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1105 uint32_t up_shift, CPUTriCoreState *env) 1106 { 1107 TCGv temp = tcg_temp_new(); 1108 TCGv temp2 = tcg_temp_new(); 1109 TCGv temp3 = tcg_temp_new(); 1110 TCGv_i64 t1 = tcg_temp_new_i64(); 1111 TCGv_i64 t2 = tcg_temp_new_i64(); 1112 TCGv_i64 t3 = tcg_temp_new_i64(); 1113 1114 tcg_gen_ext_i32_i64(t2, arg2); 1115 tcg_gen_ext_i32_i64(t3, arg3); 1116 1117 tcg_gen_mul_i64(t2, t2, t3); 1118 tcg_gen_shli_i64(t2, t2, n); 1119 1120 tcg_gen_ext_i32_i64(t1, arg1); 1121 tcg_gen_sari_i64(t2, t2, up_shift); 1122 1123 tcg_gen_add_i64(t3, t1, t2); 1124 tcg_gen_extrl_i64_i32(temp3, t3); 1125 /* calc v bit */ 1126 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1127 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1128 tcg_gen_or_i64(t1, t1, t2); 1129 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1130 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1131 /* We produce an overflow on the host if the mul before was 1132 (0x80000000 * 0x80000000) << 1). If this is the 1133 case, we negate the ovf. */ 1134 if (n == 1) { 1135 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1136 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1137 tcg_gen_and_tl(temp, temp, temp2); 1138 tcg_gen_shli_tl(temp, temp, 31); 1139 /* negate v bit, if special condition */ 1140 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1141 } 1142 /* Calc SV bit */ 1143 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1144 /* Calc AV/SAV bits */ 1145 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1146 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1147 /* calc SAV */ 1148 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1149 /* write back result */ 1150 tcg_gen_mov_tl(ret, temp3); 1151 1152 tcg_temp_free(temp); 1153 tcg_temp_free(temp2); 1154 tcg_temp_free(temp3); 1155 tcg_temp_free_i64(t1); 1156 tcg_temp_free_i64(t2); 1157 tcg_temp_free_i64(t3); 1158 } 1159 1160 static inline void 1161 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1162 { 1163 TCGv temp = tcg_temp_new(); 1164 TCGv temp2 = tcg_temp_new(); 1165 if (n == 0) { 1166 tcg_gen_mul_tl(temp, arg2, arg3); 1167 } else { /* n is expected to be 1 */ 1168 tcg_gen_mul_tl(temp, arg2, arg3); 1169 tcg_gen_shli_tl(temp, temp, 1); 1170 /* catch special case r1 = r2 = 0x8000 */ 1171 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1172 tcg_gen_sub_tl(temp, temp, temp2); 1173 } 1174 gen_add_d(ret, arg1, temp); 1175 1176 tcg_temp_free(temp); 1177 tcg_temp_free(temp2); 1178 } 1179 1180 static inline void 1181 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 1182 { 1183 TCGv temp = tcg_temp_new(); 1184 TCGv temp2 = tcg_temp_new(); 1185 if (n == 0) { 1186 tcg_gen_mul_tl(temp, arg2, arg3); 1187 } else { /* n is expected to be 1 */ 1188 tcg_gen_mul_tl(temp, arg2, arg3); 1189 tcg_gen_shli_tl(temp, temp, 1); 1190 /* catch special case r1 = r2 = 0x8000 */ 1191 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1192 tcg_gen_sub_tl(temp, temp, temp2); 1193 } 1194 gen_adds(ret, arg1, temp); 1195 1196 tcg_temp_free(temp); 1197 tcg_temp_free(temp2); 1198 } 1199 1200 static inline void 1201 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1202 TCGv arg3, uint32_t n) 1203 { 1204 TCGv temp = tcg_temp_new(); 1205 TCGv temp2 = tcg_temp_new(); 1206 TCGv_i64 t1 = tcg_temp_new_i64(); 1207 TCGv_i64 t2 = tcg_temp_new_i64(); 1208 TCGv_i64 t3 = tcg_temp_new_i64(); 1209 1210 if (n == 0) { 1211 tcg_gen_mul_tl(temp, arg2, arg3); 1212 } else { /* n is expected to be 1 */ 1213 tcg_gen_mul_tl(temp, arg2, arg3); 1214 tcg_gen_shli_tl(temp, temp, 1); 1215 /* catch special case r1 = r2 = 0x8000 */ 1216 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1217 tcg_gen_sub_tl(temp, temp, temp2); 1218 } 1219 tcg_gen_ext_i32_i64(t2, temp); 1220 tcg_gen_shli_i64(t2, t2, 16); 1221 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1222 gen_add64_d(t3, t1, t2); 1223 /* write back result */ 1224 tcg_gen_extr_i64_i32(rl, rh, t3); 1225 1226 tcg_temp_free_i64(t1); 1227 tcg_temp_free_i64(t2); 1228 tcg_temp_free_i64(t3); 1229 tcg_temp_free(temp); 1230 tcg_temp_free(temp2); 1231 } 1232 1233 static inline void 1234 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1235 TCGv arg3, uint32_t n) 1236 { 1237 TCGv temp = tcg_temp_new(); 1238 TCGv temp2 = tcg_temp_new(); 1239 TCGv_i64 t1 = tcg_temp_new_i64(); 1240 TCGv_i64 t2 = tcg_temp_new_i64(); 1241 1242 if (n == 0) { 1243 tcg_gen_mul_tl(temp, arg2, arg3); 1244 } else { /* n is expected to be 1 */ 1245 tcg_gen_mul_tl(temp, arg2, arg3); 1246 tcg_gen_shli_tl(temp, temp, 1); 1247 /* catch special case r1 = r2 = 0x8000 */ 1248 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 1249 tcg_gen_sub_tl(temp, temp, temp2); 1250 } 1251 tcg_gen_ext_i32_i64(t2, temp); 1252 tcg_gen_shli_i64(t2, t2, 16); 1253 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1254 1255 gen_helper_add64_ssov(t1, cpu_env, t1, t2); 1256 tcg_gen_extr_i64_i32(rl, rh, t1); 1257 1258 tcg_temp_free(temp); 1259 tcg_temp_free(temp2); 1260 tcg_temp_free_i64(t1); 1261 tcg_temp_free_i64(t2); 1262 } 1263 1264 static inline void 1265 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1266 TCGv arg3, uint32_t n, CPUTriCoreState *env) 1267 { 1268 TCGv_i64 t1 = tcg_temp_new_i64(); 1269 TCGv_i64 t2 = tcg_temp_new_i64(); 1270 TCGv_i64 t3 = tcg_temp_new_i64(); 1271 TCGv_i64 t4 = tcg_temp_new_i64(); 1272 TCGv temp, temp2; 1273 1274 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 1275 tcg_gen_ext_i32_i64(t2, arg2); 1276 tcg_gen_ext_i32_i64(t3, arg3); 1277 1278 tcg_gen_mul_i64(t2, t2, t3); 1279 if (n != 0) { 1280 tcg_gen_shli_i64(t2, t2, 1); 1281 } 1282 tcg_gen_add_i64(t4, t1, t2); 1283 /* calc v bit */ 1284 tcg_gen_xor_i64(t3, t4, t1); 1285 tcg_gen_xor_i64(t2, t1, t2); 1286 tcg_gen_andc_i64(t3, t3, t2); 1287 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 1288 /* We produce an overflow on the host if the mul before was 1289 (0x80000000 * 0x80000000) << 1). If this is the 1290 case, we negate the ovf. */ 1291 if (n == 1) { 1292 temp = tcg_temp_new(); 1293 temp2 = tcg_temp_new(); 1294 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 1295 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 1296 tcg_gen_and_tl(temp, temp, temp2); 1297 tcg_gen_shli_tl(temp, temp, 31); 1298 /* negate v bit, if special condition */ 1299 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 1300 1301 tcg_temp_free(temp); 1302 tcg_temp_free(temp2); 1303 } 1304 /* write back result */ 1305 tcg_gen_extr_i64_i32(rl, rh, t4); 1306 /* Calc SV bit */ 1307 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1308 /* Calc AV/SAV bits */ 1309 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 1310 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 1311 /* calc SAV */ 1312 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1313 1314 tcg_temp_free_i64(t1); 1315 tcg_temp_free_i64(t2); 1316 tcg_temp_free_i64(t3); 1317 tcg_temp_free_i64(t4); 1318 } 1319 1320 static inline void 1321 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1322 uint32_t up_shift) 1323 { 1324 TCGv_i64 t1 = tcg_temp_new_i64(); 1325 TCGv_i64 t2 = tcg_temp_new_i64(); 1326 TCGv_i64 t3 = tcg_temp_new_i64(); 1327 1328 tcg_gen_ext_i32_i64(t1, arg1); 1329 tcg_gen_ext_i32_i64(t2, arg2); 1330 tcg_gen_ext_i32_i64(t3, arg3); 1331 1332 tcg_gen_mul_i64(t2, t2, t3); 1333 tcg_gen_sari_i64(t2, t2, up_shift - n); 1334 1335 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2); 1336 1337 tcg_temp_free_i64(t1); 1338 tcg_temp_free_i64(t2); 1339 tcg_temp_free_i64(t3); 1340 } 1341 1342 static inline void 1343 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 1344 TCGv arg3, uint32_t n) 1345 { 1346 TCGv_i64 r1 = tcg_temp_new_i64(); 1347 TCGv temp = tcg_const_i32(n); 1348 1349 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 1350 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); 1351 tcg_gen_extr_i64_i32(rl, rh, r1); 1352 1353 tcg_temp_free_i64(r1); 1354 tcg_temp_free(temp); 1355 } 1356 /* ret = r2 - (r1 * r3); */ 1357 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3) 1358 { 1359 TCGv_i64 t1 = tcg_temp_new_i64(); 1360 TCGv_i64 t2 = tcg_temp_new_i64(); 1361 TCGv_i64 t3 = tcg_temp_new_i64(); 1362 1363 tcg_gen_ext_i32_i64(t1, r1); 1364 tcg_gen_ext_i32_i64(t2, r2); 1365 tcg_gen_ext_i32_i64(t3, r3); 1366 1367 tcg_gen_mul_i64(t1, t1, t3); 1368 tcg_gen_sub_i64(t1, t2, t1); 1369 1370 tcg_gen_extrl_i64_i32(ret, t1); 1371 /* calc V 1372 t2 > 0x7fffffff */ 1373 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL); 1374 /* result < -0x80000000 */ 1375 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL); 1376 tcg_gen_or_i64(t2, t2, t3); 1377 tcg_gen_extrl_i64_i32(cpu_PSW_V, t2); 1378 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1379 1380 /* Calc SV bit */ 1381 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1382 /* Calc AV/SAV bits */ 1383 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 1384 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 1385 /* calc SAV */ 1386 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1387 1388 tcg_temp_free_i64(t1); 1389 tcg_temp_free_i64(t2); 1390 tcg_temp_free_i64(t3); 1391 } 1392 1393 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con) 1394 { 1395 TCGv temp = tcg_const_i32(con); 1396 gen_msub32_d(ret, r1, r2, temp); 1397 tcg_temp_free(temp); 1398 } 1399 1400 static inline void 1401 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1402 TCGv r3) 1403 { 1404 TCGv t1 = tcg_temp_new(); 1405 TCGv t2 = tcg_temp_new(); 1406 TCGv t3 = tcg_temp_new(); 1407 TCGv t4 = tcg_temp_new(); 1408 1409 tcg_gen_muls2_tl(t1, t2, r1, r3); 1410 /* only the sub can overflow */ 1411 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2); 1412 /* calc V bit */ 1413 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high); 1414 tcg_gen_xor_tl(t1, r2_high, t2); 1415 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1); 1416 /* Calc SV bit */ 1417 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1418 /* Calc AV/SAV bits */ 1419 tcg_gen_add_tl(cpu_PSW_AV, t4, t4); 1420 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV); 1421 /* calc SAV */ 1422 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1423 /* write back the result */ 1424 tcg_gen_mov_tl(ret_low, t3); 1425 tcg_gen_mov_tl(ret_high, t4); 1426 1427 tcg_temp_free(t1); 1428 tcg_temp_free(t2); 1429 tcg_temp_free(t3); 1430 tcg_temp_free(t4); 1431 } 1432 1433 static inline void 1434 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1435 int32_t con) 1436 { 1437 TCGv temp = tcg_const_i32(con); 1438 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1439 tcg_temp_free(temp); 1440 } 1441 1442 static inline void 1443 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1444 TCGv r3) 1445 { 1446 TCGv_i64 t1 = tcg_temp_new_i64(); 1447 TCGv_i64 t2 = tcg_temp_new_i64(); 1448 TCGv_i64 t3 = tcg_temp_new_i64(); 1449 1450 tcg_gen_extu_i32_i64(t1, r1); 1451 tcg_gen_concat_i32_i64(t2, r2_low, r2_high); 1452 tcg_gen_extu_i32_i64(t3, r3); 1453 1454 tcg_gen_mul_i64(t1, t1, t3); 1455 tcg_gen_sub_i64(t3, t2, t1); 1456 tcg_gen_extr_i64_i32(ret_low, ret_high, t3); 1457 /* calc V bit, only the sub can overflow, if t1 > t2 */ 1458 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2); 1459 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1460 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1461 /* Calc SV bit */ 1462 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1463 /* Calc AV/SAV bits */ 1464 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 1465 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 1466 /* calc SAV */ 1467 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1468 1469 tcg_temp_free_i64(t1); 1470 tcg_temp_free_i64(t2); 1471 tcg_temp_free_i64(t3); 1472 } 1473 1474 static inline void 1475 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 1476 int32_t con) 1477 { 1478 TCGv temp = tcg_const_i32(con); 1479 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp); 1480 tcg_temp_free(temp); 1481 } 1482 1483 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2) 1484 { 1485 TCGv temp = tcg_const_i32(r2); 1486 gen_add_d(ret, r1, temp); 1487 tcg_temp_free(temp); 1488 } 1489 /* calculate the carry bit too */ 1490 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2) 1491 { 1492 TCGv t0 = tcg_temp_new_i32(); 1493 TCGv result = tcg_temp_new_i32(); 1494 1495 tcg_gen_movi_tl(t0, 0); 1496 /* Addition and set C/V/SV bits */ 1497 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0); 1498 /* calc V bit */ 1499 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1500 tcg_gen_xor_tl(t0, r1, r2); 1501 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1502 /* Calc SV bit */ 1503 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1504 /* Calc AV/SAV bits */ 1505 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1506 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1507 /* calc SAV */ 1508 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1509 /* write back result */ 1510 tcg_gen_mov_tl(ret, result); 1511 1512 tcg_temp_free(result); 1513 tcg_temp_free(t0); 1514 } 1515 1516 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con) 1517 { 1518 TCGv temp = tcg_const_i32(con); 1519 gen_add_CC(ret, r1, temp); 1520 tcg_temp_free(temp); 1521 } 1522 1523 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2) 1524 { 1525 TCGv carry = tcg_temp_new_i32(); 1526 TCGv t0 = tcg_temp_new_i32(); 1527 TCGv result = tcg_temp_new_i32(); 1528 1529 tcg_gen_movi_tl(t0, 0); 1530 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0); 1531 /* Addition, carry and set C/V/SV bits */ 1532 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0); 1533 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0); 1534 /* calc V bit */ 1535 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1536 tcg_gen_xor_tl(t0, r1, r2); 1537 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0); 1538 /* Calc SV bit */ 1539 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1540 /* Calc AV/SAV bits */ 1541 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1542 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1543 /* calc SAV */ 1544 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1545 /* write back result */ 1546 tcg_gen_mov_tl(ret, result); 1547 1548 tcg_temp_free(result); 1549 tcg_temp_free(t0); 1550 tcg_temp_free(carry); 1551 } 1552 1553 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con) 1554 { 1555 TCGv temp = tcg_const_i32(con); 1556 gen_addc_CC(ret, r1, temp); 1557 tcg_temp_free(temp); 1558 } 1559 1560 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1561 TCGv r4) 1562 { 1563 TCGv temp = tcg_temp_new(); 1564 TCGv temp2 = tcg_temp_new(); 1565 TCGv result = tcg_temp_new(); 1566 TCGv mask = tcg_temp_new(); 1567 TCGv t0 = tcg_const_i32(0); 1568 1569 /* create mask for sticky bits */ 1570 tcg_gen_setcond_tl(cond, mask, r4, t0); 1571 tcg_gen_shli_tl(mask, mask, 31); 1572 1573 tcg_gen_add_tl(result, r1, r2); 1574 /* Calc PSW_V */ 1575 tcg_gen_xor_tl(temp, result, r1); 1576 tcg_gen_xor_tl(temp2, r1, r2); 1577 tcg_gen_andc_tl(temp, temp, temp2); 1578 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1579 /* Set PSW_SV */ 1580 tcg_gen_and_tl(temp, temp, mask); 1581 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1582 /* calc AV bit */ 1583 tcg_gen_add_tl(temp, result, result); 1584 tcg_gen_xor_tl(temp, temp, result); 1585 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1586 /* calc SAV bit */ 1587 tcg_gen_and_tl(temp, temp, mask); 1588 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1589 /* write back result */ 1590 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1591 1592 tcg_temp_free(t0); 1593 tcg_temp_free(temp); 1594 tcg_temp_free(temp2); 1595 tcg_temp_free(result); 1596 tcg_temp_free(mask); 1597 } 1598 1599 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2, 1600 TCGv r3, TCGv r4) 1601 { 1602 TCGv temp = tcg_const_i32(r2); 1603 gen_cond_add(cond, r1, temp, r3, r4); 1604 tcg_temp_free(temp); 1605 } 1606 1607 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2) 1608 { 1609 TCGv temp = tcg_temp_new_i32(); 1610 TCGv result = tcg_temp_new_i32(); 1611 1612 tcg_gen_sub_tl(result, r1, r2); 1613 /* calc V bit */ 1614 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1615 tcg_gen_xor_tl(temp, r1, r2); 1616 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1617 /* calc SV bit */ 1618 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1619 /* Calc AV bit */ 1620 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1621 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1622 /* calc SAV bit */ 1623 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1624 /* write back result */ 1625 tcg_gen_mov_tl(ret, result); 1626 1627 tcg_temp_free(temp); 1628 tcg_temp_free(result); 1629 } 1630 1631 static inline void 1632 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2) 1633 { 1634 TCGv temp = tcg_temp_new(); 1635 TCGv_i64 t0 = tcg_temp_new_i64(); 1636 TCGv_i64 t1 = tcg_temp_new_i64(); 1637 TCGv_i64 result = tcg_temp_new_i64(); 1638 1639 tcg_gen_sub_i64(result, r1, r2); 1640 /* calc v bit */ 1641 tcg_gen_xor_i64(t1, result, r1); 1642 tcg_gen_xor_i64(t0, r1, r2); 1643 tcg_gen_and_i64(t1, t1, t0); 1644 tcg_gen_extrh_i64_i32(cpu_PSW_V, t1); 1645 /* calc SV bit */ 1646 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1647 /* calc AV/SAV bits */ 1648 tcg_gen_extrh_i64_i32(temp, result); 1649 tcg_gen_add_tl(cpu_PSW_AV, temp, temp); 1650 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV); 1651 /* calc SAV */ 1652 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1653 /* write back result */ 1654 tcg_gen_mov_i64(ret, result); 1655 1656 tcg_temp_free(temp); 1657 tcg_temp_free_i64(result); 1658 tcg_temp_free_i64(t0); 1659 tcg_temp_free_i64(t1); 1660 } 1661 1662 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2) 1663 { 1664 TCGv result = tcg_temp_new(); 1665 TCGv temp = tcg_temp_new(); 1666 1667 tcg_gen_sub_tl(result, r1, r2); 1668 /* calc C bit */ 1669 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2); 1670 /* calc V bit */ 1671 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 1672 tcg_gen_xor_tl(temp, r1, r2); 1673 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 1674 /* calc SV bit */ 1675 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1676 /* Calc AV bit */ 1677 tcg_gen_add_tl(cpu_PSW_AV, result, result); 1678 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 1679 /* calc SAV bit */ 1680 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 1681 /* write back result */ 1682 tcg_gen_mov_tl(ret, result); 1683 1684 tcg_temp_free(result); 1685 tcg_temp_free(temp); 1686 } 1687 1688 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2) 1689 { 1690 TCGv temp = tcg_temp_new(); 1691 tcg_gen_not_tl(temp, r2); 1692 gen_addc_CC(ret, r1, temp); 1693 tcg_temp_free(temp); 1694 } 1695 1696 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3, 1697 TCGv r4) 1698 { 1699 TCGv temp = tcg_temp_new(); 1700 TCGv temp2 = tcg_temp_new(); 1701 TCGv result = tcg_temp_new(); 1702 TCGv mask = tcg_temp_new(); 1703 TCGv t0 = tcg_const_i32(0); 1704 1705 /* create mask for sticky bits */ 1706 tcg_gen_setcond_tl(cond, mask, r4, t0); 1707 tcg_gen_shli_tl(mask, mask, 31); 1708 1709 tcg_gen_sub_tl(result, r1, r2); 1710 /* Calc PSW_V */ 1711 tcg_gen_xor_tl(temp, result, r1); 1712 tcg_gen_xor_tl(temp2, r1, r2); 1713 tcg_gen_and_tl(temp, temp, temp2); 1714 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V); 1715 /* Set PSW_SV */ 1716 tcg_gen_and_tl(temp, temp, mask); 1717 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV); 1718 /* calc AV bit */ 1719 tcg_gen_add_tl(temp, result, result); 1720 tcg_gen_xor_tl(temp, temp, result); 1721 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV); 1722 /* calc SAV bit */ 1723 tcg_gen_and_tl(temp, temp, mask); 1724 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV); 1725 /* write back result */ 1726 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1); 1727 1728 tcg_temp_free(t0); 1729 tcg_temp_free(temp); 1730 tcg_temp_free(temp2); 1731 tcg_temp_free(result); 1732 tcg_temp_free(mask); 1733 } 1734 1735 static inline void 1736 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1737 TCGv r3, uint32_t n, uint32_t mode) 1738 { 1739 TCGv temp = tcg_const_i32(n); 1740 TCGv temp2 = tcg_temp_new(); 1741 TCGv_i64 temp64 = tcg_temp_new_i64(); 1742 switch (mode) { 1743 case MODE_LL: 1744 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1745 break; 1746 case MODE_LU: 1747 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1748 break; 1749 case MODE_UL: 1750 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1751 break; 1752 case MODE_UU: 1753 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1754 break; 1755 } 1756 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1757 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 1758 tcg_gen_sub_tl, tcg_gen_sub_tl); 1759 tcg_temp_free(temp); 1760 tcg_temp_free(temp2); 1761 tcg_temp_free_i64(temp64); 1762 } 1763 1764 static inline void 1765 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1766 TCGv r3, uint32_t n, uint32_t mode) 1767 { 1768 TCGv temp = tcg_const_i32(n); 1769 TCGv temp2 = tcg_temp_new(); 1770 TCGv temp3 = tcg_temp_new(); 1771 TCGv_i64 temp64 = tcg_temp_new_i64(); 1772 1773 switch (mode) { 1774 case MODE_LL: 1775 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1776 break; 1777 case MODE_LU: 1778 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1779 break; 1780 case MODE_UL: 1781 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1782 break; 1783 case MODE_UU: 1784 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1785 break; 1786 } 1787 tcg_gen_extr_i64_i32(temp, temp2, temp64); 1788 gen_subs(ret_low, r1_low, temp); 1789 tcg_gen_mov_tl(temp, cpu_PSW_V); 1790 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 1791 gen_subs(ret_high, r1_high, temp2); 1792 /* combine v bits */ 1793 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 1794 /* combine av bits */ 1795 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 1796 1797 tcg_temp_free(temp); 1798 tcg_temp_free(temp2); 1799 tcg_temp_free(temp3); 1800 tcg_temp_free_i64(temp64); 1801 } 1802 1803 static inline void 1804 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1805 TCGv r3, uint32_t n, uint32_t mode) 1806 { 1807 TCGv temp = tcg_const_i32(n); 1808 TCGv_i64 temp64 = tcg_temp_new_i64(); 1809 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1810 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 1811 switch (mode) { 1812 case MODE_LL: 1813 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 1814 break; 1815 case MODE_LU: 1816 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 1817 break; 1818 case MODE_UL: 1819 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 1820 break; 1821 case MODE_UU: 1822 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 1823 break; 1824 } 1825 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1826 gen_sub64_d(temp64_3, temp64_2, temp64); 1827 /* write back result */ 1828 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3); 1829 1830 tcg_temp_free(temp); 1831 tcg_temp_free_i64(temp64); 1832 tcg_temp_free_i64(temp64_2); 1833 tcg_temp_free_i64(temp64_3); 1834 } 1835 1836 static inline void 1837 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 1838 TCGv r3, uint32_t n, uint32_t mode) 1839 { 1840 TCGv temp = tcg_const_i32(n); 1841 TCGv_i64 temp64 = tcg_temp_new_i64(); 1842 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 1843 switch (mode) { 1844 case MODE_LL: 1845 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp); 1846 break; 1847 case MODE_LU: 1848 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp); 1849 break; 1850 case MODE_UL: 1851 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp); 1852 break; 1853 case MODE_UU: 1854 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp); 1855 break; 1856 } 1857 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 1858 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 1859 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 1860 1861 tcg_temp_free(temp); 1862 tcg_temp_free_i64(temp64); 1863 tcg_temp_free_i64(temp64_2); 1864 } 1865 1866 static inline void 1867 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n, 1868 uint32_t mode) 1869 { 1870 TCGv temp = tcg_const_i32(n); 1871 TCGv_i64 temp64 = tcg_temp_new_i64(); 1872 switch (mode) { 1873 case MODE_LL: 1874 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1875 break; 1876 case MODE_LU: 1877 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1878 break; 1879 case MODE_UL: 1880 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1881 break; 1882 case MODE_UU: 1883 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1884 break; 1885 } 1886 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high); 1887 1888 tcg_temp_free(temp); 1889 tcg_temp_free_i64(temp64); 1890 } 1891 1892 static inline void 1893 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1894 { 1895 TCGv temp = tcg_temp_new(); 1896 TCGv temp2 = tcg_temp_new(); 1897 1898 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1899 tcg_gen_shli_tl(temp, r1, 16); 1900 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode); 1901 1902 tcg_temp_free(temp); 1903 tcg_temp_free(temp2); 1904 } 1905 1906 static inline void 1907 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, 1908 uint32_t n, uint32_t mode) 1909 { 1910 TCGv temp = tcg_const_i32(n); 1911 TCGv_i64 temp64 = tcg_temp_new_i64(); 1912 switch (mode) { 1913 case MODE_LL: 1914 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 1915 break; 1916 case MODE_LU: 1917 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 1918 break; 1919 case MODE_UL: 1920 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 1921 break; 1922 case MODE_UU: 1923 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 1924 break; 1925 } 1926 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high); 1927 1928 tcg_temp_free(temp); 1929 tcg_temp_free_i64(temp64); 1930 } 1931 1932 static inline void 1933 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 1934 { 1935 TCGv temp = tcg_temp_new(); 1936 TCGv temp2 = tcg_temp_new(); 1937 1938 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 1939 tcg_gen_shli_tl(temp, r1, 16); 1940 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode); 1941 1942 tcg_temp_free(temp); 1943 tcg_temp_free(temp2); 1944 } 1945 1946 static inline void 1947 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1948 { 1949 TCGv temp = tcg_const_i32(n); 1950 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp); 1951 tcg_temp_free(temp); 1952 } 1953 1954 static inline void 1955 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n) 1956 { 1957 TCGv temp = tcg_const_i32(n); 1958 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp); 1959 tcg_temp_free(temp); 1960 } 1961 1962 static inline void 1963 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 1964 uint32_t up_shift, CPUTriCoreState *env) 1965 { 1966 TCGv temp = tcg_temp_new(); 1967 TCGv temp2 = tcg_temp_new(); 1968 TCGv temp3 = tcg_temp_new(); 1969 TCGv_i64 t1 = tcg_temp_new_i64(); 1970 TCGv_i64 t2 = tcg_temp_new_i64(); 1971 TCGv_i64 t3 = tcg_temp_new_i64(); 1972 TCGv_i64 t4 = tcg_temp_new_i64(); 1973 1974 tcg_gen_ext_i32_i64(t2, arg2); 1975 tcg_gen_ext_i32_i64(t3, arg3); 1976 1977 tcg_gen_mul_i64(t2, t2, t3); 1978 1979 tcg_gen_ext_i32_i64(t1, arg1); 1980 /* if we shift part of the fraction out, we need to round up */ 1981 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 1982 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 1983 tcg_gen_sari_i64(t2, t2, up_shift - n); 1984 tcg_gen_add_i64(t2, t2, t4); 1985 1986 tcg_gen_sub_i64(t3, t1, t2); 1987 tcg_gen_extrl_i64_i32(temp3, t3); 1988 /* calc v bit */ 1989 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL); 1990 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL); 1991 tcg_gen_or_i64(t1, t1, t2); 1992 tcg_gen_extrl_i64_i32(cpu_PSW_V, t1); 1993 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 1994 /* Calc SV bit */ 1995 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 1996 /* Calc AV/SAV bits */ 1997 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3); 1998 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV); 1999 /* calc SAV */ 2000 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2001 /* write back result */ 2002 tcg_gen_mov_tl(ret, temp3); 2003 2004 tcg_temp_free(temp); 2005 tcg_temp_free(temp2); 2006 tcg_temp_free(temp3); 2007 tcg_temp_free_i64(t1); 2008 tcg_temp_free_i64(t2); 2009 tcg_temp_free_i64(t3); 2010 tcg_temp_free_i64(t4); 2011 } 2012 2013 static inline void 2014 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 2015 { 2016 TCGv temp = tcg_temp_new(); 2017 TCGv temp2 = tcg_temp_new(); 2018 if (n == 0) { 2019 tcg_gen_mul_tl(temp, arg2, arg3); 2020 } else { /* n is expected to be 1 */ 2021 tcg_gen_mul_tl(temp, arg2, arg3); 2022 tcg_gen_shli_tl(temp, temp, 1); 2023 /* catch special case r1 = r2 = 0x8000 */ 2024 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2025 tcg_gen_sub_tl(temp, temp, temp2); 2026 } 2027 gen_sub_d(ret, arg1, temp); 2028 2029 tcg_temp_free(temp); 2030 tcg_temp_free(temp2); 2031 } 2032 2033 static inline void 2034 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n) 2035 { 2036 TCGv temp = tcg_temp_new(); 2037 TCGv temp2 = tcg_temp_new(); 2038 if (n == 0) { 2039 tcg_gen_mul_tl(temp, arg2, arg3); 2040 } else { /* n is expected to be 1 */ 2041 tcg_gen_mul_tl(temp, arg2, arg3); 2042 tcg_gen_shli_tl(temp, temp, 1); 2043 /* catch special case r1 = r2 = 0x8000 */ 2044 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2045 tcg_gen_sub_tl(temp, temp, temp2); 2046 } 2047 gen_subs(ret, arg1, temp); 2048 2049 tcg_temp_free(temp); 2050 tcg_temp_free(temp2); 2051 } 2052 2053 static inline void 2054 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2055 TCGv arg3, uint32_t n) 2056 { 2057 TCGv temp = tcg_temp_new(); 2058 TCGv temp2 = tcg_temp_new(); 2059 TCGv_i64 t1 = tcg_temp_new_i64(); 2060 TCGv_i64 t2 = tcg_temp_new_i64(); 2061 TCGv_i64 t3 = tcg_temp_new_i64(); 2062 2063 if (n == 0) { 2064 tcg_gen_mul_tl(temp, arg2, arg3); 2065 } else { /* n is expected to be 1 */ 2066 tcg_gen_mul_tl(temp, arg2, arg3); 2067 tcg_gen_shli_tl(temp, temp, 1); 2068 /* catch special case r1 = r2 = 0x8000 */ 2069 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2070 tcg_gen_sub_tl(temp, temp, temp2); 2071 } 2072 tcg_gen_ext_i32_i64(t2, temp); 2073 tcg_gen_shli_i64(t2, t2, 16); 2074 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 2075 gen_sub64_d(t3, t1, t2); 2076 /* write back result */ 2077 tcg_gen_extr_i64_i32(rl, rh, t3); 2078 2079 tcg_temp_free_i64(t1); 2080 tcg_temp_free_i64(t2); 2081 tcg_temp_free_i64(t3); 2082 tcg_temp_free(temp); 2083 tcg_temp_free(temp2); 2084 } 2085 2086 static inline void 2087 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2088 TCGv arg3, uint32_t n) 2089 { 2090 TCGv temp = tcg_temp_new(); 2091 TCGv temp2 = tcg_temp_new(); 2092 TCGv_i64 t1 = tcg_temp_new_i64(); 2093 TCGv_i64 t2 = tcg_temp_new_i64(); 2094 2095 if (n == 0) { 2096 tcg_gen_mul_tl(temp, arg2, arg3); 2097 } else { /* n is expected to be 1 */ 2098 tcg_gen_mul_tl(temp, arg2, arg3); 2099 tcg_gen_shli_tl(temp, temp, 1); 2100 /* catch special case r1 = r2 = 0x8000 */ 2101 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000); 2102 tcg_gen_sub_tl(temp, temp, temp2); 2103 } 2104 tcg_gen_ext_i32_i64(t2, temp); 2105 tcg_gen_shli_i64(t2, t2, 16); 2106 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 2107 2108 gen_helper_sub64_ssov(t1, cpu_env, t1, t2); 2109 tcg_gen_extr_i64_i32(rl, rh, t1); 2110 2111 tcg_temp_free(temp); 2112 tcg_temp_free(temp2); 2113 tcg_temp_free_i64(t1); 2114 tcg_temp_free_i64(t2); 2115 } 2116 2117 static inline void 2118 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2119 TCGv arg3, uint32_t n, CPUTriCoreState *env) 2120 { 2121 TCGv_i64 t1 = tcg_temp_new_i64(); 2122 TCGv_i64 t2 = tcg_temp_new_i64(); 2123 TCGv_i64 t3 = tcg_temp_new_i64(); 2124 TCGv_i64 t4 = tcg_temp_new_i64(); 2125 TCGv temp, temp2; 2126 2127 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high); 2128 tcg_gen_ext_i32_i64(t2, arg2); 2129 tcg_gen_ext_i32_i64(t3, arg3); 2130 2131 tcg_gen_mul_i64(t2, t2, t3); 2132 if (n != 0) { 2133 tcg_gen_shli_i64(t2, t2, 1); 2134 } 2135 tcg_gen_sub_i64(t4, t1, t2); 2136 /* calc v bit */ 2137 tcg_gen_xor_i64(t3, t4, t1); 2138 tcg_gen_xor_i64(t2, t1, t2); 2139 tcg_gen_and_i64(t3, t3, t2); 2140 tcg_gen_extrh_i64_i32(cpu_PSW_V, t3); 2141 /* We produce an overflow on the host if the mul before was 2142 (0x80000000 * 0x80000000) << 1). If this is the 2143 case, we negate the ovf. */ 2144 if (n == 1) { 2145 temp = tcg_temp_new(); 2146 temp2 = tcg_temp_new(); 2147 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); 2148 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); 2149 tcg_gen_and_tl(temp, temp, temp2); 2150 tcg_gen_shli_tl(temp, temp, 31); 2151 /* negate v bit, if special condition */ 2152 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); 2153 2154 tcg_temp_free(temp); 2155 tcg_temp_free(temp2); 2156 } 2157 /* write back result */ 2158 tcg_gen_extr_i64_i32(rl, rh, t4); 2159 /* Calc SV bit */ 2160 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2161 /* Calc AV/SAV bits */ 2162 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2163 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2164 /* calc SAV */ 2165 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2166 2167 tcg_temp_free_i64(t1); 2168 tcg_temp_free_i64(t2); 2169 tcg_temp_free_i64(t3); 2170 tcg_temp_free_i64(t4); 2171 } 2172 2173 static inline void 2174 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, 2175 uint32_t up_shift) 2176 { 2177 TCGv_i64 t1 = tcg_temp_new_i64(); 2178 TCGv_i64 t2 = tcg_temp_new_i64(); 2179 TCGv_i64 t3 = tcg_temp_new_i64(); 2180 TCGv_i64 t4 = tcg_temp_new_i64(); 2181 2182 tcg_gen_ext_i32_i64(t1, arg1); 2183 tcg_gen_ext_i32_i64(t2, arg2); 2184 tcg_gen_ext_i32_i64(t3, arg3); 2185 2186 tcg_gen_mul_i64(t2, t2, t3); 2187 /* if we shift part of the fraction out, we need to round up */ 2188 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1); 2189 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0); 2190 tcg_gen_sari_i64(t3, t2, up_shift - n); 2191 tcg_gen_add_i64(t3, t3, t4); 2192 2193 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3); 2194 2195 tcg_temp_free_i64(t1); 2196 tcg_temp_free_i64(t2); 2197 tcg_temp_free_i64(t3); 2198 tcg_temp_free_i64(t4); 2199 } 2200 2201 static inline void 2202 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2, 2203 TCGv arg3, uint32_t n) 2204 { 2205 TCGv_i64 r1 = tcg_temp_new_i64(); 2206 TCGv temp = tcg_const_i32(n); 2207 2208 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high); 2209 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp); 2210 tcg_gen_extr_i64_i32(rl, rh, r1); 2211 2212 tcg_temp_free_i64(r1); 2213 tcg_temp_free(temp); 2214 } 2215 2216 static inline void 2217 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2218 TCGv r3, uint32_t n, uint32_t mode) 2219 { 2220 TCGv temp = tcg_const_i32(n); 2221 TCGv temp2 = tcg_temp_new(); 2222 TCGv_i64 temp64 = tcg_temp_new_i64(); 2223 switch (mode) { 2224 case MODE_LL: 2225 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2226 break; 2227 case MODE_LU: 2228 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2229 break; 2230 case MODE_UL: 2231 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2232 break; 2233 case MODE_UU: 2234 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2235 break; 2236 } 2237 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2238 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2, 2239 tcg_gen_add_tl, tcg_gen_sub_tl); 2240 tcg_temp_free(temp); 2241 tcg_temp_free(temp2); 2242 tcg_temp_free_i64(temp64); 2243 } 2244 2245 static inline void 2246 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2247 TCGv r3, uint32_t n, uint32_t mode) 2248 { 2249 TCGv temp = tcg_const_i32(n); 2250 TCGv_i64 temp64 = tcg_temp_new_i64(); 2251 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2252 TCGv_i64 temp64_3 = tcg_temp_new_i64(); 2253 switch (mode) { 2254 case MODE_LL: 2255 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2256 break; 2257 case MODE_LU: 2258 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2259 break; 2260 case MODE_UL: 2261 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2262 break; 2263 case MODE_UU: 2264 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2265 break; 2266 } 2267 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high); 2268 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2269 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2270 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2271 tcg_gen_shli_i64(temp64, temp64, 16); 2272 2273 gen_sub64_d(temp64_2, temp64_3, temp64); 2274 /* write back result */ 2275 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2); 2276 2277 tcg_temp_free(temp); 2278 tcg_temp_free_i64(temp64); 2279 tcg_temp_free_i64(temp64_2); 2280 tcg_temp_free_i64(temp64_3); 2281 } 2282 2283 static inline void 2284 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2285 { 2286 TCGv temp = tcg_const_i32(n); 2287 TCGv temp2 = tcg_temp_new(); 2288 TCGv_i64 temp64 = tcg_temp_new_i64(); 2289 switch (mode) { 2290 case MODE_LL: 2291 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2292 break; 2293 case MODE_LU: 2294 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2295 break; 2296 case MODE_UL: 2297 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2298 break; 2299 case MODE_UU: 2300 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2301 break; 2302 } 2303 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2304 tcg_gen_shli_tl(temp, r1, 16); 2305 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2); 2306 2307 tcg_temp_free(temp); 2308 tcg_temp_free(temp2); 2309 tcg_temp_free_i64(temp64); 2310 } 2311 2312 static inline void 2313 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2314 TCGv r3, uint32_t n, uint32_t mode) 2315 { 2316 TCGv temp = tcg_const_i32(n); 2317 TCGv temp2 = tcg_temp_new(); 2318 TCGv temp3 = tcg_temp_new(); 2319 TCGv_i64 temp64 = tcg_temp_new_i64(); 2320 2321 switch (mode) { 2322 case MODE_LL: 2323 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2324 break; 2325 case MODE_LU: 2326 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2327 break; 2328 case MODE_UL: 2329 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2330 break; 2331 case MODE_UU: 2332 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2333 break; 2334 } 2335 tcg_gen_extr_i64_i32(temp, temp2, temp64); 2336 gen_adds(ret_low, r1_low, temp); 2337 tcg_gen_mov_tl(temp, cpu_PSW_V); 2338 tcg_gen_mov_tl(temp3, cpu_PSW_AV); 2339 gen_subs(ret_high, r1_high, temp2); 2340 /* combine v bits */ 2341 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp); 2342 /* combine av bits */ 2343 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3); 2344 2345 tcg_temp_free(temp); 2346 tcg_temp_free(temp2); 2347 tcg_temp_free(temp3); 2348 tcg_temp_free_i64(temp64); 2349 } 2350 2351 static inline void 2352 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2, 2353 TCGv r3, uint32_t n, uint32_t mode) 2354 { 2355 TCGv temp = tcg_const_i32(n); 2356 TCGv_i64 temp64 = tcg_temp_new_i64(); 2357 TCGv_i64 temp64_2 = tcg_temp_new_i64(); 2358 2359 switch (mode) { 2360 case MODE_LL: 2361 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2362 break; 2363 case MODE_LU: 2364 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2365 break; 2366 case MODE_UL: 2367 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2368 break; 2369 case MODE_UU: 2370 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2371 break; 2372 } 2373 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */ 2374 tcg_gen_ext32s_i64(temp64, temp64); /* low */ 2375 tcg_gen_sub_i64(temp64, temp64_2, temp64); 2376 tcg_gen_shli_i64(temp64, temp64, 16); 2377 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high); 2378 2379 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64); 2380 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2381 2382 tcg_temp_free(temp); 2383 tcg_temp_free_i64(temp64); 2384 tcg_temp_free_i64(temp64_2); 2385 } 2386 2387 static inline void 2388 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode) 2389 { 2390 TCGv temp = tcg_const_i32(n); 2391 TCGv temp2 = tcg_temp_new(); 2392 TCGv_i64 temp64 = tcg_temp_new_i64(); 2393 switch (mode) { 2394 case MODE_LL: 2395 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp); 2396 break; 2397 case MODE_LU: 2398 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp); 2399 break; 2400 case MODE_UL: 2401 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp); 2402 break; 2403 case MODE_UU: 2404 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp); 2405 break; 2406 } 2407 tcg_gen_andi_tl(temp2, r1, 0xffff0000); 2408 tcg_gen_shli_tl(temp, r1, 16); 2409 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2); 2410 2411 tcg_temp_free(temp); 2412 tcg_temp_free(temp2); 2413 tcg_temp_free_i64(temp64); 2414 } 2415 2416 static inline void gen_abs(TCGv ret, TCGv r1) 2417 { 2418 TCGv temp = tcg_temp_new(); 2419 TCGv t0 = tcg_const_i32(0); 2420 2421 tcg_gen_neg_tl(temp, r1); 2422 tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp); 2423 /* overflow can only happen, if r1 = 0x80000000 */ 2424 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000); 2425 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2426 /* calc SV bit */ 2427 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2428 /* Calc AV bit */ 2429 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2430 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2431 /* calc SAV bit */ 2432 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2433 2434 tcg_temp_free(temp); 2435 tcg_temp_free(t0); 2436 } 2437 2438 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2) 2439 { 2440 TCGv temp = tcg_temp_new_i32(); 2441 TCGv result = tcg_temp_new_i32(); 2442 2443 tcg_gen_sub_tl(result, r1, r2); 2444 tcg_gen_sub_tl(temp, r2, r1); 2445 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp); 2446 2447 /* calc V bit */ 2448 tcg_gen_xor_tl(cpu_PSW_V, result, r1); 2449 tcg_gen_xor_tl(temp, result, r2); 2450 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp); 2451 tcg_gen_xor_tl(temp, r1, r2); 2452 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp); 2453 /* calc SV bit */ 2454 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2455 /* Calc AV bit */ 2456 tcg_gen_add_tl(cpu_PSW_AV, result, result); 2457 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV); 2458 /* calc SAV bit */ 2459 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2460 /* write back result */ 2461 tcg_gen_mov_tl(ret, result); 2462 2463 tcg_temp_free(temp); 2464 tcg_temp_free(result); 2465 } 2466 2467 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con) 2468 { 2469 TCGv temp = tcg_const_i32(con); 2470 gen_absdif(ret, r1, temp); 2471 tcg_temp_free(temp); 2472 } 2473 2474 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con) 2475 { 2476 TCGv temp = tcg_const_i32(con); 2477 gen_helper_absdif_ssov(ret, cpu_env, r1, temp); 2478 tcg_temp_free(temp); 2479 } 2480 2481 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2) 2482 { 2483 TCGv high = tcg_temp_new(); 2484 TCGv low = tcg_temp_new(); 2485 2486 tcg_gen_muls2_tl(low, high, r1, r2); 2487 tcg_gen_mov_tl(ret, low); 2488 /* calc V bit */ 2489 tcg_gen_sari_tl(low, low, 31); 2490 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low); 2491 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2492 /* calc SV bit */ 2493 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2494 /* Calc AV bit */ 2495 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2496 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2497 /* calc SAV bit */ 2498 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2499 2500 tcg_temp_free(high); 2501 tcg_temp_free(low); 2502 } 2503 2504 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con) 2505 { 2506 TCGv temp = tcg_const_i32(con); 2507 gen_mul_i32s(ret, r1, temp); 2508 tcg_temp_free(temp); 2509 } 2510 2511 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2512 { 2513 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2); 2514 /* clear V bit */ 2515 tcg_gen_movi_tl(cpu_PSW_V, 0); 2516 /* calc SV bit */ 2517 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2518 /* Calc AV bit */ 2519 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2520 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2521 /* calc SAV bit */ 2522 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2523 } 2524 2525 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, 2526 int32_t con) 2527 { 2528 TCGv temp = tcg_const_i32(con); 2529 gen_mul_i64s(ret_low, ret_high, r1, temp); 2530 tcg_temp_free(temp); 2531 } 2532 2533 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2) 2534 { 2535 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2); 2536 /* clear V bit */ 2537 tcg_gen_movi_tl(cpu_PSW_V, 0); 2538 /* calc SV bit */ 2539 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2540 /* Calc AV bit */ 2541 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high); 2542 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV); 2543 /* calc SAV bit */ 2544 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2545 } 2546 2547 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, 2548 int32_t con) 2549 { 2550 TCGv temp = tcg_const_i32(con); 2551 gen_mul_i64u(ret_low, ret_high, r1, temp); 2552 tcg_temp_free(temp); 2553 } 2554 2555 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con) 2556 { 2557 TCGv temp = tcg_const_i32(con); 2558 gen_helper_mul_ssov(ret, cpu_env, r1, temp); 2559 tcg_temp_free(temp); 2560 } 2561 2562 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con) 2563 { 2564 TCGv temp = tcg_const_i32(con); 2565 gen_helper_mul_suov(ret, cpu_env, r1, temp); 2566 tcg_temp_free(temp); 2567 } 2568 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */ 2569 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2570 { 2571 TCGv temp = tcg_const_i32(con); 2572 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp); 2573 tcg_temp_free(temp); 2574 } 2575 2576 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2577 { 2578 TCGv temp = tcg_const_i32(con); 2579 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp); 2580 tcg_temp_free(temp); 2581 } 2582 2583 static void 2584 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift) 2585 { 2586 TCGv temp = tcg_temp_new(); 2587 TCGv_i64 temp_64 = tcg_temp_new_i64(); 2588 TCGv_i64 temp2_64 = tcg_temp_new_i64(); 2589 2590 if (n == 0) { 2591 if (up_shift == 32) { 2592 tcg_gen_muls2_tl(rh, rl, arg1, arg2); 2593 } else if (up_shift == 16) { 2594 tcg_gen_ext_i32_i64(temp_64, arg1); 2595 tcg_gen_ext_i32_i64(temp2_64, arg2); 2596 2597 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2598 tcg_gen_shri_i64(temp_64, temp_64, up_shift); 2599 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2600 } else { 2601 tcg_gen_muls2_tl(rl, rh, arg1, arg2); 2602 } 2603 /* reset v bit */ 2604 tcg_gen_movi_tl(cpu_PSW_V, 0); 2605 } else { /* n is expected to be 1 */ 2606 tcg_gen_ext_i32_i64(temp_64, arg1); 2607 tcg_gen_ext_i32_i64(temp2_64, arg2); 2608 2609 tcg_gen_mul_i64(temp_64, temp_64, temp2_64); 2610 2611 if (up_shift == 0) { 2612 tcg_gen_shli_i64(temp_64, temp_64, 1); 2613 } else { 2614 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1); 2615 } 2616 tcg_gen_extr_i64_i32(rl, rh, temp_64); 2617 /* overflow only occurs if r1 = r2 = 0x8000 */ 2618 if (up_shift == 0) {/* result is 64 bit */ 2619 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh, 2620 0x80000000); 2621 } else { /* result is 32 bit */ 2622 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl, 2623 0x80000000); 2624 } 2625 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2626 /* calc sv overflow bit */ 2627 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 2628 } 2629 /* calc av overflow bit */ 2630 if (up_shift == 0) { 2631 tcg_gen_add_tl(cpu_PSW_AV, rh, rh); 2632 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV); 2633 } else { 2634 tcg_gen_add_tl(cpu_PSW_AV, rl, rl); 2635 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV); 2636 } 2637 /* calc sav overflow bit */ 2638 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2639 tcg_temp_free(temp); 2640 tcg_temp_free_i64(temp_64); 2641 tcg_temp_free_i64(temp2_64); 2642 } 2643 2644 static void 2645 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2646 { 2647 TCGv temp = tcg_temp_new(); 2648 if (n == 0) { 2649 tcg_gen_mul_tl(ret, arg1, arg2); 2650 } else { /* n is expected to be 1 */ 2651 tcg_gen_mul_tl(ret, arg1, arg2); 2652 tcg_gen_shli_tl(ret, ret, 1); 2653 /* catch special case r1 = r2 = 0x8000 */ 2654 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000); 2655 tcg_gen_sub_tl(ret, ret, temp); 2656 } 2657 /* reset v bit */ 2658 tcg_gen_movi_tl(cpu_PSW_V, 0); 2659 /* calc av overflow bit */ 2660 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2661 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2662 /* calc sav overflow bit */ 2663 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2664 2665 tcg_temp_free(temp); 2666 } 2667 2668 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n) 2669 { 2670 TCGv temp = tcg_temp_new(); 2671 if (n == 0) { 2672 tcg_gen_mul_tl(ret, arg1, arg2); 2673 tcg_gen_addi_tl(ret, ret, 0x8000); 2674 } else { 2675 tcg_gen_mul_tl(ret, arg1, arg2); 2676 tcg_gen_shli_tl(ret, ret, 1); 2677 tcg_gen_addi_tl(ret, ret, 0x8000); 2678 /* catch special case r1 = r2 = 0x8000 */ 2679 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000); 2680 tcg_gen_muli_tl(temp, temp, 0x8001); 2681 tcg_gen_sub_tl(ret, ret, temp); 2682 } 2683 /* reset v bit */ 2684 tcg_gen_movi_tl(cpu_PSW_V, 0); 2685 /* calc av overflow bit */ 2686 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2687 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2688 /* calc sav overflow bit */ 2689 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2690 /* cut halfword off */ 2691 tcg_gen_andi_tl(ret, ret, 0xffff0000); 2692 2693 tcg_temp_free(temp); 2694 } 2695 2696 static inline void 2697 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2698 TCGv r3) 2699 { 2700 TCGv_i64 temp64 = tcg_temp_new_i64(); 2701 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2702 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3); 2703 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2704 tcg_temp_free_i64(temp64); 2705 } 2706 2707 static inline void 2708 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2709 int32_t con) 2710 { 2711 TCGv temp = tcg_const_i32(con); 2712 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2713 tcg_temp_free(temp); 2714 } 2715 2716 static inline void 2717 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2718 TCGv r3) 2719 { 2720 TCGv_i64 temp64 = tcg_temp_new_i64(); 2721 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2722 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3); 2723 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2724 tcg_temp_free_i64(temp64); 2725 } 2726 2727 static inline void 2728 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2729 int32_t con) 2730 { 2731 TCGv temp = tcg_const_i32(con); 2732 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2733 tcg_temp_free(temp); 2734 } 2735 2736 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2737 { 2738 TCGv temp = tcg_const_i32(con); 2739 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp); 2740 tcg_temp_free(temp); 2741 } 2742 2743 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con) 2744 { 2745 TCGv temp = tcg_const_i32(con); 2746 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp); 2747 tcg_temp_free(temp); 2748 } 2749 2750 static inline void 2751 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2752 TCGv r3) 2753 { 2754 TCGv_i64 temp64 = tcg_temp_new_i64(); 2755 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2756 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3); 2757 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2758 tcg_temp_free_i64(temp64); 2759 } 2760 2761 static inline void 2762 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2763 int32_t con) 2764 { 2765 TCGv temp = tcg_const_i32(con); 2766 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2767 tcg_temp_free(temp); 2768 } 2769 2770 static inline void 2771 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2772 TCGv r3) 2773 { 2774 TCGv_i64 temp64 = tcg_temp_new_i64(); 2775 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high); 2776 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3); 2777 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64); 2778 tcg_temp_free_i64(temp64); 2779 } 2780 2781 static inline void 2782 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high, 2783 int32_t con) 2784 { 2785 TCGv temp = tcg_const_i32(con); 2786 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp); 2787 tcg_temp_free(temp); 2788 } 2789 2790 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low) 2791 { 2792 TCGv sat_neg = tcg_const_i32(low); 2793 TCGv temp = tcg_const_i32(up); 2794 2795 /* sat_neg = (arg < low ) ? low : arg; */ 2796 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg); 2797 2798 /* ret = (sat_neg > up ) ? up : sat_neg; */ 2799 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg); 2800 2801 tcg_temp_free(sat_neg); 2802 tcg_temp_free(temp); 2803 } 2804 2805 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up) 2806 { 2807 TCGv temp = tcg_const_i32(up); 2808 /* sat_neg = (arg > up ) ? up : arg; */ 2809 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg); 2810 tcg_temp_free(temp); 2811 } 2812 2813 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count) 2814 { 2815 if (shift_count == -32) { 2816 tcg_gen_movi_tl(ret, 0); 2817 } else if (shift_count >= 0) { 2818 tcg_gen_shli_tl(ret, r1, shift_count); 2819 } else { 2820 tcg_gen_shri_tl(ret, r1, -shift_count); 2821 } 2822 } 2823 2824 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount) 2825 { 2826 TCGv temp_low, temp_high; 2827 2828 if (shiftcount == -16) { 2829 tcg_gen_movi_tl(ret, 0); 2830 } else { 2831 temp_high = tcg_temp_new(); 2832 temp_low = tcg_temp_new(); 2833 2834 tcg_gen_andi_tl(temp_low, r1, 0xffff); 2835 tcg_gen_andi_tl(temp_high, r1, 0xffff0000); 2836 gen_shi(temp_low, temp_low, shiftcount); 2837 gen_shi(ret, temp_high, shiftcount); 2838 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16); 2839 2840 tcg_temp_free(temp_low); 2841 tcg_temp_free(temp_high); 2842 } 2843 } 2844 2845 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count) 2846 { 2847 uint32_t msk, msk_start; 2848 TCGv temp = tcg_temp_new(); 2849 TCGv temp2 = tcg_temp_new(); 2850 TCGv t_0 = tcg_const_i32(0); 2851 2852 if (shift_count == 0) { 2853 /* Clear PSW.C and PSW.V */ 2854 tcg_gen_movi_tl(cpu_PSW_C, 0); 2855 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C); 2856 tcg_gen_mov_tl(ret, r1); 2857 } else if (shift_count == -32) { 2858 /* set PSW.C */ 2859 tcg_gen_mov_tl(cpu_PSW_C, r1); 2860 /* fill ret completely with sign bit */ 2861 tcg_gen_sari_tl(ret, r1, 31); 2862 /* clear PSW.V */ 2863 tcg_gen_movi_tl(cpu_PSW_V, 0); 2864 } else if (shift_count > 0) { 2865 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count); 2866 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count); 2867 2868 /* calc carry */ 2869 msk_start = 32 - shift_count; 2870 msk = ((1 << shift_count) - 1) << msk_start; 2871 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2872 /* calc v/sv bits */ 2873 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max); 2874 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min); 2875 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 2876 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 2877 /* calc sv */ 2878 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV); 2879 /* do shift */ 2880 tcg_gen_shli_tl(ret, r1, shift_count); 2881 2882 tcg_temp_free(t_max); 2883 tcg_temp_free(t_min); 2884 } else { 2885 /* clear PSW.V */ 2886 tcg_gen_movi_tl(cpu_PSW_V, 0); 2887 /* calc carry */ 2888 msk = (1 << -shift_count) - 1; 2889 tcg_gen_andi_tl(cpu_PSW_C, r1, msk); 2890 /* do shift */ 2891 tcg_gen_sari_tl(ret, r1, -shift_count); 2892 } 2893 /* calc av overflow bit */ 2894 tcg_gen_add_tl(cpu_PSW_AV, ret, ret); 2895 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV); 2896 /* calc sav overflow bit */ 2897 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 2898 2899 tcg_temp_free(temp); 2900 tcg_temp_free(temp2); 2901 tcg_temp_free(t_0); 2902 } 2903 2904 static void gen_shas(TCGv ret, TCGv r1, TCGv r2) 2905 { 2906 gen_helper_sha_ssov(ret, cpu_env, r1, r2); 2907 } 2908 2909 static void gen_shasi(TCGv ret, TCGv r1, int32_t con) 2910 { 2911 TCGv temp = tcg_const_i32(con); 2912 gen_shas(ret, r1, temp); 2913 tcg_temp_free(temp); 2914 } 2915 2916 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count) 2917 { 2918 TCGv low, high; 2919 2920 if (shift_count == 0) { 2921 tcg_gen_mov_tl(ret, r1); 2922 } else if (shift_count > 0) { 2923 low = tcg_temp_new(); 2924 high = tcg_temp_new(); 2925 2926 tcg_gen_andi_tl(high, r1, 0xffff0000); 2927 tcg_gen_shli_tl(low, r1, shift_count); 2928 tcg_gen_shli_tl(ret, high, shift_count); 2929 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2930 2931 tcg_temp_free(low); 2932 tcg_temp_free(high); 2933 } else { 2934 low = tcg_temp_new(); 2935 high = tcg_temp_new(); 2936 2937 tcg_gen_ext16s_tl(low, r1); 2938 tcg_gen_sari_tl(low, low, -shift_count); 2939 tcg_gen_sari_tl(ret, r1, -shift_count); 2940 tcg_gen_deposit_tl(ret, ret, low, 0, 16); 2941 2942 tcg_temp_free(low); 2943 tcg_temp_free(high); 2944 } 2945 2946 } 2947 2948 /* ret = {ret[30:0], (r1 cond r2)}; */ 2949 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2) 2950 { 2951 TCGv temp = tcg_temp_new(); 2952 TCGv temp2 = tcg_temp_new(); 2953 2954 tcg_gen_shli_tl(temp, ret, 1); 2955 tcg_gen_setcond_tl(cond, temp2, r1, r2); 2956 tcg_gen_or_tl(ret, temp, temp2); 2957 2958 tcg_temp_free(temp); 2959 tcg_temp_free(temp2); 2960 } 2961 2962 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con) 2963 { 2964 TCGv temp = tcg_const_i32(con); 2965 gen_sh_cond(cond, ret, r1, temp); 2966 tcg_temp_free(temp); 2967 } 2968 2969 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2) 2970 { 2971 gen_helper_add_ssov(ret, cpu_env, r1, r2); 2972 } 2973 2974 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con) 2975 { 2976 TCGv temp = tcg_const_i32(con); 2977 gen_helper_add_ssov(ret, cpu_env, r1, temp); 2978 tcg_temp_free(temp); 2979 } 2980 2981 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con) 2982 { 2983 TCGv temp = tcg_const_i32(con); 2984 gen_helper_add_suov(ret, cpu_env, r1, temp); 2985 tcg_temp_free(temp); 2986 } 2987 2988 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2) 2989 { 2990 gen_helper_sub_ssov(ret, cpu_env, r1, r2); 2991 } 2992 2993 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2) 2994 { 2995 gen_helper_sub_suov(ret, cpu_env, r1, r2); 2996 } 2997 2998 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2, 2999 int pos1, int pos2, 3000 void(*op1)(TCGv, TCGv, TCGv), 3001 void(*op2)(TCGv, TCGv, TCGv)) 3002 { 3003 TCGv temp1, temp2; 3004 3005 temp1 = tcg_temp_new(); 3006 temp2 = tcg_temp_new(); 3007 3008 tcg_gen_shri_tl(temp2, r2, pos2); 3009 tcg_gen_shri_tl(temp1, r1, pos1); 3010 3011 (*op1)(temp1, temp1, temp2); 3012 (*op2)(temp1 , ret, temp1); 3013 3014 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1); 3015 3016 tcg_temp_free(temp1); 3017 tcg_temp_free(temp2); 3018 } 3019 3020 /* ret = r1[pos1] op1 r2[pos2]; */ 3021 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2, 3022 int pos1, int pos2, 3023 void(*op1)(TCGv, TCGv, TCGv)) 3024 { 3025 TCGv temp1, temp2; 3026 3027 temp1 = tcg_temp_new(); 3028 temp2 = tcg_temp_new(); 3029 3030 tcg_gen_shri_tl(temp2, r2, pos2); 3031 tcg_gen_shri_tl(temp1, r1, pos1); 3032 3033 (*op1)(ret, temp1, temp2); 3034 3035 tcg_gen_andi_tl(ret, ret, 0x1); 3036 3037 tcg_temp_free(temp1); 3038 tcg_temp_free(temp2); 3039 } 3040 3041 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2, 3042 void(*op)(TCGv, TCGv, TCGv)) 3043 { 3044 TCGv temp = tcg_temp_new(); 3045 TCGv temp2 = tcg_temp_new(); 3046 /* temp = (arg1 cond arg2 )*/ 3047 tcg_gen_setcond_tl(cond, temp, r1, r2); 3048 /* temp2 = ret[0]*/ 3049 tcg_gen_andi_tl(temp2, ret, 0x1); 3050 /* temp = temp insn temp2 */ 3051 (*op)(temp, temp, temp2); 3052 /* ret = {ret[31:1], temp} */ 3053 tcg_gen_deposit_tl(ret, ret, temp, 0, 1); 3054 3055 tcg_temp_free(temp); 3056 tcg_temp_free(temp2); 3057 } 3058 3059 static inline void 3060 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, 3061 void(*op)(TCGv, TCGv, TCGv)) 3062 { 3063 TCGv temp = tcg_const_i32(con); 3064 gen_accumulating_cond(cond, ret, r1, temp, op); 3065 tcg_temp_free(temp); 3066 } 3067 3068 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ 3069 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2) 3070 { 3071 tcg_gen_setcond_tl(cond, ret, r1, r2); 3072 tcg_gen_neg_tl(ret, ret); 3073 } 3074 3075 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) 3076 { 3077 TCGv b0 = tcg_temp_new(); 3078 TCGv b1 = tcg_temp_new(); 3079 TCGv b2 = tcg_temp_new(); 3080 TCGv b3 = tcg_temp_new(); 3081 3082 /* byte 0 */ 3083 tcg_gen_andi_tl(b0, r1, 0xff); 3084 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff); 3085 3086 /* byte 1 */ 3087 tcg_gen_andi_tl(b1, r1, 0xff00); 3088 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00); 3089 3090 /* byte 2 */ 3091 tcg_gen_andi_tl(b2, r1, 0xff0000); 3092 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000); 3093 3094 /* byte 3 */ 3095 tcg_gen_andi_tl(b3, r1, 0xff000000); 3096 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000); 3097 3098 /* combine them */ 3099 tcg_gen_or_tl(ret, b0, b1); 3100 tcg_gen_or_tl(ret, ret, b2); 3101 tcg_gen_or_tl(ret, ret, b3); 3102 3103 tcg_temp_free(b0); 3104 tcg_temp_free(b1); 3105 tcg_temp_free(b2); 3106 tcg_temp_free(b3); 3107 } 3108 3109 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con) 3110 { 3111 TCGv h0 = tcg_temp_new(); 3112 TCGv h1 = tcg_temp_new(); 3113 3114 /* halfword 0 */ 3115 tcg_gen_andi_tl(h0, r1, 0xffff); 3116 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff); 3117 3118 /* halfword 1 */ 3119 tcg_gen_andi_tl(h1, r1, 0xffff0000); 3120 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000); 3121 3122 /* combine them */ 3123 tcg_gen_or_tl(ret, h0, h1); 3124 3125 tcg_temp_free(h0); 3126 tcg_temp_free(h1); 3127 } 3128 /* mask = ((1 << width) -1) << pos; 3129 ret = (r1 & ~mask) | (r2 << pos) & mask); */ 3130 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos) 3131 { 3132 TCGv mask = tcg_temp_new(); 3133 TCGv temp = tcg_temp_new(); 3134 TCGv temp2 = tcg_temp_new(); 3135 3136 tcg_gen_movi_tl(mask, 1); 3137 tcg_gen_shl_tl(mask, mask, width); 3138 tcg_gen_subi_tl(mask, mask, 1); 3139 tcg_gen_shl_tl(mask, mask, pos); 3140 3141 tcg_gen_shl_tl(temp, r2, pos); 3142 tcg_gen_and_tl(temp, temp, mask); 3143 tcg_gen_andc_tl(temp2, r1, mask); 3144 tcg_gen_or_tl(ret, temp, temp2); 3145 3146 tcg_temp_free(mask); 3147 tcg_temp_free(temp); 3148 tcg_temp_free(temp2); 3149 } 3150 3151 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1) 3152 { 3153 TCGv_i64 temp = tcg_temp_new_i64(); 3154 3155 gen_helper_bsplit(temp, r1); 3156 tcg_gen_extr_i64_i32(rl, rh, temp); 3157 3158 tcg_temp_free_i64(temp); 3159 } 3160 3161 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1) 3162 { 3163 TCGv_i64 temp = tcg_temp_new_i64(); 3164 3165 gen_helper_unpack(temp, r1); 3166 tcg_gen_extr_i64_i32(rl, rh, temp); 3167 3168 tcg_temp_free_i64(temp); 3169 } 3170 3171 static inline void 3172 gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 3173 { 3174 TCGv_i64 ret = tcg_temp_new_i64(); 3175 3176 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 3177 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2); 3178 } else { 3179 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2); 3180 } 3181 tcg_gen_extr_i64_i32(rl, rh, ret); 3182 3183 tcg_temp_free_i64(ret); 3184 } 3185 3186 static inline void 3187 gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2) 3188 { 3189 TCGv_i64 ret = tcg_temp_new_i64(); 3190 3191 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 3192 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2); 3193 } else { 3194 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2); 3195 } 3196 tcg_gen_extr_i64_i32(rl, rh, ret); 3197 3198 tcg_temp_free_i64(ret); 3199 } 3200 3201 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high) 3202 { 3203 TCGv temp = tcg_temp_new(); 3204 /* calc AV bit */ 3205 tcg_gen_add_tl(temp, arg_low, arg_low); 3206 tcg_gen_xor_tl(temp, temp, arg_low); 3207 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high); 3208 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high); 3209 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 3210 /* calc SAV bit */ 3211 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3212 tcg_gen_movi_tl(cpu_PSW_V, 0); 3213 tcg_temp_free(temp); 3214 } 3215 3216 static void gen_calc_usb_mulr_h(TCGv arg) 3217 { 3218 TCGv temp = tcg_temp_new(); 3219 /* calc AV bit */ 3220 tcg_gen_add_tl(temp, arg, arg); 3221 tcg_gen_xor_tl(temp, temp, arg); 3222 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16); 3223 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp); 3224 /* calc SAV bit */ 3225 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3226 /* clear V bit */ 3227 tcg_gen_movi_tl(cpu_PSW_V, 0); 3228 tcg_temp_free(temp); 3229 } 3230 3231 /* helpers for generating program flow micro-ops */ 3232 3233 static inline void gen_save_pc(target_ulong pc) 3234 { 3235 tcg_gen_movi_tl(cpu_PC, pc); 3236 } 3237 3238 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 3239 { 3240 if (unlikely(ctx->singlestep_enabled)) { 3241 return false; 3242 } 3243 3244 #ifndef CONFIG_USER_ONLY 3245 return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 3246 #else 3247 return true; 3248 #endif 3249 } 3250 3251 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 3252 { 3253 if (use_goto_tb(ctx, dest)) { 3254 tcg_gen_goto_tb(n); 3255 gen_save_pc(dest); 3256 tcg_gen_exit_tb(ctx->tb, n); 3257 } else { 3258 gen_save_pc(dest); 3259 if (ctx->singlestep_enabled) { 3260 /* raise exception debug */ 3261 } 3262 tcg_gen_exit_tb(NULL, 0); 3263 } 3264 } 3265 3266 static void generate_trap(DisasContext *ctx, int class, int tin) 3267 { 3268 TCGv_i32 classtemp = tcg_const_i32(class); 3269 TCGv_i32 tintemp = tcg_const_i32(tin); 3270 3271 gen_save_pc(ctx->pc); 3272 gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp); 3273 ctx->bstate = BS_EXCP; 3274 3275 tcg_temp_free(classtemp); 3276 tcg_temp_free(tintemp); 3277 } 3278 3279 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1, 3280 TCGv r2, int16_t address) 3281 { 3282 TCGLabel *jumpLabel = gen_new_label(); 3283 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel); 3284 3285 gen_goto_tb(ctx, 1, ctx->next_pc); 3286 3287 gen_set_label(jumpLabel); 3288 gen_goto_tb(ctx, 0, ctx->pc + address * 2); 3289 } 3290 3291 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1, 3292 int r2, int16_t address) 3293 { 3294 TCGv temp = tcg_const_i32(r2); 3295 gen_branch_cond(ctx, cond, r1, temp, address); 3296 tcg_temp_free(temp); 3297 } 3298 3299 static void gen_loop(DisasContext *ctx, int r1, int32_t offset) 3300 { 3301 TCGLabel *l1 = gen_new_label(); 3302 3303 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1); 3304 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1); 3305 gen_goto_tb(ctx, 1, ctx->pc + offset); 3306 gen_set_label(l1); 3307 gen_goto_tb(ctx, 0, ctx->next_pc); 3308 } 3309 3310 static void gen_fcall_save_ctx(DisasContext *ctx) 3311 { 3312 TCGv temp = tcg_temp_new(); 3313 3314 tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4); 3315 tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL); 3316 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 3317 tcg_gen_mov_tl(cpu_gpr_a[10], temp); 3318 3319 tcg_temp_free(temp); 3320 } 3321 3322 static void gen_fret(DisasContext *ctx) 3323 { 3324 TCGv temp = tcg_temp_new(); 3325 3326 tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1); 3327 tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL); 3328 tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4); 3329 tcg_gen_mov_tl(cpu_PC, temp); 3330 tcg_gen_exit_tb(NULL, 0); 3331 ctx->bstate = BS_BRANCH; 3332 3333 tcg_temp_free(temp); 3334 } 3335 3336 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, 3337 int r2 , int32_t constant , int32_t offset) 3338 { 3339 TCGv temp, temp2; 3340 int n; 3341 3342 switch (opc) { 3343 /* SB-format jumps */ 3344 case OPC1_16_SB_J: 3345 case OPC1_32_B_J: 3346 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3347 break; 3348 case OPC1_32_B_CALL: 3349 case OPC1_16_SB_CALL: 3350 gen_helper_1arg(call, ctx->next_pc); 3351 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3352 break; 3353 case OPC1_16_SB_JZ: 3354 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset); 3355 break; 3356 case OPC1_16_SB_JNZ: 3357 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset); 3358 break; 3359 /* SBC-format jumps */ 3360 case OPC1_16_SBC_JEQ: 3361 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); 3362 break; 3363 case OPC1_16_SBC_JEQ2: 3364 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, 3365 offset + 16); 3366 break; 3367 case OPC1_16_SBC_JNE: 3368 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); 3369 break; 3370 case OPC1_16_SBC_JNE2: 3371 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 3372 constant, offset + 16); 3373 break; 3374 /* SBRN-format jumps */ 3375 case OPC1_16_SBRN_JZ_T: 3376 temp = tcg_temp_new(); 3377 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 3378 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3379 tcg_temp_free(temp); 3380 break; 3381 case OPC1_16_SBRN_JNZ_T: 3382 temp = tcg_temp_new(); 3383 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant); 3384 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3385 tcg_temp_free(temp); 3386 break; 3387 /* SBR-format jumps */ 3388 case OPC1_16_SBR_JEQ: 3389 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 3390 offset); 3391 break; 3392 case OPC1_16_SBR_JEQ2: 3393 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], 3394 offset + 16); 3395 break; 3396 case OPC1_16_SBR_JNE: 3397 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 3398 offset); 3399 break; 3400 case OPC1_16_SBR_JNE2: 3401 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], 3402 offset + 16); 3403 break; 3404 case OPC1_16_SBR_JNZ: 3405 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset); 3406 break; 3407 case OPC1_16_SBR_JNZ_A: 3408 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3409 break; 3410 case OPC1_16_SBR_JGEZ: 3411 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset); 3412 break; 3413 case OPC1_16_SBR_JGTZ: 3414 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset); 3415 break; 3416 case OPC1_16_SBR_JLEZ: 3417 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset); 3418 break; 3419 case OPC1_16_SBR_JLTZ: 3420 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset); 3421 break; 3422 case OPC1_16_SBR_JZ: 3423 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset); 3424 break; 3425 case OPC1_16_SBR_JZ_A: 3426 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3427 break; 3428 case OPC1_16_SBR_LOOP: 3429 gen_loop(ctx, r1, offset * 2 - 32); 3430 break; 3431 /* SR-format jumps */ 3432 case OPC1_16_SR_JI: 3433 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe); 3434 tcg_gen_exit_tb(NULL, 0); 3435 break; 3436 case OPC2_32_SYS_RET: 3437 case OPC2_16_SR_RET: 3438 gen_helper_ret(cpu_env); 3439 tcg_gen_exit_tb(NULL, 0); 3440 break; 3441 /* B-format */ 3442 case OPC1_32_B_CALLA: 3443 gen_helper_1arg(call, ctx->next_pc); 3444 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3445 break; 3446 case OPC1_32_B_FCALL: 3447 gen_fcall_save_ctx(ctx); 3448 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3449 break; 3450 case OPC1_32_B_FCALLA: 3451 gen_fcall_save_ctx(ctx); 3452 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3453 break; 3454 case OPC1_32_B_JLA: 3455 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 3456 /* fall through */ 3457 case OPC1_32_B_JA: 3458 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset)); 3459 break; 3460 case OPC1_32_B_JL: 3461 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 3462 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3463 break; 3464 /* BOL format */ 3465 case OPCM_32_BRC_EQ_NEQ: 3466 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) { 3467 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset); 3468 } else { 3469 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset); 3470 } 3471 break; 3472 case OPCM_32_BRC_GE: 3473 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) { 3474 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset); 3475 } else { 3476 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3477 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant, 3478 offset); 3479 } 3480 break; 3481 case OPCM_32_BRC_JLT: 3482 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) { 3483 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset); 3484 } else { 3485 constant = MASK_OP_BRC_CONST4(ctx->opcode); 3486 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant, 3487 offset); 3488 } 3489 break; 3490 case OPCM_32_BRC_JNE: 3491 temp = tcg_temp_new(); 3492 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) { 3493 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3494 /* subi is unconditional */ 3495 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3496 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3497 } else { 3498 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3499 /* addi is unconditional */ 3500 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3501 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset); 3502 } 3503 tcg_temp_free(temp); 3504 break; 3505 /* BRN format */ 3506 case OPCM_32_BRN_JTT: 3507 n = MASK_OP_BRN_N(ctx->opcode); 3508 3509 temp = tcg_temp_new(); 3510 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n)); 3511 3512 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) { 3513 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset); 3514 } else { 3515 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset); 3516 } 3517 tcg_temp_free(temp); 3518 break; 3519 /* BRR Format */ 3520 case OPCM_32_BRR_EQ_NEQ: 3521 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) { 3522 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], 3523 offset); 3524 } else { 3525 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3526 offset); 3527 } 3528 break; 3529 case OPCM_32_BRR_ADDR_EQ_NEQ: 3530 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) { 3531 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2], 3532 offset); 3533 } else { 3534 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2], 3535 offset); 3536 } 3537 break; 3538 case OPCM_32_BRR_GE: 3539 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) { 3540 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2], 3541 offset); 3542 } else { 3543 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3544 offset); 3545 } 3546 break; 3547 case OPCM_32_BRR_JLT: 3548 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) { 3549 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2], 3550 offset); 3551 } else { 3552 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2], 3553 offset); 3554 } 3555 break; 3556 case OPCM_32_BRR_LOOP: 3557 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) { 3558 gen_loop(ctx, r2, offset * 2); 3559 } else { 3560 /* OPC2_32_BRR_LOOPU */ 3561 gen_goto_tb(ctx, 0, ctx->pc + offset * 2); 3562 } 3563 break; 3564 case OPCM_32_BRR_JNE: 3565 temp = tcg_temp_new(); 3566 temp2 = tcg_temp_new(); 3567 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) { 3568 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3569 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3570 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3571 /* subi is unconditional */ 3572 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3573 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3574 } else { 3575 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 3576 /* also save r2, in case of r1 == r2, so r2 is not decremented */ 3577 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]); 3578 /* addi is unconditional */ 3579 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1); 3580 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset); 3581 } 3582 tcg_temp_free(temp); 3583 tcg_temp_free(temp2); 3584 break; 3585 case OPCM_32_BRR_JNZ: 3586 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) { 3587 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset); 3588 } else { 3589 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset); 3590 } 3591 break; 3592 default: 3593 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3594 } 3595 ctx->bstate = BS_BRANCH; 3596 } 3597 3598 3599 /* 3600 * Functions for decoding instructions 3601 */ 3602 3603 static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1) 3604 { 3605 int r1; 3606 int32_t const4; 3607 TCGv temp, temp2; 3608 3609 r1 = MASK_OP_SRC_S1D(ctx->opcode); 3610 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode); 3611 3612 switch (op1) { 3613 case OPC1_16_SRC_ADD: 3614 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3615 break; 3616 case OPC1_16_SRC_ADD_A15: 3617 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4); 3618 break; 3619 case OPC1_16_SRC_ADD_15A: 3620 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4); 3621 break; 3622 case OPC1_16_SRC_ADD_A: 3623 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4); 3624 break; 3625 case OPC1_16_SRC_CADD: 3626 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3627 cpu_gpr_d[15]); 3628 break; 3629 case OPC1_16_SRC_CADDN: 3630 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1], 3631 cpu_gpr_d[15]); 3632 break; 3633 case OPC1_16_SRC_CMOV: 3634 temp = tcg_const_tl(0); 3635 temp2 = tcg_const_tl(const4); 3636 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3637 temp2, cpu_gpr_d[r1]); 3638 tcg_temp_free(temp); 3639 tcg_temp_free(temp2); 3640 break; 3641 case OPC1_16_SRC_CMOVN: 3642 temp = tcg_const_tl(0); 3643 temp2 = tcg_const_tl(const4); 3644 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3645 temp2, cpu_gpr_d[r1]); 3646 tcg_temp_free(temp); 3647 tcg_temp_free(temp2); 3648 break; 3649 case OPC1_16_SRC_EQ: 3650 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3651 const4); 3652 break; 3653 case OPC1_16_SRC_LT: 3654 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3655 const4); 3656 break; 3657 case OPC1_16_SRC_MOV: 3658 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3659 break; 3660 case OPC1_16_SRC_MOV_A: 3661 const4 = MASK_OP_SRC_CONST4(ctx->opcode); 3662 tcg_gen_movi_tl(cpu_gpr_a[r1], const4); 3663 break; 3664 case OPC1_16_SRC_MOV_E: 3665 if (tricore_feature(env, TRICORE_FEATURE_16)) { 3666 tcg_gen_movi_tl(cpu_gpr_d[r1], const4); 3667 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31); 3668 } else { 3669 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3670 } 3671 break; 3672 case OPC1_16_SRC_SH: 3673 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3674 break; 3675 case OPC1_16_SRC_SHA: 3676 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4); 3677 break; 3678 default: 3679 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3680 } 3681 } 3682 3683 static void decode_srr_opc(DisasContext *ctx, int op1) 3684 { 3685 int r1, r2; 3686 TCGv temp; 3687 3688 r1 = MASK_OP_SRR_S1D(ctx->opcode); 3689 r2 = MASK_OP_SRR_S2(ctx->opcode); 3690 3691 switch (op1) { 3692 case OPC1_16_SRR_ADD: 3693 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3694 break; 3695 case OPC1_16_SRR_ADD_A15: 3696 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3697 break; 3698 case OPC1_16_SRR_ADD_15A: 3699 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3700 break; 3701 case OPC1_16_SRR_ADD_A: 3702 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]); 3703 break; 3704 case OPC1_16_SRR_ADDS: 3705 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3706 break; 3707 case OPC1_16_SRR_AND: 3708 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3709 break; 3710 case OPC1_16_SRR_CMOV: 3711 temp = tcg_const_tl(0); 3712 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3713 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3714 tcg_temp_free(temp); 3715 break; 3716 case OPC1_16_SRR_CMOVN: 3717 temp = tcg_const_tl(0); 3718 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp, 3719 cpu_gpr_d[r2], cpu_gpr_d[r1]); 3720 tcg_temp_free(temp); 3721 break; 3722 case OPC1_16_SRR_EQ: 3723 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1], 3724 cpu_gpr_d[r2]); 3725 break; 3726 case OPC1_16_SRR_LT: 3727 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1], 3728 cpu_gpr_d[r2]); 3729 break; 3730 case OPC1_16_SRR_MOV: 3731 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]); 3732 break; 3733 case OPC1_16_SRR_MOV_A: 3734 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]); 3735 break; 3736 case OPC1_16_SRR_MOV_AA: 3737 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]); 3738 break; 3739 case OPC1_16_SRR_MOV_D: 3740 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]); 3741 break; 3742 case OPC1_16_SRR_MUL: 3743 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3744 break; 3745 case OPC1_16_SRR_OR: 3746 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3747 break; 3748 case OPC1_16_SRR_SUB: 3749 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3750 break; 3751 case OPC1_16_SRR_SUB_A15B: 3752 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]); 3753 break; 3754 case OPC1_16_SRR_SUB_15AB: 3755 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3756 break; 3757 case OPC1_16_SRR_SUBS: 3758 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3759 break; 3760 case OPC1_16_SRR_XOR: 3761 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]); 3762 break; 3763 default: 3764 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3765 } 3766 } 3767 3768 static void decode_ssr_opc(DisasContext *ctx, int op1) 3769 { 3770 int r1, r2; 3771 3772 r1 = MASK_OP_SSR_S1(ctx->opcode); 3773 r2 = MASK_OP_SSR_S2(ctx->opcode); 3774 3775 switch (op1) { 3776 case OPC1_16_SSR_ST_A: 3777 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3778 break; 3779 case OPC1_16_SSR_ST_A_POSTINC: 3780 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3781 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3782 break; 3783 case OPC1_16_SSR_ST_B: 3784 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3785 break; 3786 case OPC1_16_SSR_ST_B_POSTINC: 3787 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3788 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3789 break; 3790 case OPC1_16_SSR_ST_H: 3791 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3792 break; 3793 case OPC1_16_SSR_ST_H_POSTINC: 3794 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW); 3795 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3796 break; 3797 case OPC1_16_SSR_ST_W: 3798 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3799 break; 3800 case OPC1_16_SSR_ST_W_POSTINC: 3801 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL); 3802 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3803 break; 3804 default: 3805 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3806 } 3807 } 3808 3809 static void decode_sc_opc(DisasContext *ctx, int op1) 3810 { 3811 int32_t const16; 3812 3813 const16 = MASK_OP_SC_CONST8(ctx->opcode); 3814 3815 switch (op1) { 3816 case OPC1_16_SC_AND: 3817 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3818 break; 3819 case OPC1_16_SC_BISR: 3820 gen_helper_1arg(bisr, const16 & 0xff); 3821 break; 3822 case OPC1_16_SC_LD_A: 3823 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3824 break; 3825 case OPC1_16_SC_LD_W: 3826 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3827 break; 3828 case OPC1_16_SC_MOV: 3829 tcg_gen_movi_tl(cpu_gpr_d[15], const16); 3830 break; 3831 case OPC1_16_SC_OR: 3832 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16); 3833 break; 3834 case OPC1_16_SC_ST_A: 3835 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3836 break; 3837 case OPC1_16_SC_ST_W: 3838 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL); 3839 break; 3840 case OPC1_16_SC_SUB_A: 3841 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16); 3842 break; 3843 default: 3844 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3845 } 3846 } 3847 3848 static void decode_slr_opc(DisasContext *ctx, int op1) 3849 { 3850 int r1, r2; 3851 3852 r1 = MASK_OP_SLR_D(ctx->opcode); 3853 r2 = MASK_OP_SLR_S2(ctx->opcode); 3854 3855 switch (op1) { 3856 /* SLR-format */ 3857 case OPC1_16_SLR_LD_A: 3858 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3859 break; 3860 case OPC1_16_SLR_LD_A_POSTINC: 3861 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3862 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3863 break; 3864 case OPC1_16_SLR_LD_BU: 3865 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3866 break; 3867 case OPC1_16_SLR_LD_BU_POSTINC: 3868 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB); 3869 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1); 3870 break; 3871 case OPC1_16_SLR_LD_H: 3872 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3873 break; 3874 case OPC1_16_SLR_LD_H_POSTINC: 3875 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW); 3876 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2); 3877 break; 3878 case OPC1_16_SLR_LD_W: 3879 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3880 break; 3881 case OPC1_16_SLR_LD_W_POSTINC: 3882 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL); 3883 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4); 3884 break; 3885 default: 3886 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3887 } 3888 } 3889 3890 static void decode_sro_opc(DisasContext *ctx, int op1) 3891 { 3892 int r2; 3893 int32_t address; 3894 3895 r2 = MASK_OP_SRO_S2(ctx->opcode); 3896 address = MASK_OP_SRO_OFF4(ctx->opcode); 3897 3898 /* SRO-format */ 3899 switch (op1) { 3900 case OPC1_16_SRO_LD_A: 3901 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3902 break; 3903 case OPC1_16_SRO_LD_BU: 3904 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3905 break; 3906 case OPC1_16_SRO_LD_H: 3907 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW); 3908 break; 3909 case OPC1_16_SRO_LD_W: 3910 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3911 break; 3912 case OPC1_16_SRO_ST_A: 3913 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3914 break; 3915 case OPC1_16_SRO_ST_B: 3916 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); 3917 break; 3918 case OPC1_16_SRO_ST_H: 3919 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); 3920 break; 3921 case OPC1_16_SRO_ST_W: 3922 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); 3923 break; 3924 default: 3925 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3926 } 3927 } 3928 3929 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx) 3930 { 3931 uint32_t op2; 3932 op2 = MASK_OP_SR_OP2(ctx->opcode); 3933 3934 switch (op2) { 3935 case OPC2_16_SR_NOP: 3936 break; 3937 case OPC2_16_SR_RET: 3938 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 3939 break; 3940 case OPC2_16_SR_RFE: 3941 gen_helper_rfe(cpu_env); 3942 tcg_gen_exit_tb(NULL, 0); 3943 ctx->bstate = BS_BRANCH; 3944 break; 3945 case OPC2_16_SR_DEBUG: 3946 /* raise EXCP_DEBUG */ 3947 break; 3948 case OPC2_16_SR_FRET: 3949 gen_fret(ctx); 3950 break; 3951 default: 3952 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3953 } 3954 } 3955 3956 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx) 3957 { 3958 uint32_t op2; 3959 uint32_t r1; 3960 TCGv temp; 3961 3962 r1 = MASK_OP_SR_S1D(ctx->opcode); 3963 op2 = MASK_OP_SR_OP2(ctx->opcode); 3964 3965 switch (op2) { 3966 case OPC2_16_SR_RSUB: 3967 /* overflow only if r1 = -0x80000000 */ 3968 temp = tcg_const_i32(-0x80000000); 3969 /* calc V bit */ 3970 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp); 3971 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 3972 /* calc SV bit */ 3973 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 3974 /* sub */ 3975 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 3976 /* calc av */ 3977 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]); 3978 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV); 3979 /* calc sav */ 3980 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV); 3981 tcg_temp_free(temp); 3982 break; 3983 case OPC2_16_SR_SAT_B: 3984 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80); 3985 break; 3986 case OPC2_16_SR_SAT_BU: 3987 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff); 3988 break; 3989 case OPC2_16_SR_SAT_H: 3990 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000); 3991 break; 3992 case OPC2_16_SR_SAT_HU: 3993 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff); 3994 break; 3995 default: 3996 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 3997 } 3998 } 3999 4000 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) 4001 { 4002 int op1; 4003 int r1, r2; 4004 int32_t const16; 4005 int32_t address; 4006 TCGv temp; 4007 4008 op1 = MASK_OP_MAJOR(ctx->opcode); 4009 4010 /* handle ADDSC.A opcode only being 6 bit long */ 4011 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) { 4012 op1 = OPC1_16_SRRS_ADDSC_A; 4013 } 4014 4015 switch (op1) { 4016 case OPC1_16_SRC_ADD: 4017 case OPC1_16_SRC_ADD_A15: 4018 case OPC1_16_SRC_ADD_15A: 4019 case OPC1_16_SRC_ADD_A: 4020 case OPC1_16_SRC_CADD: 4021 case OPC1_16_SRC_CADDN: 4022 case OPC1_16_SRC_CMOV: 4023 case OPC1_16_SRC_CMOVN: 4024 case OPC1_16_SRC_EQ: 4025 case OPC1_16_SRC_LT: 4026 case OPC1_16_SRC_MOV: 4027 case OPC1_16_SRC_MOV_A: 4028 case OPC1_16_SRC_MOV_E: 4029 case OPC1_16_SRC_SH: 4030 case OPC1_16_SRC_SHA: 4031 decode_src_opc(env, ctx, op1); 4032 break; 4033 /* SRR-format */ 4034 case OPC1_16_SRR_ADD: 4035 case OPC1_16_SRR_ADD_A15: 4036 case OPC1_16_SRR_ADD_15A: 4037 case OPC1_16_SRR_ADD_A: 4038 case OPC1_16_SRR_ADDS: 4039 case OPC1_16_SRR_AND: 4040 case OPC1_16_SRR_CMOV: 4041 case OPC1_16_SRR_CMOVN: 4042 case OPC1_16_SRR_EQ: 4043 case OPC1_16_SRR_LT: 4044 case OPC1_16_SRR_MOV: 4045 case OPC1_16_SRR_MOV_A: 4046 case OPC1_16_SRR_MOV_AA: 4047 case OPC1_16_SRR_MOV_D: 4048 case OPC1_16_SRR_MUL: 4049 case OPC1_16_SRR_OR: 4050 case OPC1_16_SRR_SUB: 4051 case OPC1_16_SRR_SUB_A15B: 4052 case OPC1_16_SRR_SUB_15AB: 4053 case OPC1_16_SRR_SUBS: 4054 case OPC1_16_SRR_XOR: 4055 decode_srr_opc(ctx, op1); 4056 break; 4057 /* SSR-format */ 4058 case OPC1_16_SSR_ST_A: 4059 case OPC1_16_SSR_ST_A_POSTINC: 4060 case OPC1_16_SSR_ST_B: 4061 case OPC1_16_SSR_ST_B_POSTINC: 4062 case OPC1_16_SSR_ST_H: 4063 case OPC1_16_SSR_ST_H_POSTINC: 4064 case OPC1_16_SSR_ST_W: 4065 case OPC1_16_SSR_ST_W_POSTINC: 4066 decode_ssr_opc(ctx, op1); 4067 break; 4068 /* SRRS-format */ 4069 case OPC1_16_SRRS_ADDSC_A: 4070 r2 = MASK_OP_SRRS_S2(ctx->opcode); 4071 r1 = MASK_OP_SRRS_S1D(ctx->opcode); 4072 const16 = MASK_OP_SRRS_N(ctx->opcode); 4073 temp = tcg_temp_new(); 4074 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16); 4075 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp); 4076 tcg_temp_free(temp); 4077 break; 4078 /* SLRO-format */ 4079 case OPC1_16_SLRO_LD_A: 4080 r1 = MASK_OP_SLRO_D(ctx->opcode); 4081 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4082 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4083 break; 4084 case OPC1_16_SLRO_LD_BU: 4085 r1 = MASK_OP_SLRO_D(ctx->opcode); 4086 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4087 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 4088 break; 4089 case OPC1_16_SLRO_LD_H: 4090 r1 = MASK_OP_SLRO_D(ctx->opcode); 4091 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4092 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 4093 break; 4094 case OPC1_16_SLRO_LD_W: 4095 r1 = MASK_OP_SLRO_D(ctx->opcode); 4096 const16 = MASK_OP_SLRO_OFF4(ctx->opcode); 4097 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4098 break; 4099 /* SB-format */ 4100 case OPC1_16_SB_CALL: 4101 case OPC1_16_SB_J: 4102 case OPC1_16_SB_JNZ: 4103 case OPC1_16_SB_JZ: 4104 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode); 4105 gen_compute_branch(ctx, op1, 0, 0, 0, address); 4106 break; 4107 /* SBC-format */ 4108 case OPC1_16_SBC_JEQ: 4109 case OPC1_16_SBC_JNE: 4110 address = MASK_OP_SBC_DISP4(ctx->opcode); 4111 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 4112 gen_compute_branch(ctx, op1, 0, 0, const16, address); 4113 break; 4114 case OPC1_16_SBC_JEQ2: 4115 case OPC1_16_SBC_JNE2: 4116 if (tricore_feature(env, TRICORE_FEATURE_16)) { 4117 address = MASK_OP_SBC_DISP4(ctx->opcode); 4118 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); 4119 gen_compute_branch(ctx, op1, 0, 0, const16, address); 4120 } else { 4121 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4122 } 4123 break; 4124 /* SBRN-format */ 4125 case OPC1_16_SBRN_JNZ_T: 4126 case OPC1_16_SBRN_JZ_T: 4127 address = MASK_OP_SBRN_DISP4(ctx->opcode); 4128 const16 = MASK_OP_SBRN_N(ctx->opcode); 4129 gen_compute_branch(ctx, op1, 0, 0, const16, address); 4130 break; 4131 /* SBR-format */ 4132 case OPC1_16_SBR_JEQ2: 4133 case OPC1_16_SBR_JNE2: 4134 if (tricore_feature(env, TRICORE_FEATURE_16)) { 4135 r1 = MASK_OP_SBR_S2(ctx->opcode); 4136 address = MASK_OP_SBR_DISP4(ctx->opcode); 4137 gen_compute_branch(ctx, op1, r1, 0, 0, address); 4138 } else { 4139 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4140 } 4141 break; 4142 case OPC1_16_SBR_JEQ: 4143 case OPC1_16_SBR_JGEZ: 4144 case OPC1_16_SBR_JGTZ: 4145 case OPC1_16_SBR_JLEZ: 4146 case OPC1_16_SBR_JLTZ: 4147 case OPC1_16_SBR_JNE: 4148 case OPC1_16_SBR_JNZ: 4149 case OPC1_16_SBR_JNZ_A: 4150 case OPC1_16_SBR_JZ: 4151 case OPC1_16_SBR_JZ_A: 4152 case OPC1_16_SBR_LOOP: 4153 r1 = MASK_OP_SBR_S2(ctx->opcode); 4154 address = MASK_OP_SBR_DISP4(ctx->opcode); 4155 gen_compute_branch(ctx, op1, r1, 0, 0, address); 4156 break; 4157 /* SC-format */ 4158 case OPC1_16_SC_AND: 4159 case OPC1_16_SC_BISR: 4160 case OPC1_16_SC_LD_A: 4161 case OPC1_16_SC_LD_W: 4162 case OPC1_16_SC_MOV: 4163 case OPC1_16_SC_OR: 4164 case OPC1_16_SC_ST_A: 4165 case OPC1_16_SC_ST_W: 4166 case OPC1_16_SC_SUB_A: 4167 decode_sc_opc(ctx, op1); 4168 break; 4169 /* SLR-format */ 4170 case OPC1_16_SLR_LD_A: 4171 case OPC1_16_SLR_LD_A_POSTINC: 4172 case OPC1_16_SLR_LD_BU: 4173 case OPC1_16_SLR_LD_BU_POSTINC: 4174 case OPC1_16_SLR_LD_H: 4175 case OPC1_16_SLR_LD_H_POSTINC: 4176 case OPC1_16_SLR_LD_W: 4177 case OPC1_16_SLR_LD_W_POSTINC: 4178 decode_slr_opc(ctx, op1); 4179 break; 4180 /* SRO-format */ 4181 case OPC1_16_SRO_LD_A: 4182 case OPC1_16_SRO_LD_BU: 4183 case OPC1_16_SRO_LD_H: 4184 case OPC1_16_SRO_LD_W: 4185 case OPC1_16_SRO_ST_A: 4186 case OPC1_16_SRO_ST_B: 4187 case OPC1_16_SRO_ST_H: 4188 case OPC1_16_SRO_ST_W: 4189 decode_sro_opc(ctx, op1); 4190 break; 4191 /* SSRO-format */ 4192 case OPC1_16_SSRO_ST_A: 4193 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4194 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4195 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4196 break; 4197 case OPC1_16_SSRO_ST_B: 4198 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4199 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4200 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB); 4201 break; 4202 case OPC1_16_SSRO_ST_H: 4203 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4204 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4205 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW); 4206 break; 4207 case OPC1_16_SSRO_ST_W: 4208 r1 = MASK_OP_SSRO_S1(ctx->opcode); 4209 const16 = MASK_OP_SSRO_OFF4(ctx->opcode); 4210 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL); 4211 break; 4212 /* SR-format */ 4213 case OPCM_16_SR_SYSTEM: 4214 decode_sr_system(env, ctx); 4215 break; 4216 case OPCM_16_SR_ACCU: 4217 decode_sr_accu(env, ctx); 4218 break; 4219 case OPC1_16_SR_JI: 4220 r1 = MASK_OP_SR_S1D(ctx->opcode); 4221 gen_compute_branch(ctx, op1, r1, 0, 0, 0); 4222 break; 4223 case OPC1_16_SR_NOT: 4224 r1 = MASK_OP_SR_S1D(ctx->opcode); 4225 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]); 4226 break; 4227 default: 4228 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4229 } 4230 } 4231 4232 /* 4233 * 32 bit instructions 4234 */ 4235 4236 /* ABS-format */ 4237 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx) 4238 { 4239 int32_t op2; 4240 int32_t r1; 4241 uint32_t address; 4242 TCGv temp; 4243 4244 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4245 address = MASK_OP_ABS_OFF18(ctx->opcode); 4246 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4247 4248 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4249 4250 switch (op2) { 4251 case OPC2_32_ABS_LD_A: 4252 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 4253 break; 4254 case OPC2_32_ABS_LD_D: 4255 CHECK_REG_PAIR(r1); 4256 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4257 break; 4258 case OPC2_32_ABS_LD_DA: 4259 CHECK_REG_PAIR(r1); 4260 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4261 break; 4262 case OPC2_32_ABS_LD_W: 4263 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 4264 break; 4265 default: 4266 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4267 } 4268 4269 tcg_temp_free(temp); 4270 } 4271 4272 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx) 4273 { 4274 int32_t op2; 4275 int32_t r1; 4276 uint32_t address; 4277 TCGv temp; 4278 4279 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4280 address = MASK_OP_ABS_OFF18(ctx->opcode); 4281 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4282 4283 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4284 4285 switch (op2) { 4286 case OPC2_32_ABS_LD_B: 4287 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB); 4288 break; 4289 case OPC2_32_ABS_LD_BU: 4290 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 4291 break; 4292 case OPC2_32_ABS_LD_H: 4293 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW); 4294 break; 4295 case OPC2_32_ABS_LD_HU: 4296 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 4297 break; 4298 default: 4299 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4300 } 4301 4302 tcg_temp_free(temp); 4303 } 4304 4305 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx) 4306 { 4307 int32_t op2; 4308 int32_t r1; 4309 uint32_t address; 4310 TCGv temp; 4311 4312 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4313 address = MASK_OP_ABS_OFF18(ctx->opcode); 4314 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4315 4316 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4317 4318 switch (op2) { 4319 case OPC2_32_ABS_LDMST: 4320 gen_ldmst(ctx, r1, temp); 4321 break; 4322 case OPC2_32_ABS_SWAP_W: 4323 gen_swap(ctx, r1, temp); 4324 break; 4325 default: 4326 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4327 } 4328 4329 tcg_temp_free(temp); 4330 } 4331 4332 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx) 4333 { 4334 uint32_t op2; 4335 int32_t off18; 4336 4337 off18 = MASK_OP_ABS_OFF18(ctx->opcode); 4338 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4339 4340 switch (op2) { 4341 case OPC2_32_ABS_LDLCX: 4342 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18)); 4343 break; 4344 case OPC2_32_ABS_LDUCX: 4345 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18)); 4346 break; 4347 case OPC2_32_ABS_STLCX: 4348 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18)); 4349 break; 4350 case OPC2_32_ABS_STUCX: 4351 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18)); 4352 break; 4353 default: 4354 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4355 } 4356 } 4357 4358 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx) 4359 { 4360 int32_t op2; 4361 int32_t r1; 4362 uint32_t address; 4363 TCGv temp; 4364 4365 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4366 address = MASK_OP_ABS_OFF18(ctx->opcode); 4367 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4368 4369 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4370 4371 switch (op2) { 4372 case OPC2_32_ABS_ST_A: 4373 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL); 4374 break; 4375 case OPC2_32_ABS_ST_D: 4376 CHECK_REG_PAIR(r1); 4377 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4378 break; 4379 case OPC2_32_ABS_ST_DA: 4380 CHECK_REG_PAIR(r1); 4381 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4382 break; 4383 case OPC2_32_ABS_ST_W: 4384 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL); 4385 break; 4386 default: 4387 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4388 } 4389 tcg_temp_free(temp); 4390 } 4391 4392 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx) 4393 { 4394 int32_t op2; 4395 int32_t r1; 4396 uint32_t address; 4397 TCGv temp; 4398 4399 r1 = MASK_OP_ABS_S1D(ctx->opcode); 4400 address = MASK_OP_ABS_OFF18(ctx->opcode); 4401 op2 = MASK_OP_ABS_OP2(ctx->opcode); 4402 4403 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 4404 4405 switch (op2) { 4406 case OPC2_32_ABS_ST_B: 4407 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB); 4408 break; 4409 case OPC2_32_ABS_ST_H: 4410 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 4411 break; 4412 default: 4413 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4414 } 4415 tcg_temp_free(temp); 4416 } 4417 4418 /* Bit-format */ 4419 4420 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx) 4421 { 4422 uint32_t op2; 4423 int r1, r2, r3; 4424 int pos1, pos2; 4425 4426 r1 = MASK_OP_BIT_S1(ctx->opcode); 4427 r2 = MASK_OP_BIT_S2(ctx->opcode); 4428 r3 = MASK_OP_BIT_D(ctx->opcode); 4429 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4430 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4431 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4432 4433 4434 switch (op2) { 4435 case OPC2_32_BIT_AND_AND_T: 4436 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4437 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl); 4438 break; 4439 case OPC2_32_BIT_AND_ANDN_T: 4440 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4441 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl); 4442 break; 4443 case OPC2_32_BIT_AND_NOR_T: 4444 if (TCG_TARGET_HAS_andc_i32) { 4445 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4446 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl); 4447 } else { 4448 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4449 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl); 4450 } 4451 break; 4452 case OPC2_32_BIT_AND_OR_T: 4453 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4454 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl); 4455 break; 4456 default: 4457 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4458 } 4459 } 4460 4461 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx) 4462 { 4463 uint32_t op2; 4464 int r1, r2, r3; 4465 int pos1, pos2; 4466 r1 = MASK_OP_BIT_S1(ctx->opcode); 4467 r2 = MASK_OP_BIT_S2(ctx->opcode); 4468 r3 = MASK_OP_BIT_D(ctx->opcode); 4469 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4470 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4471 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4472 4473 switch (op2) { 4474 case OPC2_32_BIT_AND_T: 4475 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4476 pos1, pos2, &tcg_gen_and_tl); 4477 break; 4478 case OPC2_32_BIT_ANDN_T: 4479 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4480 pos1, pos2, &tcg_gen_andc_tl); 4481 break; 4482 case OPC2_32_BIT_NOR_T: 4483 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4484 pos1, pos2, &tcg_gen_nor_tl); 4485 break; 4486 case OPC2_32_BIT_OR_T: 4487 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4488 pos1, pos2, &tcg_gen_or_tl); 4489 break; 4490 default: 4491 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4492 } 4493 } 4494 4495 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx) 4496 { 4497 uint32_t op2; 4498 int r1, r2, r3; 4499 int pos1, pos2; 4500 TCGv temp; 4501 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4502 r1 = MASK_OP_BIT_S1(ctx->opcode); 4503 r2 = MASK_OP_BIT_S2(ctx->opcode); 4504 r3 = MASK_OP_BIT_D(ctx->opcode); 4505 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4506 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4507 4508 temp = tcg_temp_new(); 4509 4510 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2); 4511 if (op2 == OPC2_32_BIT_INSN_T) { 4512 tcg_gen_not_tl(temp, temp); 4513 } 4514 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1); 4515 tcg_temp_free(temp); 4516 } 4517 4518 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx) 4519 { 4520 uint32_t op2; 4521 4522 int r1, r2, r3; 4523 int pos1, pos2; 4524 4525 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4526 r1 = MASK_OP_BIT_S1(ctx->opcode); 4527 r2 = MASK_OP_BIT_S2(ctx->opcode); 4528 r3 = MASK_OP_BIT_D(ctx->opcode); 4529 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4530 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4531 4532 switch (op2) { 4533 case OPC2_32_BIT_NAND_T: 4534 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4535 pos1, pos2, &tcg_gen_nand_tl); 4536 break; 4537 case OPC2_32_BIT_ORN_T: 4538 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4539 pos1, pos2, &tcg_gen_orc_tl); 4540 break; 4541 case OPC2_32_BIT_XNOR_T: 4542 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4543 pos1, pos2, &tcg_gen_eqv_tl); 4544 break; 4545 case OPC2_32_BIT_XOR_T: 4546 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4547 pos1, pos2, &tcg_gen_xor_tl); 4548 break; 4549 default: 4550 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4551 } 4552 } 4553 4554 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx) 4555 { 4556 uint32_t op2; 4557 4558 int r1, r2, r3; 4559 int pos1, pos2; 4560 4561 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4562 r1 = MASK_OP_BIT_S1(ctx->opcode); 4563 r2 = MASK_OP_BIT_S2(ctx->opcode); 4564 r3 = MASK_OP_BIT_D(ctx->opcode); 4565 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4566 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4567 4568 switch (op2) { 4569 case OPC2_32_BIT_OR_AND_T: 4570 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4571 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl); 4572 break; 4573 case OPC2_32_BIT_OR_ANDN_T: 4574 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4575 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl); 4576 break; 4577 case OPC2_32_BIT_OR_NOR_T: 4578 if (TCG_TARGET_HAS_orc_i32) { 4579 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4580 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl); 4581 } else { 4582 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4583 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl); 4584 } 4585 break; 4586 case OPC2_32_BIT_OR_OR_T: 4587 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 4588 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl); 4589 break; 4590 default: 4591 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4592 } 4593 } 4594 4595 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx) 4596 { 4597 uint32_t op2; 4598 int r1, r2, r3; 4599 int pos1, pos2; 4600 TCGv temp; 4601 4602 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4603 r1 = MASK_OP_BIT_S1(ctx->opcode); 4604 r2 = MASK_OP_BIT_S2(ctx->opcode); 4605 r3 = MASK_OP_BIT_D(ctx->opcode); 4606 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4607 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4608 4609 temp = tcg_temp_new(); 4610 4611 switch (op2) { 4612 case OPC2_32_BIT_SH_AND_T: 4613 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4614 pos1, pos2, &tcg_gen_and_tl); 4615 break; 4616 case OPC2_32_BIT_SH_ANDN_T: 4617 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4618 pos1, pos2, &tcg_gen_andc_tl); 4619 break; 4620 case OPC2_32_BIT_SH_NOR_T: 4621 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4622 pos1, pos2, &tcg_gen_nor_tl); 4623 break; 4624 case OPC2_32_BIT_SH_OR_T: 4625 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4626 pos1, pos2, &tcg_gen_or_tl); 4627 break; 4628 default: 4629 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4630 } 4631 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4632 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4633 tcg_temp_free(temp); 4634 } 4635 4636 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx) 4637 { 4638 uint32_t op2; 4639 int r1, r2, r3; 4640 int pos1, pos2; 4641 TCGv temp; 4642 4643 op2 = MASK_OP_BIT_OP2(ctx->opcode); 4644 r1 = MASK_OP_BIT_S1(ctx->opcode); 4645 r2 = MASK_OP_BIT_S2(ctx->opcode); 4646 r3 = MASK_OP_BIT_D(ctx->opcode); 4647 pos1 = MASK_OP_BIT_POS1(ctx->opcode); 4648 pos2 = MASK_OP_BIT_POS2(ctx->opcode); 4649 4650 temp = tcg_temp_new(); 4651 4652 switch (op2) { 4653 case OPC2_32_BIT_SH_NAND_T: 4654 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] , 4655 pos1, pos2, &tcg_gen_nand_tl); 4656 break; 4657 case OPC2_32_BIT_SH_ORN_T: 4658 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4659 pos1, pos2, &tcg_gen_orc_tl); 4660 break; 4661 case OPC2_32_BIT_SH_XNOR_T: 4662 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4663 pos1, pos2, &tcg_gen_eqv_tl); 4664 break; 4665 case OPC2_32_BIT_SH_XOR_T: 4666 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2], 4667 pos1, pos2, &tcg_gen_xor_tl); 4668 break; 4669 default: 4670 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4671 } 4672 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1); 4673 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 4674 tcg_temp_free(temp); 4675 } 4676 4677 /* BO-format */ 4678 4679 4680 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env, 4681 DisasContext *ctx) 4682 { 4683 uint32_t op2; 4684 uint32_t off10; 4685 int32_t r1, r2; 4686 TCGv temp; 4687 4688 r1 = MASK_OP_BO_S1D(ctx->opcode); 4689 r2 = MASK_OP_BO_S2(ctx->opcode); 4690 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4691 op2 = MASK_OP_BO_OP2(ctx->opcode); 4692 4693 switch (op2) { 4694 case OPC2_32_BO_CACHEA_WI_SHORTOFF: 4695 case OPC2_32_BO_CACHEA_W_SHORTOFF: 4696 case OPC2_32_BO_CACHEA_I_SHORTOFF: 4697 /* instruction to access the cache */ 4698 break; 4699 case OPC2_32_BO_CACHEA_WI_POSTINC: 4700 case OPC2_32_BO_CACHEA_W_POSTINC: 4701 case OPC2_32_BO_CACHEA_I_POSTINC: 4702 /* instruction to access the cache, but we still need to handle 4703 the addressing mode */ 4704 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4705 break; 4706 case OPC2_32_BO_CACHEA_WI_PREINC: 4707 case OPC2_32_BO_CACHEA_W_PREINC: 4708 case OPC2_32_BO_CACHEA_I_PREINC: 4709 /* instruction to access the cache, but we still need to handle 4710 the addressing mode */ 4711 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4712 break; 4713 case OPC2_32_BO_CACHEI_WI_SHORTOFF: 4714 case OPC2_32_BO_CACHEI_W_SHORTOFF: 4715 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 4716 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4717 } 4718 break; 4719 case OPC2_32_BO_CACHEI_W_POSTINC: 4720 case OPC2_32_BO_CACHEI_WI_POSTINC: 4721 if (tricore_feature(env, TRICORE_FEATURE_131)) { 4722 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4723 } else { 4724 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4725 } 4726 break; 4727 case OPC2_32_BO_CACHEI_W_PREINC: 4728 case OPC2_32_BO_CACHEI_WI_PREINC: 4729 if (tricore_feature(env, TRICORE_FEATURE_131)) { 4730 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4731 } else { 4732 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4733 } 4734 break; 4735 case OPC2_32_BO_ST_A_SHORTOFF: 4736 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4737 break; 4738 case OPC2_32_BO_ST_A_POSTINC: 4739 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4740 MO_LESL); 4741 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4742 break; 4743 case OPC2_32_BO_ST_A_PREINC: 4744 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL); 4745 break; 4746 case OPC2_32_BO_ST_B_SHORTOFF: 4747 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4748 break; 4749 case OPC2_32_BO_ST_B_POSTINC: 4750 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4751 MO_UB); 4752 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4753 break; 4754 case OPC2_32_BO_ST_B_PREINC: 4755 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4756 break; 4757 case OPC2_32_BO_ST_D_SHORTOFF: 4758 CHECK_REG_PAIR(r1); 4759 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 4760 off10, ctx); 4761 break; 4762 case OPC2_32_BO_ST_D_POSTINC: 4763 CHECK_REG_PAIR(r1); 4764 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 4765 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4766 break; 4767 case OPC2_32_BO_ST_D_PREINC: 4768 CHECK_REG_PAIR(r1); 4769 temp = tcg_temp_new(); 4770 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4771 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 4772 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4773 tcg_temp_free(temp); 4774 break; 4775 case OPC2_32_BO_ST_DA_SHORTOFF: 4776 CHECK_REG_PAIR(r1); 4777 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 4778 off10, ctx); 4779 break; 4780 case OPC2_32_BO_ST_DA_POSTINC: 4781 CHECK_REG_PAIR(r1); 4782 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 4783 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4784 break; 4785 case OPC2_32_BO_ST_DA_PREINC: 4786 CHECK_REG_PAIR(r1); 4787 temp = tcg_temp_new(); 4788 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 4789 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 4790 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 4791 tcg_temp_free(temp); 4792 break; 4793 case OPC2_32_BO_ST_H_SHORTOFF: 4794 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4795 break; 4796 case OPC2_32_BO_ST_H_POSTINC: 4797 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4798 MO_LEUW); 4799 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4800 break; 4801 case OPC2_32_BO_ST_H_PREINC: 4802 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 4803 break; 4804 case OPC2_32_BO_ST_Q_SHORTOFF: 4805 temp = tcg_temp_new(); 4806 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4807 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4808 tcg_temp_free(temp); 4809 break; 4810 case OPC2_32_BO_ST_Q_POSTINC: 4811 temp = tcg_temp_new(); 4812 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4813 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx, 4814 MO_LEUW); 4815 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4816 tcg_temp_free(temp); 4817 break; 4818 case OPC2_32_BO_ST_Q_PREINC: 4819 temp = tcg_temp_new(); 4820 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4821 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW); 4822 tcg_temp_free(temp); 4823 break; 4824 case OPC2_32_BO_ST_W_SHORTOFF: 4825 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4826 break; 4827 case OPC2_32_BO_ST_W_POSTINC: 4828 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4829 MO_LEUL); 4830 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4831 break; 4832 case OPC2_32_BO_ST_W_PREINC: 4833 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4834 break; 4835 default: 4836 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4837 } 4838 } 4839 4840 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env, 4841 DisasContext *ctx) 4842 { 4843 uint32_t op2; 4844 uint32_t off10; 4845 int32_t r1, r2; 4846 TCGv temp, temp2, temp3; 4847 4848 r1 = MASK_OP_BO_S1D(ctx->opcode); 4849 r2 = MASK_OP_BO_S2(ctx->opcode); 4850 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4851 op2 = MASK_OP_BO_OP2(ctx->opcode); 4852 4853 temp = tcg_temp_new(); 4854 temp2 = tcg_temp_new(); 4855 temp3 = tcg_const_i32(off10); 4856 CHECK_REG_PAIR(r2); 4857 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 4858 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4859 4860 switch (op2) { 4861 case OPC2_32_BO_CACHEA_WI_BR: 4862 case OPC2_32_BO_CACHEA_W_BR: 4863 case OPC2_32_BO_CACHEA_I_BR: 4864 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4865 break; 4866 case OPC2_32_BO_CACHEA_WI_CIRC: 4867 case OPC2_32_BO_CACHEA_W_CIRC: 4868 case OPC2_32_BO_CACHEA_I_CIRC: 4869 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4870 break; 4871 case OPC2_32_BO_ST_A_BR: 4872 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4873 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4874 break; 4875 case OPC2_32_BO_ST_A_CIRC: 4876 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4877 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4878 break; 4879 case OPC2_32_BO_ST_B_BR: 4880 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4881 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4882 break; 4883 case OPC2_32_BO_ST_B_CIRC: 4884 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 4885 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4886 break; 4887 case OPC2_32_BO_ST_D_BR: 4888 CHECK_REG_PAIR(r1); 4889 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 4890 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4891 break; 4892 case OPC2_32_BO_ST_D_CIRC: 4893 CHECK_REG_PAIR(r1); 4894 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4895 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4896 tcg_gen_addi_tl(temp, temp, 4); 4897 tcg_gen_rem_tl(temp, temp, temp2); 4898 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4899 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4900 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4901 break; 4902 case OPC2_32_BO_ST_DA_BR: 4903 CHECK_REG_PAIR(r1); 4904 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 4905 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4906 break; 4907 case OPC2_32_BO_ST_DA_CIRC: 4908 CHECK_REG_PAIR(r1); 4909 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 4910 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 4911 tcg_gen_addi_tl(temp, temp, 4); 4912 tcg_gen_rem_tl(temp, temp, temp2); 4913 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 4914 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 4915 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4916 break; 4917 case OPC2_32_BO_ST_H_BR: 4918 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4919 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4920 break; 4921 case OPC2_32_BO_ST_H_CIRC: 4922 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 4923 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4924 break; 4925 case OPC2_32_BO_ST_Q_BR: 4926 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4927 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4928 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4929 break; 4930 case OPC2_32_BO_ST_Q_CIRC: 4931 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16); 4932 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW); 4933 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4934 break; 4935 case OPC2_32_BO_ST_W_BR: 4936 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4937 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 4938 break; 4939 case OPC2_32_BO_ST_W_CIRC: 4940 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 4941 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 4942 break; 4943 default: 4944 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 4945 } 4946 tcg_temp_free(temp); 4947 tcg_temp_free(temp2); 4948 tcg_temp_free(temp3); 4949 } 4950 4951 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env, 4952 DisasContext *ctx) 4953 { 4954 uint32_t op2; 4955 uint32_t off10; 4956 int32_t r1, r2; 4957 TCGv temp; 4958 4959 r1 = MASK_OP_BO_S1D(ctx->opcode); 4960 r2 = MASK_OP_BO_S2(ctx->opcode); 4961 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 4962 op2 = MASK_OP_BO_OP2(ctx->opcode); 4963 4964 switch (op2) { 4965 case OPC2_32_BO_LD_A_SHORTOFF: 4966 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4967 break; 4968 case OPC2_32_BO_LD_A_POSTINC: 4969 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, 4970 MO_LEUL); 4971 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4972 break; 4973 case OPC2_32_BO_LD_A_PREINC: 4974 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL); 4975 break; 4976 case OPC2_32_BO_LD_B_SHORTOFF: 4977 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4978 break; 4979 case OPC2_32_BO_LD_B_POSTINC: 4980 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4981 MO_SB); 4982 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4983 break; 4984 case OPC2_32_BO_LD_B_PREINC: 4985 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4986 break; 4987 case OPC2_32_BO_LD_BU_SHORTOFF: 4988 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB); 4989 break; 4990 case OPC2_32_BO_LD_BU_POSTINC: 4991 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 4992 MO_UB); 4993 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 4994 break; 4995 case OPC2_32_BO_LD_BU_PREINC: 4996 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB); 4997 break; 4998 case OPC2_32_BO_LD_D_SHORTOFF: 4999 CHECK_REG_PAIR(r1); 5000 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], 5001 off10, ctx); 5002 break; 5003 case OPC2_32_BO_LD_D_POSTINC: 5004 CHECK_REG_PAIR(r1); 5005 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx); 5006 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5007 break; 5008 case OPC2_32_BO_LD_D_PREINC: 5009 CHECK_REG_PAIR(r1); 5010 temp = tcg_temp_new(); 5011 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5012 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx); 5013 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 5014 tcg_temp_free(temp); 5015 break; 5016 case OPC2_32_BO_LD_DA_SHORTOFF: 5017 CHECK_REG_PAIR(r1); 5018 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], 5019 off10, ctx); 5020 break; 5021 case OPC2_32_BO_LD_DA_POSTINC: 5022 CHECK_REG_PAIR(r1); 5023 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx); 5024 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5025 break; 5026 case OPC2_32_BO_LD_DA_PREINC: 5027 CHECK_REG_PAIR(r1); 5028 temp = tcg_temp_new(); 5029 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5030 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx); 5031 tcg_gen_mov_tl(cpu_gpr_a[r2], temp); 5032 tcg_temp_free(temp); 5033 break; 5034 case OPC2_32_BO_LD_H_SHORTOFF: 5035 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 5036 break; 5037 case OPC2_32_BO_LD_H_POSTINC: 5038 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5039 MO_LESW); 5040 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5041 break; 5042 case OPC2_32_BO_LD_H_PREINC: 5043 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW); 5044 break; 5045 case OPC2_32_BO_LD_HU_SHORTOFF: 5046 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5047 break; 5048 case OPC2_32_BO_LD_HU_POSTINC: 5049 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5050 MO_LEUW); 5051 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5052 break; 5053 case OPC2_32_BO_LD_HU_PREINC: 5054 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5055 break; 5056 case OPC2_32_BO_LD_Q_SHORTOFF: 5057 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5058 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5059 break; 5060 case OPC2_32_BO_LD_Q_POSTINC: 5061 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5062 MO_LEUW); 5063 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5064 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5065 break; 5066 case OPC2_32_BO_LD_Q_PREINC: 5067 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW); 5068 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5069 break; 5070 case OPC2_32_BO_LD_W_SHORTOFF: 5071 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 5072 break; 5073 case OPC2_32_BO_LD_W_POSTINC: 5074 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, 5075 MO_LEUL); 5076 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5077 break; 5078 case OPC2_32_BO_LD_W_PREINC: 5079 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL); 5080 break; 5081 default: 5082 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5083 } 5084 } 5085 5086 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env, 5087 DisasContext *ctx) 5088 { 5089 uint32_t op2; 5090 uint32_t off10; 5091 int r1, r2; 5092 5093 TCGv temp, temp2, temp3; 5094 5095 r1 = MASK_OP_BO_S1D(ctx->opcode); 5096 r2 = MASK_OP_BO_S2(ctx->opcode); 5097 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 5098 op2 = MASK_OP_BO_OP2(ctx->opcode); 5099 5100 temp = tcg_temp_new(); 5101 temp2 = tcg_temp_new(); 5102 temp3 = tcg_const_i32(off10); 5103 CHECK_REG_PAIR(r2); 5104 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 5105 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5106 5107 5108 switch (op2) { 5109 case OPC2_32_BO_LD_A_BR: 5110 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 5111 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5112 break; 5113 case OPC2_32_BO_LD_A_CIRC: 5114 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 5115 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5116 break; 5117 case OPC2_32_BO_LD_B_BR: 5118 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 5119 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5120 break; 5121 case OPC2_32_BO_LD_B_CIRC: 5122 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB); 5123 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5124 break; 5125 case OPC2_32_BO_LD_BU_BR: 5126 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 5127 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5128 break; 5129 case OPC2_32_BO_LD_BU_CIRC: 5130 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB); 5131 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5132 break; 5133 case OPC2_32_BO_LD_D_BR: 5134 CHECK_REG_PAIR(r1); 5135 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx); 5136 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5137 break; 5138 case OPC2_32_BO_LD_D_CIRC: 5139 CHECK_REG_PAIR(r1); 5140 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 5141 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 5142 tcg_gen_addi_tl(temp, temp, 4); 5143 tcg_gen_rem_tl(temp, temp, temp2); 5144 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5145 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL); 5146 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5147 break; 5148 case OPC2_32_BO_LD_DA_BR: 5149 CHECK_REG_PAIR(r1); 5150 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx); 5151 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5152 break; 5153 case OPC2_32_BO_LD_DA_CIRC: 5154 CHECK_REG_PAIR(r1); 5155 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL); 5156 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16); 5157 tcg_gen_addi_tl(temp, temp, 4); 5158 tcg_gen_rem_tl(temp, temp, temp2); 5159 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5160 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL); 5161 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5162 break; 5163 case OPC2_32_BO_LD_H_BR: 5164 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 5165 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5166 break; 5167 case OPC2_32_BO_LD_H_CIRC: 5168 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW); 5169 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5170 break; 5171 case OPC2_32_BO_LD_HU_BR: 5172 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5173 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5174 break; 5175 case OPC2_32_BO_LD_HU_CIRC: 5176 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5177 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5178 break; 5179 case OPC2_32_BO_LD_Q_BR: 5180 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5181 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5182 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5183 break; 5184 case OPC2_32_BO_LD_Q_CIRC: 5185 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW); 5186 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 5187 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5188 break; 5189 case OPC2_32_BO_LD_W_BR: 5190 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 5191 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5192 break; 5193 case OPC2_32_BO_LD_W_CIRC: 5194 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL); 5195 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5196 break; 5197 default: 5198 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5199 } 5200 tcg_temp_free(temp); 5201 tcg_temp_free(temp2); 5202 tcg_temp_free(temp3); 5203 } 5204 5205 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env, 5206 DisasContext *ctx) 5207 { 5208 uint32_t op2; 5209 uint32_t off10; 5210 int r1, r2; 5211 5212 TCGv temp, temp2; 5213 5214 r1 = MASK_OP_BO_S1D(ctx->opcode); 5215 r2 = MASK_OP_BO_S2(ctx->opcode); 5216 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 5217 op2 = MASK_OP_BO_OP2(ctx->opcode); 5218 5219 5220 temp = tcg_temp_new(); 5221 temp2 = tcg_temp_new(); 5222 5223 switch (op2) { 5224 case OPC2_32_BO_LDLCX_SHORTOFF: 5225 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5226 gen_helper_ldlcx(cpu_env, temp); 5227 break; 5228 case OPC2_32_BO_LDMST_SHORTOFF: 5229 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5230 gen_ldmst(ctx, r1, temp); 5231 break; 5232 case OPC2_32_BO_LDMST_POSTINC: 5233 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 5234 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5235 break; 5236 case OPC2_32_BO_LDMST_PREINC: 5237 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5238 gen_ldmst(ctx, r1, cpu_gpr_a[r2]); 5239 break; 5240 case OPC2_32_BO_LDUCX_SHORTOFF: 5241 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5242 gen_helper_lducx(cpu_env, temp); 5243 break; 5244 case OPC2_32_BO_LEA_SHORTOFF: 5245 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10); 5246 break; 5247 case OPC2_32_BO_STLCX_SHORTOFF: 5248 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5249 gen_helper_stlcx(cpu_env, temp); 5250 break; 5251 case OPC2_32_BO_STUCX_SHORTOFF: 5252 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5253 gen_helper_stucx(cpu_env, temp); 5254 break; 5255 case OPC2_32_BO_SWAP_W_SHORTOFF: 5256 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5257 gen_swap(ctx, r1, temp); 5258 break; 5259 case OPC2_32_BO_SWAP_W_POSTINC: 5260 gen_swap(ctx, r1, cpu_gpr_a[r2]); 5261 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5262 break; 5263 case OPC2_32_BO_SWAP_W_PREINC: 5264 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5265 gen_swap(ctx, r1, cpu_gpr_a[r2]); 5266 break; 5267 case OPC2_32_BO_CMPSWAP_W_SHORTOFF: 5268 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5269 gen_cmpswap(ctx, r1, temp); 5270 break; 5271 case OPC2_32_BO_CMPSWAP_W_POSTINC: 5272 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 5273 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5274 break; 5275 case OPC2_32_BO_CMPSWAP_W_PREINC: 5276 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5277 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]); 5278 break; 5279 case OPC2_32_BO_SWAPMSK_W_SHORTOFF: 5280 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10); 5281 gen_swapmsk(ctx, r1, temp); 5282 break; 5283 case OPC2_32_BO_SWAPMSK_W_POSTINC: 5284 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 5285 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5286 break; 5287 case OPC2_32_BO_SWAPMSK_W_PREINC: 5288 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); 5289 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]); 5290 break; 5291 default: 5292 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5293 } 5294 tcg_temp_free(temp); 5295 tcg_temp_free(temp2); 5296 } 5297 5298 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env, 5299 DisasContext *ctx) 5300 { 5301 uint32_t op2; 5302 uint32_t off10; 5303 int r1, r2; 5304 5305 TCGv temp, temp2, temp3; 5306 5307 r1 = MASK_OP_BO_S1D(ctx->opcode); 5308 r2 = MASK_OP_BO_S2(ctx->opcode); 5309 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode); 5310 op2 = MASK_OP_BO_OP2(ctx->opcode); 5311 5312 temp = tcg_temp_new(); 5313 temp2 = tcg_temp_new(); 5314 temp3 = tcg_const_i32(off10); 5315 CHECK_REG_PAIR(r2); 5316 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]); 5317 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp); 5318 5319 switch (op2) { 5320 case OPC2_32_BO_LDMST_BR: 5321 gen_ldmst(ctx, r1, temp2); 5322 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5323 break; 5324 case OPC2_32_BO_LDMST_CIRC: 5325 gen_ldmst(ctx, r1, temp2); 5326 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5327 break; 5328 case OPC2_32_BO_SWAP_W_BR: 5329 gen_swap(ctx, r1, temp2); 5330 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5331 break; 5332 case OPC2_32_BO_SWAP_W_CIRC: 5333 gen_swap(ctx, r1, temp2); 5334 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5335 break; 5336 case OPC2_32_BO_CMPSWAP_W_BR: 5337 gen_cmpswap(ctx, r1, temp2); 5338 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5339 break; 5340 case OPC2_32_BO_CMPSWAP_W_CIRC: 5341 gen_cmpswap(ctx, r1, temp2); 5342 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5343 break; 5344 case OPC2_32_BO_SWAPMSK_W_BR: 5345 gen_swapmsk(ctx, r1, temp2); 5346 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]); 5347 break; 5348 case OPC2_32_BO_SWAPMSK_W_CIRC: 5349 gen_swapmsk(ctx, r1, temp2); 5350 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3); 5351 break; 5352 default: 5353 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5354 } 5355 5356 tcg_temp_free(temp); 5357 tcg_temp_free(temp2); 5358 tcg_temp_free(temp3); 5359 } 5360 5361 static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1) 5362 { 5363 int r1, r2; 5364 int32_t address; 5365 TCGv temp; 5366 5367 r1 = MASK_OP_BOL_S1D(ctx->opcode); 5368 r2 = MASK_OP_BOL_S2(ctx->opcode); 5369 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode); 5370 5371 switch (op1) { 5372 case OPC1_32_BOL_LD_A_LONGOFF: 5373 temp = tcg_temp_new(); 5374 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 5375 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL); 5376 tcg_temp_free(temp); 5377 break; 5378 case OPC1_32_BOL_LD_W_LONGOFF: 5379 temp = tcg_temp_new(); 5380 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address); 5381 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL); 5382 tcg_temp_free(temp); 5383 break; 5384 case OPC1_32_BOL_LEA_LONGOFF: 5385 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address); 5386 break; 5387 case OPC1_32_BOL_ST_A_LONGOFF: 5388 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5389 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL); 5390 } else { 5391 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5392 } 5393 break; 5394 case OPC1_32_BOL_ST_W_LONGOFF: 5395 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL); 5396 break; 5397 case OPC1_32_BOL_LD_B_LONGOFF: 5398 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5399 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 5400 } else { 5401 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5402 } 5403 break; 5404 case OPC1_32_BOL_LD_BU_LONGOFF: 5405 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5406 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB); 5407 } else { 5408 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5409 } 5410 break; 5411 case OPC1_32_BOL_LD_H_LONGOFF: 5412 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5413 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 5414 } else { 5415 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5416 } 5417 break; 5418 case OPC1_32_BOL_LD_HU_LONGOFF: 5419 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5420 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW); 5421 } else { 5422 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5423 } 5424 break; 5425 case OPC1_32_BOL_ST_B_LONGOFF: 5426 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5427 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB); 5428 } else { 5429 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5430 } 5431 break; 5432 case OPC1_32_BOL_ST_H_LONGOFF: 5433 if (tricore_feature(env, TRICORE_FEATURE_16)) { 5434 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); 5435 } else { 5436 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5437 } 5438 break; 5439 default: 5440 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5441 } 5442 } 5443 5444 /* RC format */ 5445 static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx) 5446 { 5447 uint32_t op2; 5448 int r1, r2; 5449 int32_t const9; 5450 TCGv temp; 5451 5452 r2 = MASK_OP_RC_D(ctx->opcode); 5453 r1 = MASK_OP_RC_S1(ctx->opcode); 5454 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5455 op2 = MASK_OP_RC_OP2(ctx->opcode); 5456 5457 temp = tcg_temp_new(); 5458 5459 switch (op2) { 5460 case OPC2_32_RC_AND: 5461 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5462 break; 5463 case OPC2_32_RC_ANDN: 5464 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 5465 break; 5466 case OPC2_32_RC_NAND: 5467 tcg_gen_movi_tl(temp, const9); 5468 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 5469 break; 5470 case OPC2_32_RC_NOR: 5471 tcg_gen_movi_tl(temp, const9); 5472 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp); 5473 break; 5474 case OPC2_32_RC_OR: 5475 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5476 break; 5477 case OPC2_32_RC_ORN: 5478 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9); 5479 break; 5480 case OPC2_32_RC_SH: 5481 const9 = sextract32(const9, 0, 6); 5482 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5483 break; 5484 case OPC2_32_RC_SH_H: 5485 const9 = sextract32(const9, 0, 5); 5486 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5487 break; 5488 case OPC2_32_RC_SHA: 5489 const9 = sextract32(const9, 0, 6); 5490 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5491 break; 5492 case OPC2_32_RC_SHA_H: 5493 const9 = sextract32(const9, 0, 5); 5494 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5495 break; 5496 case OPC2_32_RC_SHAS: 5497 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5498 break; 5499 case OPC2_32_RC_XNOR: 5500 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5501 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]); 5502 break; 5503 case OPC2_32_RC_XOR: 5504 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5505 break; 5506 default: 5507 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5508 } 5509 tcg_temp_free(temp); 5510 } 5511 5512 static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx) 5513 { 5514 uint32_t op2; 5515 int r1, r2; 5516 int16_t const9; 5517 5518 TCGv temp; 5519 5520 r2 = MASK_OP_RC_D(ctx->opcode); 5521 r1 = MASK_OP_RC_S1(ctx->opcode); 5522 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5523 5524 op2 = MASK_OP_RC_OP2(ctx->opcode); 5525 5526 temp = tcg_temp_new(); 5527 5528 switch (op2) { 5529 case OPC2_32_RC_ABSDIF: 5530 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5531 break; 5532 case OPC2_32_RC_ABSDIFS: 5533 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5534 break; 5535 case OPC2_32_RC_ADD: 5536 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5537 break; 5538 case OPC2_32_RC_ADDC: 5539 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5540 break; 5541 case OPC2_32_RC_ADDS: 5542 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5543 break; 5544 case OPC2_32_RC_ADDS_U: 5545 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5546 break; 5547 case OPC2_32_RC_ADDX: 5548 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5549 break; 5550 case OPC2_32_RC_AND_EQ: 5551 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5552 const9, &tcg_gen_and_tl); 5553 break; 5554 case OPC2_32_RC_AND_GE: 5555 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5556 const9, &tcg_gen_and_tl); 5557 break; 5558 case OPC2_32_RC_AND_GE_U: 5559 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5560 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5561 const9, &tcg_gen_and_tl); 5562 break; 5563 case OPC2_32_RC_AND_LT: 5564 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5565 const9, &tcg_gen_and_tl); 5566 break; 5567 case OPC2_32_RC_AND_LT_U: 5568 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5569 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5570 const9, &tcg_gen_and_tl); 5571 break; 5572 case OPC2_32_RC_AND_NE: 5573 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5574 const9, &tcg_gen_and_tl); 5575 break; 5576 case OPC2_32_RC_EQ: 5577 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5578 break; 5579 case OPC2_32_RC_EQANY_B: 5580 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5581 break; 5582 case OPC2_32_RC_EQANY_H: 5583 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5584 break; 5585 case OPC2_32_RC_GE: 5586 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5587 break; 5588 case OPC2_32_RC_GE_U: 5589 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5590 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5591 break; 5592 case OPC2_32_RC_LT: 5593 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5594 break; 5595 case OPC2_32_RC_LT_U: 5596 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5597 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5598 break; 5599 case OPC2_32_RC_MAX: 5600 tcg_gen_movi_tl(temp, const9); 5601 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5602 cpu_gpr_d[r1], temp); 5603 break; 5604 case OPC2_32_RC_MAX_U: 5605 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5606 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5607 cpu_gpr_d[r1], temp); 5608 break; 5609 case OPC2_32_RC_MIN: 5610 tcg_gen_movi_tl(temp, const9); 5611 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5612 cpu_gpr_d[r1], temp); 5613 break; 5614 case OPC2_32_RC_MIN_U: 5615 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode)); 5616 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp, 5617 cpu_gpr_d[r1], temp); 5618 break; 5619 case OPC2_32_RC_NE: 5620 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5621 break; 5622 case OPC2_32_RC_OR_EQ: 5623 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5624 const9, &tcg_gen_or_tl); 5625 break; 5626 case OPC2_32_RC_OR_GE: 5627 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5628 const9, &tcg_gen_or_tl); 5629 break; 5630 case OPC2_32_RC_OR_GE_U: 5631 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5632 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5633 const9, &tcg_gen_or_tl); 5634 break; 5635 case OPC2_32_RC_OR_LT: 5636 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5637 const9, &tcg_gen_or_tl); 5638 break; 5639 case OPC2_32_RC_OR_LT_U: 5640 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5641 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5642 const9, &tcg_gen_or_tl); 5643 break; 5644 case OPC2_32_RC_OR_NE: 5645 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5646 const9, &tcg_gen_or_tl); 5647 break; 5648 case OPC2_32_RC_RSUB: 5649 tcg_gen_movi_tl(temp, const9); 5650 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5651 break; 5652 case OPC2_32_RC_RSUBS: 5653 tcg_gen_movi_tl(temp, const9); 5654 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5655 break; 5656 case OPC2_32_RC_RSUBS_U: 5657 tcg_gen_movi_tl(temp, const9); 5658 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]); 5659 break; 5660 case OPC2_32_RC_SH_EQ: 5661 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5662 break; 5663 case OPC2_32_RC_SH_GE: 5664 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5665 break; 5666 case OPC2_32_RC_SH_GE_U: 5667 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5668 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5669 break; 5670 case OPC2_32_RC_SH_LT: 5671 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5672 break; 5673 case OPC2_32_RC_SH_LT_U: 5674 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5675 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5676 break; 5677 case OPC2_32_RC_SH_NE: 5678 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5679 break; 5680 case OPC2_32_RC_XOR_EQ: 5681 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], 5682 const9, &tcg_gen_xor_tl); 5683 break; 5684 case OPC2_32_RC_XOR_GE: 5685 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5686 const9, &tcg_gen_xor_tl); 5687 break; 5688 case OPC2_32_RC_XOR_GE_U: 5689 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5690 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5691 const9, &tcg_gen_xor_tl); 5692 break; 5693 case OPC2_32_RC_XOR_LT: 5694 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], 5695 const9, &tcg_gen_xor_tl); 5696 break; 5697 case OPC2_32_RC_XOR_LT_U: 5698 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5699 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], 5700 const9, &tcg_gen_xor_tl); 5701 break; 5702 case OPC2_32_RC_XOR_NE: 5703 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], 5704 const9, &tcg_gen_xor_tl); 5705 break; 5706 default: 5707 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5708 } 5709 tcg_temp_free(temp); 5710 } 5711 5712 static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx) 5713 { 5714 uint32_t op2; 5715 uint32_t const9; 5716 5717 op2 = MASK_OP_RC_OP2(ctx->opcode); 5718 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5719 5720 switch (op2) { 5721 case OPC2_32_RC_BISR: 5722 gen_helper_1arg(bisr, const9); 5723 break; 5724 case OPC2_32_RC_SYSCALL: 5725 /* TODO: Add exception generation */ 5726 break; 5727 default: 5728 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5729 } 5730 } 5731 5732 static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx) 5733 { 5734 uint32_t op2; 5735 int r1, r2; 5736 int16_t const9; 5737 5738 r2 = MASK_OP_RC_D(ctx->opcode); 5739 r1 = MASK_OP_RC_S1(ctx->opcode); 5740 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode); 5741 5742 op2 = MASK_OP_RC_OP2(ctx->opcode); 5743 5744 switch (op2) { 5745 case OPC2_32_RC_MUL_32: 5746 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5747 break; 5748 case OPC2_32_RC_MUL_64: 5749 CHECK_REG_PAIR(r2); 5750 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5751 break; 5752 case OPC2_32_RC_MULS_32: 5753 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5754 break; 5755 case OPC2_32_RC_MUL_U_64: 5756 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5757 CHECK_REG_PAIR(r2); 5758 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9); 5759 break; 5760 case OPC2_32_RC_MULS_U_32: 5761 const9 = MASK_OP_RC_CONST9(ctx->opcode); 5762 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9); 5763 break; 5764 default: 5765 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5766 } 5767 } 5768 5769 /* RCPW format */ 5770 static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx) 5771 { 5772 uint32_t op2; 5773 int r1, r2; 5774 int32_t pos, width, const4; 5775 5776 TCGv temp; 5777 5778 op2 = MASK_OP_RCPW_OP2(ctx->opcode); 5779 r1 = MASK_OP_RCPW_S1(ctx->opcode); 5780 r2 = MASK_OP_RCPW_D(ctx->opcode); 5781 const4 = MASK_OP_RCPW_CONST4(ctx->opcode); 5782 width = MASK_OP_RCPW_WIDTH(ctx->opcode); 5783 pos = MASK_OP_RCPW_POS(ctx->opcode); 5784 5785 switch (op2) { 5786 case OPC2_32_RCPW_IMASK: 5787 CHECK_REG_PAIR(r2); 5788 /* if pos + width > 31 undefined result */ 5789 if (pos + width <= 31) { 5790 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos); 5791 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos)); 5792 } 5793 break; 5794 case OPC2_32_RCPW_INSERT: 5795 /* if pos + width > 32 undefined result */ 5796 if (pos + width <= 32) { 5797 temp = tcg_const_i32(const4); 5798 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width); 5799 tcg_temp_free(temp); 5800 } 5801 break; 5802 default: 5803 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5804 } 5805 } 5806 5807 /* RCRW format */ 5808 5809 static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx) 5810 { 5811 uint32_t op2; 5812 int r1, r3, r4; 5813 int32_t width, const4; 5814 5815 TCGv temp, temp2, temp3; 5816 5817 op2 = MASK_OP_RCRW_OP2(ctx->opcode); 5818 r1 = MASK_OP_RCRW_S1(ctx->opcode); 5819 r3 = MASK_OP_RCRW_S3(ctx->opcode); 5820 r4 = MASK_OP_RCRW_D(ctx->opcode); 5821 width = MASK_OP_RCRW_WIDTH(ctx->opcode); 5822 const4 = MASK_OP_RCRW_CONST4(ctx->opcode); 5823 5824 temp = tcg_temp_new(); 5825 temp2 = tcg_temp_new(); 5826 5827 switch (op2) { 5828 case OPC2_32_RCRW_IMASK: 5829 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f); 5830 tcg_gen_movi_tl(temp2, (1 << width) - 1); 5831 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp); 5832 tcg_gen_movi_tl(temp2, const4); 5833 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp); 5834 break; 5835 case OPC2_32_RCRW_INSERT: 5836 temp3 = tcg_temp_new(); 5837 5838 tcg_gen_movi_tl(temp, width); 5839 tcg_gen_movi_tl(temp2, const4); 5840 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f); 5841 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3); 5842 5843 tcg_temp_free(temp3); 5844 break; 5845 default: 5846 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5847 } 5848 tcg_temp_free(temp); 5849 tcg_temp_free(temp2); 5850 } 5851 5852 /* RCR format */ 5853 5854 static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx) 5855 { 5856 uint32_t op2; 5857 int r1, r3, r4; 5858 int32_t const9; 5859 5860 TCGv temp, temp2; 5861 5862 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5863 r1 = MASK_OP_RCR_S1(ctx->opcode); 5864 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5865 r3 = MASK_OP_RCR_S3(ctx->opcode); 5866 r4 = MASK_OP_RCR_D(ctx->opcode); 5867 5868 switch (op2) { 5869 case OPC2_32_RCR_CADD: 5870 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5871 cpu_gpr_d[r3]); 5872 break; 5873 case OPC2_32_RCR_CADDN: 5874 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r4], 5875 cpu_gpr_d[r3]); 5876 break; 5877 case OPC2_32_RCR_SEL: 5878 temp = tcg_const_i32(0); 5879 temp2 = tcg_const_i32(const9); 5880 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5881 cpu_gpr_d[r1], temp2); 5882 tcg_temp_free(temp); 5883 tcg_temp_free(temp2); 5884 break; 5885 case OPC2_32_RCR_SELN: 5886 temp = tcg_const_i32(0); 5887 temp2 = tcg_const_i32(const9); 5888 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 5889 cpu_gpr_d[r1], temp2); 5890 tcg_temp_free(temp); 5891 tcg_temp_free(temp2); 5892 break; 5893 default: 5894 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5895 } 5896 } 5897 5898 static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx) 5899 { 5900 uint32_t op2; 5901 int r1, r3, r4; 5902 int32_t const9; 5903 5904 5905 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5906 r1 = MASK_OP_RCR_S1(ctx->opcode); 5907 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5908 r3 = MASK_OP_RCR_S3(ctx->opcode); 5909 r4 = MASK_OP_RCR_D(ctx->opcode); 5910 5911 switch (op2) { 5912 case OPC2_32_RCR_MADD_32: 5913 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5914 break; 5915 case OPC2_32_RCR_MADD_64: 5916 CHECK_REG_PAIR(r4); 5917 CHECK_REG_PAIR(r3); 5918 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5919 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5920 break; 5921 case OPC2_32_RCR_MADDS_32: 5922 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5923 break; 5924 case OPC2_32_RCR_MADDS_64: 5925 CHECK_REG_PAIR(r4); 5926 CHECK_REG_PAIR(r3); 5927 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5928 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5929 break; 5930 case OPC2_32_RCR_MADD_U_64: 5931 CHECK_REG_PAIR(r4); 5932 CHECK_REG_PAIR(r3); 5933 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5934 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5935 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5936 break; 5937 case OPC2_32_RCR_MADDS_U_32: 5938 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5939 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5940 break; 5941 case OPC2_32_RCR_MADDS_U_64: 5942 CHECK_REG_PAIR(r4); 5943 CHECK_REG_PAIR(r3); 5944 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5945 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5946 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5947 break; 5948 default: 5949 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 5950 } 5951 } 5952 5953 static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx) 5954 { 5955 uint32_t op2; 5956 int r1, r3, r4; 5957 int32_t const9; 5958 5959 5960 op2 = MASK_OP_RCR_OP2(ctx->opcode); 5961 r1 = MASK_OP_RCR_S1(ctx->opcode); 5962 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode); 5963 r3 = MASK_OP_RCR_S3(ctx->opcode); 5964 r4 = MASK_OP_RCR_D(ctx->opcode); 5965 5966 switch (op2) { 5967 case OPC2_32_RCR_MSUB_32: 5968 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5969 break; 5970 case OPC2_32_RCR_MSUB_64: 5971 CHECK_REG_PAIR(r4); 5972 CHECK_REG_PAIR(r3); 5973 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5974 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5975 break; 5976 case OPC2_32_RCR_MSUBS_32: 5977 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5978 break; 5979 case OPC2_32_RCR_MSUBS_64: 5980 CHECK_REG_PAIR(r4); 5981 CHECK_REG_PAIR(r3); 5982 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5983 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5984 break; 5985 case OPC2_32_RCR_MSUB_U_64: 5986 CHECK_REG_PAIR(r4); 5987 CHECK_REG_PAIR(r3); 5988 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5989 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 5990 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 5991 break; 5992 case OPC2_32_RCR_MSUBS_U_32: 5993 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 5994 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); 5995 break; 5996 case OPC2_32_RCR_MSUBS_U_64: 5997 CHECK_REG_PAIR(r4); 5998 CHECK_REG_PAIR(r3); 5999 const9 = MASK_OP_RCR_CONST9(ctx->opcode); 6000 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 6001 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9); 6002 break; 6003 default: 6004 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6005 } 6006 } 6007 6008 /* RLC format */ 6009 6010 static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, 6011 uint32_t op1) 6012 { 6013 int32_t const16; 6014 int r1, r2; 6015 6016 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode); 6017 r1 = MASK_OP_RLC_S1(ctx->opcode); 6018 r2 = MASK_OP_RLC_D(ctx->opcode); 6019 6020 switch (op1) { 6021 case OPC1_32_RLC_ADDI: 6022 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16); 6023 break; 6024 case OPC1_32_RLC_ADDIH: 6025 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16); 6026 break; 6027 case OPC1_32_RLC_ADDIH_A: 6028 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16); 6029 break; 6030 case OPC1_32_RLC_MFCR: 6031 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 6032 gen_mfcr(env, cpu_gpr_d[r2], const16); 6033 break; 6034 case OPC1_32_RLC_MOV: 6035 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 6036 break; 6037 case OPC1_32_RLC_MOV_64: 6038 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6039 CHECK_REG_PAIR(r2); 6040 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 6041 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); 6042 } else { 6043 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6044 } 6045 break; 6046 case OPC1_32_RLC_MOV_U: 6047 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 6048 tcg_gen_movi_tl(cpu_gpr_d[r2], const16); 6049 break; 6050 case OPC1_32_RLC_MOV_H: 6051 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16); 6052 break; 6053 case OPC1_32_RLC_MOVH_A: 6054 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16); 6055 break; 6056 case OPC1_32_RLC_MTCR: 6057 const16 = MASK_OP_RLC_CONST16(ctx->opcode); 6058 gen_mtcr(env, ctx, cpu_gpr_d[r1], const16); 6059 break; 6060 default: 6061 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6062 } 6063 } 6064 6065 /* RR format */ 6066 static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) 6067 { 6068 uint32_t op2; 6069 int r3, r2, r1; 6070 6071 TCGv temp; 6072 6073 r3 = MASK_OP_RR_D(ctx->opcode); 6074 r2 = MASK_OP_RR_S2(ctx->opcode); 6075 r1 = MASK_OP_RR_S1(ctx->opcode); 6076 op2 = MASK_OP_RR_OP2(ctx->opcode); 6077 6078 switch (op2) { 6079 case OPC2_32_RR_ABS: 6080 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]); 6081 break; 6082 case OPC2_32_RR_ABS_B: 6083 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6084 break; 6085 case OPC2_32_RR_ABS_H: 6086 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6087 break; 6088 case OPC2_32_RR_ABSDIF: 6089 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6090 break; 6091 case OPC2_32_RR_ABSDIF_B: 6092 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6093 cpu_gpr_d[r2]); 6094 break; 6095 case OPC2_32_RR_ABSDIF_H: 6096 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6097 cpu_gpr_d[r2]); 6098 break; 6099 case OPC2_32_RR_ABSDIFS: 6100 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6101 cpu_gpr_d[r2]); 6102 break; 6103 case OPC2_32_RR_ABSDIFS_H: 6104 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6105 cpu_gpr_d[r2]); 6106 break; 6107 case OPC2_32_RR_ABSS: 6108 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6109 break; 6110 case OPC2_32_RR_ABSS_H: 6111 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]); 6112 break; 6113 case OPC2_32_RR_ADD: 6114 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6115 break; 6116 case OPC2_32_RR_ADD_B: 6117 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6118 break; 6119 case OPC2_32_RR_ADD_H: 6120 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6121 break; 6122 case OPC2_32_RR_ADDC: 6123 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6124 break; 6125 case OPC2_32_RR_ADDS: 6126 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6127 break; 6128 case OPC2_32_RR_ADDS_H: 6129 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6130 cpu_gpr_d[r2]); 6131 break; 6132 case OPC2_32_RR_ADDS_HU: 6133 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6134 cpu_gpr_d[r2]); 6135 break; 6136 case OPC2_32_RR_ADDS_U: 6137 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6138 cpu_gpr_d[r2]); 6139 break; 6140 case OPC2_32_RR_ADDX: 6141 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6142 break; 6143 case OPC2_32_RR_AND_EQ: 6144 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6145 cpu_gpr_d[r2], &tcg_gen_and_tl); 6146 break; 6147 case OPC2_32_RR_AND_GE: 6148 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6149 cpu_gpr_d[r2], &tcg_gen_and_tl); 6150 break; 6151 case OPC2_32_RR_AND_GE_U: 6152 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6153 cpu_gpr_d[r2], &tcg_gen_and_tl); 6154 break; 6155 case OPC2_32_RR_AND_LT: 6156 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6157 cpu_gpr_d[r2], &tcg_gen_and_tl); 6158 break; 6159 case OPC2_32_RR_AND_LT_U: 6160 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6161 cpu_gpr_d[r2], &tcg_gen_and_tl); 6162 break; 6163 case OPC2_32_RR_AND_NE: 6164 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6165 cpu_gpr_d[r2], &tcg_gen_and_tl); 6166 break; 6167 case OPC2_32_RR_EQ: 6168 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6169 cpu_gpr_d[r2]); 6170 break; 6171 case OPC2_32_RR_EQ_B: 6172 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6173 break; 6174 case OPC2_32_RR_EQ_H: 6175 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6176 break; 6177 case OPC2_32_RR_EQ_W: 6178 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6179 break; 6180 case OPC2_32_RR_EQANY_B: 6181 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6182 break; 6183 case OPC2_32_RR_EQANY_H: 6184 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6185 break; 6186 case OPC2_32_RR_GE: 6187 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6188 cpu_gpr_d[r2]); 6189 break; 6190 case OPC2_32_RR_GE_U: 6191 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6192 cpu_gpr_d[r2]); 6193 break; 6194 case OPC2_32_RR_LT: 6195 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6196 cpu_gpr_d[r2]); 6197 break; 6198 case OPC2_32_RR_LT_U: 6199 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6200 cpu_gpr_d[r2]); 6201 break; 6202 case OPC2_32_RR_LT_B: 6203 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6204 break; 6205 case OPC2_32_RR_LT_BU: 6206 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6207 break; 6208 case OPC2_32_RR_LT_H: 6209 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6210 break; 6211 case OPC2_32_RR_LT_HU: 6212 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6213 break; 6214 case OPC2_32_RR_LT_W: 6215 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6216 break; 6217 case OPC2_32_RR_LT_WU: 6218 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6219 break; 6220 case OPC2_32_RR_MAX: 6221 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6222 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6223 break; 6224 case OPC2_32_RR_MAX_U: 6225 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6226 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6227 break; 6228 case OPC2_32_RR_MAX_B: 6229 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6230 break; 6231 case OPC2_32_RR_MAX_BU: 6232 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6233 break; 6234 case OPC2_32_RR_MAX_H: 6235 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6236 break; 6237 case OPC2_32_RR_MAX_HU: 6238 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6239 break; 6240 case OPC2_32_RR_MIN: 6241 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6242 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6243 break; 6244 case OPC2_32_RR_MIN_U: 6245 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6246 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6247 break; 6248 case OPC2_32_RR_MIN_B: 6249 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6250 break; 6251 case OPC2_32_RR_MIN_BU: 6252 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6253 break; 6254 case OPC2_32_RR_MIN_H: 6255 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6256 break; 6257 case OPC2_32_RR_MIN_HU: 6258 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6259 break; 6260 case OPC2_32_RR_MOV: 6261 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 6262 break; 6263 case OPC2_32_RR_MOV_64: 6264 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6265 temp = tcg_temp_new(); 6266 6267 CHECK_REG_PAIR(r3); 6268 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); 6269 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 6270 tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); 6271 6272 tcg_temp_free(temp); 6273 } else { 6274 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6275 } 6276 break; 6277 case OPC2_32_RR_MOVS_64: 6278 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6279 CHECK_REG_PAIR(r3); 6280 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); 6281 tcg_gen_sari_tl(cpu_gpr_d[r3 + 1], cpu_gpr_d[r2], 31); 6282 } else { 6283 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6284 } 6285 break; 6286 case OPC2_32_RR_NE: 6287 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6288 cpu_gpr_d[r2]); 6289 break; 6290 case OPC2_32_RR_OR_EQ: 6291 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6292 cpu_gpr_d[r2], &tcg_gen_or_tl); 6293 break; 6294 case OPC2_32_RR_OR_GE: 6295 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6296 cpu_gpr_d[r2], &tcg_gen_or_tl); 6297 break; 6298 case OPC2_32_RR_OR_GE_U: 6299 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6300 cpu_gpr_d[r2], &tcg_gen_or_tl); 6301 break; 6302 case OPC2_32_RR_OR_LT: 6303 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6304 cpu_gpr_d[r2], &tcg_gen_or_tl); 6305 break; 6306 case OPC2_32_RR_OR_LT_U: 6307 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6308 cpu_gpr_d[r2], &tcg_gen_or_tl); 6309 break; 6310 case OPC2_32_RR_OR_NE: 6311 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6312 cpu_gpr_d[r2], &tcg_gen_or_tl); 6313 break; 6314 case OPC2_32_RR_SAT_B: 6315 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80); 6316 break; 6317 case OPC2_32_RR_SAT_BU: 6318 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff); 6319 break; 6320 case OPC2_32_RR_SAT_H: 6321 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000); 6322 break; 6323 case OPC2_32_RR_SAT_HU: 6324 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff); 6325 break; 6326 case OPC2_32_RR_SH_EQ: 6327 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6328 cpu_gpr_d[r2]); 6329 break; 6330 case OPC2_32_RR_SH_GE: 6331 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6332 cpu_gpr_d[r2]); 6333 break; 6334 case OPC2_32_RR_SH_GE_U: 6335 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6336 cpu_gpr_d[r2]); 6337 break; 6338 case OPC2_32_RR_SH_LT: 6339 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6340 cpu_gpr_d[r2]); 6341 break; 6342 case OPC2_32_RR_SH_LT_U: 6343 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6344 cpu_gpr_d[r2]); 6345 break; 6346 case OPC2_32_RR_SH_NE: 6347 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6348 cpu_gpr_d[r2]); 6349 break; 6350 case OPC2_32_RR_SUB: 6351 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6352 break; 6353 case OPC2_32_RR_SUB_B: 6354 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6355 break; 6356 case OPC2_32_RR_SUB_H: 6357 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6358 break; 6359 case OPC2_32_RR_SUBC: 6360 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6361 break; 6362 case OPC2_32_RR_SUBS: 6363 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6364 break; 6365 case OPC2_32_RR_SUBS_U: 6366 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6367 break; 6368 case OPC2_32_RR_SUBS_H: 6369 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6370 cpu_gpr_d[r2]); 6371 break; 6372 case OPC2_32_RR_SUBS_HU: 6373 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6374 cpu_gpr_d[r2]); 6375 break; 6376 case OPC2_32_RR_SUBX: 6377 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6378 break; 6379 case OPC2_32_RR_XOR_EQ: 6380 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], 6381 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6382 break; 6383 case OPC2_32_RR_XOR_GE: 6384 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6385 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6386 break; 6387 case OPC2_32_RR_XOR_GE_U: 6388 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6389 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6390 break; 6391 case OPC2_32_RR_XOR_LT: 6392 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], 6393 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6394 break; 6395 case OPC2_32_RR_XOR_LT_U: 6396 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], 6397 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6398 break; 6399 case OPC2_32_RR_XOR_NE: 6400 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], 6401 cpu_gpr_d[r2], &tcg_gen_xor_tl); 6402 break; 6403 default: 6404 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6405 } 6406 } 6407 6408 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) 6409 { 6410 uint32_t op2; 6411 int r3, r2, r1; 6412 TCGv temp; 6413 6414 r3 = MASK_OP_RR_D(ctx->opcode); 6415 r2 = MASK_OP_RR_S2(ctx->opcode); 6416 r1 = MASK_OP_RR_S1(ctx->opcode); 6417 6418 temp = tcg_temp_new(); 6419 op2 = MASK_OP_RR_OP2(ctx->opcode); 6420 6421 switch (op2) { 6422 case OPC2_32_RR_AND: 6423 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6424 break; 6425 case OPC2_32_RR_ANDN: 6426 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6427 break; 6428 case OPC2_32_RR_CLO: 6429 tcg_gen_not_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6430 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], TARGET_LONG_BITS); 6431 break; 6432 case OPC2_32_RR_CLO_H: 6433 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6434 break; 6435 case OPC2_32_RR_CLS: 6436 tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6437 break; 6438 case OPC2_32_RR_CLS_H: 6439 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6440 break; 6441 case OPC2_32_RR_CLZ: 6442 tcg_gen_clzi_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], TARGET_LONG_BITS); 6443 break; 6444 case OPC2_32_RR_CLZ_H: 6445 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6446 break; 6447 case OPC2_32_RR_NAND: 6448 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6449 break; 6450 case OPC2_32_RR_NOR: 6451 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6452 break; 6453 case OPC2_32_RR_OR: 6454 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6455 break; 6456 case OPC2_32_RR_ORN: 6457 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6458 break; 6459 case OPC2_32_RR_SH: 6460 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6461 break; 6462 case OPC2_32_RR_SH_H: 6463 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6464 break; 6465 case OPC2_32_RR_SHA: 6466 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6467 break; 6468 case OPC2_32_RR_SHA_H: 6469 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6470 break; 6471 case OPC2_32_RR_SHAS: 6472 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6473 break; 6474 case OPC2_32_RR_XNOR: 6475 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6476 break; 6477 case OPC2_32_RR_XOR: 6478 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6479 break; 6480 default: 6481 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6482 } 6483 tcg_temp_free(temp); 6484 } 6485 6486 static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx) 6487 { 6488 uint32_t op2, n; 6489 int r1, r2, r3; 6490 TCGv temp; 6491 6492 op2 = MASK_OP_RR_OP2(ctx->opcode); 6493 r3 = MASK_OP_RR_D(ctx->opcode); 6494 r2 = MASK_OP_RR_S2(ctx->opcode); 6495 r1 = MASK_OP_RR_S1(ctx->opcode); 6496 n = MASK_OP_RR_N(ctx->opcode); 6497 6498 switch (op2) { 6499 case OPC2_32_RR_ADD_A: 6500 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6501 break; 6502 case OPC2_32_RR_ADDSC_A: 6503 temp = tcg_temp_new(); 6504 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n); 6505 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp); 6506 tcg_temp_free(temp); 6507 break; 6508 case OPC2_32_RR_ADDSC_AT: 6509 temp = tcg_temp_new(); 6510 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3); 6511 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp); 6512 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC); 6513 tcg_temp_free(temp); 6514 break; 6515 case OPC2_32_RR_EQ_A: 6516 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 6517 cpu_gpr_a[r2]); 6518 break; 6519 case OPC2_32_RR_EQZ: 6520 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6521 break; 6522 case OPC2_32_RR_GE_A: 6523 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6524 cpu_gpr_a[r2]); 6525 break; 6526 case OPC2_32_RR_LT_A: 6527 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1], 6528 cpu_gpr_a[r2]); 6529 break; 6530 case OPC2_32_RR_MOV_A: 6531 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]); 6532 break; 6533 case OPC2_32_RR_MOV_AA: 6534 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]); 6535 break; 6536 case OPC2_32_RR_MOV_D: 6537 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]); 6538 break; 6539 case OPC2_32_RR_NE_A: 6540 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 6541 cpu_gpr_a[r2]); 6542 break; 6543 case OPC2_32_RR_NEZ_A: 6544 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0); 6545 break; 6546 case OPC2_32_RR_SUB_A: 6547 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]); 6548 break; 6549 default: 6550 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6551 } 6552 } 6553 6554 static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx) 6555 { 6556 uint32_t op2; 6557 int r1; 6558 6559 op2 = MASK_OP_RR_OP2(ctx->opcode); 6560 r1 = MASK_OP_RR_S1(ctx->opcode); 6561 6562 switch (op2) { 6563 case OPC2_32_RR_JI: 6564 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6565 break; 6566 case OPC2_32_RR_JLI: 6567 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc); 6568 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6569 break; 6570 case OPC2_32_RR_CALLI: 6571 gen_helper_1arg(call, ctx->next_pc); 6572 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6573 break; 6574 case OPC2_32_RR_FCALLI: 6575 gen_fcall_save_ctx(ctx); 6576 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1); 6577 break; 6578 default: 6579 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6580 } 6581 tcg_gen_exit_tb(NULL, 0); 6582 ctx->bstate = BS_BRANCH; 6583 } 6584 6585 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) 6586 { 6587 uint32_t op2; 6588 int r1, r2, r3; 6589 6590 TCGv temp, temp2, temp3; 6591 6592 op2 = MASK_OP_RR_OP2(ctx->opcode); 6593 r3 = MASK_OP_RR_D(ctx->opcode); 6594 r2 = MASK_OP_RR_S2(ctx->opcode); 6595 r1 = MASK_OP_RR_S1(ctx->opcode); 6596 6597 switch (op2) { 6598 case OPC2_32_RR_BMERGE: 6599 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6600 break; 6601 case OPC2_32_RR_BSPLIT: 6602 CHECK_REG_PAIR(r3); 6603 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6604 break; 6605 case OPC2_32_RR_DVINIT_B: 6606 CHECK_REG_PAIR(r3); 6607 gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6608 cpu_gpr_d[r2]); 6609 break; 6610 case OPC2_32_RR_DVINIT_BU: 6611 temp = tcg_temp_new(); 6612 temp2 = tcg_temp_new(); 6613 temp3 = tcg_temp_new(); 6614 CHECK_REG_PAIR(r3); 6615 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8); 6616 /* reset av */ 6617 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6618 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 6619 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6620 tcg_gen_neg_tl(temp, temp3); 6621 /* use cpu_PSW_AV to compare against 0 */ 6622 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV, 6623 temp, temp3); 6624 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); 6625 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV, 6626 temp2, cpu_gpr_d[r2]); 6627 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6628 } else { 6629 /* overflow = (D[b] == 0) */ 6630 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6631 } 6632 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6633 /* sv */ 6634 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6635 /* write result */ 6636 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24); 6637 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6638 6639 tcg_temp_free(temp); 6640 tcg_temp_free(temp2); 6641 tcg_temp_free(temp3); 6642 break; 6643 case OPC2_32_RR_DVINIT_H: 6644 CHECK_REG_PAIR(r3); 6645 gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6646 cpu_gpr_d[r2]); 6647 break; 6648 case OPC2_32_RR_DVINIT_HU: 6649 temp = tcg_temp_new(); 6650 temp2 = tcg_temp_new(); 6651 temp3 = tcg_temp_new(); 6652 CHECK_REG_PAIR(r3); 6653 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16); 6654 /* reset av */ 6655 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6656 if (!tricore_feature(env, TRICORE_FEATURE_131)) { 6657 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */ 6658 tcg_gen_neg_tl(temp, temp3); 6659 /* use cpu_PSW_AV to compare against 0 */ 6660 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV, 6661 temp, temp3); 6662 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]); 6663 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV, 6664 temp2, cpu_gpr_d[r2]); 6665 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2); 6666 } else { 6667 /* overflow = (D[b] == 0) */ 6668 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6669 } 6670 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6671 /* sv */ 6672 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6673 /* write result */ 6674 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); 6675 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); 6676 tcg_temp_free(temp); 6677 tcg_temp_free(temp2); 6678 tcg_temp_free(temp3); 6679 break; 6680 case OPC2_32_RR_DVINIT: 6681 temp = tcg_temp_new(); 6682 temp2 = tcg_temp_new(); 6683 CHECK_REG_PAIR(r3); 6684 /* overflow = ((D[b] == 0) || 6685 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */ 6686 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff); 6687 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000); 6688 tcg_gen_and_tl(temp, temp, temp2); 6689 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0); 6690 tcg_gen_or_tl(cpu_PSW_V, temp, temp2); 6691 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6692 /* sv */ 6693 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6694 /* reset av */ 6695 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6696 /* write result */ 6697 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6698 /* sign extend to high reg */ 6699 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31); 6700 tcg_temp_free(temp); 6701 tcg_temp_free(temp2); 6702 break; 6703 case OPC2_32_RR_DVINIT_U: 6704 /* overflow = (D[b] == 0) */ 6705 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0); 6706 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); 6707 /* sv */ 6708 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); 6709 /* reset av */ 6710 tcg_gen_movi_tl(cpu_PSW_AV, 0); 6711 /* write result */ 6712 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6713 /* zero extend to high reg*/ 6714 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0); 6715 break; 6716 case OPC2_32_RR_PARITY: 6717 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]); 6718 break; 6719 case OPC2_32_RR_UNPACK: 6720 CHECK_REG_PAIR(r3); 6721 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 6722 break; 6723 case OPC2_32_RR_CRC32: 6724 if (tricore_feature(env, TRICORE_FEATURE_161)) { 6725 gen_helper_crc32(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6726 } else { 6727 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6728 } 6729 break; 6730 case OPC2_32_RR_DIV: 6731 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6732 GEN_HELPER_RR(divide, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6733 cpu_gpr_d[r2]); 6734 } else { 6735 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6736 } 6737 break; 6738 case OPC2_32_RR_DIV_U: 6739 if (tricore_feature(env, TRICORE_FEATURE_16)) { 6740 GEN_HELPER_RR(divide_u, cpu_gpr_d[r3], cpu_gpr_d[r3+1], 6741 cpu_gpr_d[r1], cpu_gpr_d[r2]); 6742 } else { 6743 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6744 } 6745 break; 6746 case OPC2_32_RR_MUL_F: 6747 gen_helper_fmul(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6748 break; 6749 case OPC2_32_RR_DIV_F: 6750 gen_helper_fdiv(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6751 break; 6752 case OPC2_32_RR_CMP_F: 6753 gen_helper_fcmp(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]); 6754 break; 6755 case OPC2_32_RR_FTOI: 6756 gen_helper_ftoi(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6757 break; 6758 case OPC2_32_RR_ITOF: 6759 gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6760 break; 6761 case OPC2_32_RR_FTOUZ: 6762 gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); 6763 break; 6764 case OPC2_32_RR_UPDFL: 6765 gen_helper_updfl(cpu_env, cpu_gpr_d[r1]); 6766 break; 6767 default: 6768 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6769 } 6770 } 6771 6772 /* RR1 Format */ 6773 static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx) 6774 { 6775 uint32_t op2; 6776 6777 int r1, r2, r3; 6778 TCGv n; 6779 TCGv_i64 temp64; 6780 6781 r1 = MASK_OP_RR1_S1(ctx->opcode); 6782 r2 = MASK_OP_RR1_S2(ctx->opcode); 6783 r3 = MASK_OP_RR1_D(ctx->opcode); 6784 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode)); 6785 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6786 6787 switch (op2) { 6788 case OPC2_32_RR1_MUL_H_32_LL: 6789 temp64 = tcg_temp_new_i64(); 6790 CHECK_REG_PAIR(r3); 6791 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6792 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6793 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6794 tcg_temp_free_i64(temp64); 6795 break; 6796 case OPC2_32_RR1_MUL_H_32_LU: 6797 temp64 = tcg_temp_new_i64(); 6798 CHECK_REG_PAIR(r3); 6799 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6800 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6801 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6802 tcg_temp_free_i64(temp64); 6803 break; 6804 case OPC2_32_RR1_MUL_H_32_UL: 6805 temp64 = tcg_temp_new_i64(); 6806 CHECK_REG_PAIR(r3); 6807 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6808 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6809 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6810 tcg_temp_free_i64(temp64); 6811 break; 6812 case OPC2_32_RR1_MUL_H_32_UU: 6813 temp64 = tcg_temp_new_i64(); 6814 CHECK_REG_PAIR(r3); 6815 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6816 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6817 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]); 6818 tcg_temp_free_i64(temp64); 6819 break; 6820 case OPC2_32_RR1_MULM_H_64_LL: 6821 temp64 = tcg_temp_new_i64(); 6822 CHECK_REG_PAIR(r3); 6823 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6824 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6825 /* reset V bit */ 6826 tcg_gen_movi_tl(cpu_PSW_V, 0); 6827 /* reset AV bit */ 6828 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6829 tcg_temp_free_i64(temp64); 6830 break; 6831 case OPC2_32_RR1_MULM_H_64_LU: 6832 temp64 = tcg_temp_new_i64(); 6833 CHECK_REG_PAIR(r3); 6834 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6835 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6836 /* reset V bit */ 6837 tcg_gen_movi_tl(cpu_PSW_V, 0); 6838 /* reset AV bit */ 6839 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6840 tcg_temp_free_i64(temp64); 6841 break; 6842 case OPC2_32_RR1_MULM_H_64_UL: 6843 temp64 = tcg_temp_new_i64(); 6844 CHECK_REG_PAIR(r3); 6845 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6846 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6847 /* reset V bit */ 6848 tcg_gen_movi_tl(cpu_PSW_V, 0); 6849 /* reset AV bit */ 6850 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6851 tcg_temp_free_i64(temp64); 6852 break; 6853 case OPC2_32_RR1_MULM_H_64_UU: 6854 temp64 = tcg_temp_new_i64(); 6855 CHECK_REG_PAIR(r3); 6856 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6857 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64); 6858 /* reset V bit */ 6859 tcg_gen_movi_tl(cpu_PSW_V, 0); 6860 /* reset AV bit */ 6861 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 6862 tcg_temp_free_i64(temp64); 6863 6864 break; 6865 case OPC2_32_RR1_MULR_H_16_LL: 6866 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6867 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6868 break; 6869 case OPC2_32_RR1_MULR_H_16_LU: 6870 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6871 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6872 break; 6873 case OPC2_32_RR1_MULR_H_16_UL: 6874 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6875 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6876 break; 6877 case OPC2_32_RR1_MULR_H_16_UU: 6878 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n); 6879 gen_calc_usb_mulr_h(cpu_gpr_d[r3]); 6880 break; 6881 default: 6882 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6883 } 6884 tcg_temp_free(n); 6885 } 6886 6887 static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx) 6888 { 6889 uint32_t op2; 6890 int r1, r2, r3; 6891 uint32_t n; 6892 6893 TCGv temp, temp2; 6894 6895 r1 = MASK_OP_RR1_S1(ctx->opcode); 6896 r2 = MASK_OP_RR1_S2(ctx->opcode); 6897 r3 = MASK_OP_RR1_D(ctx->opcode); 6898 n = MASK_OP_RR1_N(ctx->opcode); 6899 op2 = MASK_OP_RR1_OP2(ctx->opcode); 6900 6901 temp = tcg_temp_new(); 6902 temp2 = tcg_temp_new(); 6903 6904 switch (op2) { 6905 case OPC2_32_RR1_MUL_Q_32: 6906 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32); 6907 break; 6908 case OPC2_32_RR1_MUL_Q_64: 6909 CHECK_REG_PAIR(r3); 6910 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 6911 n, 0); 6912 break; 6913 case OPC2_32_RR1_MUL_Q_32_L: 6914 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6915 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6916 break; 6917 case OPC2_32_RR1_MUL_Q_64_L: 6918 CHECK_REG_PAIR(r3); 6919 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 6920 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6921 break; 6922 case OPC2_32_RR1_MUL_Q_32_U: 6923 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6924 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16); 6925 break; 6926 case OPC2_32_RR1_MUL_Q_64_U: 6927 CHECK_REG_PAIR(r3); 6928 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 6929 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0); 6930 break; 6931 case OPC2_32_RR1_MUL_Q_32_LL: 6932 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6933 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6934 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6935 break; 6936 case OPC2_32_RR1_MUL_Q_32_UU: 6937 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6938 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6939 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n); 6940 break; 6941 case OPC2_32_RR1_MULR_Q_32_L: 6942 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 6943 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 6944 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6945 break; 6946 case OPC2_32_RR1_MULR_Q_32_U: 6947 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 6948 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 6949 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n); 6950 break; 6951 default: 6952 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6953 } 6954 tcg_temp_free(temp); 6955 tcg_temp_free(temp2); 6956 } 6957 6958 /* RR2 format */ 6959 static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx) 6960 { 6961 uint32_t op2; 6962 int r1, r2, r3; 6963 6964 op2 = MASK_OP_RR2_OP2(ctx->opcode); 6965 r1 = MASK_OP_RR2_S1(ctx->opcode); 6966 r2 = MASK_OP_RR2_S2(ctx->opcode); 6967 r3 = MASK_OP_RR2_D(ctx->opcode); 6968 switch (op2) { 6969 case OPC2_32_RR2_MUL_32: 6970 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); 6971 break; 6972 case OPC2_32_RR2_MUL_64: 6973 CHECK_REG_PAIR(r3); 6974 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6975 cpu_gpr_d[r2]); 6976 break; 6977 case OPC2_32_RR2_MULS_32: 6978 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6979 cpu_gpr_d[r2]); 6980 break; 6981 case OPC2_32_RR2_MUL_U_64: 6982 CHECK_REG_PAIR(r3); 6983 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], 6984 cpu_gpr_d[r2]); 6985 break; 6986 case OPC2_32_RR2_MULS_U_32: 6987 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], 6988 cpu_gpr_d[r2]); 6989 break; 6990 default: 6991 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 6992 } 6993 } 6994 6995 /* RRPW format */ 6996 static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) 6997 { 6998 uint32_t op2; 6999 int r1, r2, r3; 7000 int32_t pos, width; 7001 7002 op2 = MASK_OP_RRPW_OP2(ctx->opcode); 7003 r1 = MASK_OP_RRPW_S1(ctx->opcode); 7004 r2 = MASK_OP_RRPW_S2(ctx->opcode); 7005 r3 = MASK_OP_RRPW_D(ctx->opcode); 7006 pos = MASK_OP_RRPW_POS(ctx->opcode); 7007 width = MASK_OP_RRPW_WIDTH(ctx->opcode); 7008 7009 switch (op2) { 7010 case OPC2_32_RRPW_EXTR: 7011 if (pos + width <= 31) { 7012 /* optimize special cases */ 7013 if ((pos == 0) && (width == 8)) { 7014 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 7015 } else if ((pos == 0) && (width == 16)) { 7016 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); 7017 } else { 7018 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width); 7019 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width); 7020 } 7021 } 7022 break; 7023 case OPC2_32_RRPW_EXTR_U: 7024 if (width == 0) { 7025 tcg_gen_movi_tl(cpu_gpr_d[r3], 0); 7026 } else { 7027 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos); 7028 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width)); 7029 } 7030 break; 7031 case OPC2_32_RRPW_IMASK: 7032 CHECK_REG_PAIR(r3); 7033 if (pos + width <= 31) { 7034 tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos); 7035 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos); 7036 } 7037 break; 7038 case OPC2_32_RRPW_INSERT: 7039 if (pos + width <= 31) { 7040 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], 7041 width, pos); 7042 } 7043 break; 7044 default: 7045 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7046 } 7047 } 7048 7049 /* RRR format */ 7050 static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx) 7051 { 7052 uint32_t op2; 7053 int r1, r2, r3, r4; 7054 TCGv temp; 7055 7056 op2 = MASK_OP_RRR_OP2(ctx->opcode); 7057 r1 = MASK_OP_RRR_S1(ctx->opcode); 7058 r2 = MASK_OP_RRR_S2(ctx->opcode); 7059 r3 = MASK_OP_RRR_S3(ctx->opcode); 7060 r4 = MASK_OP_RRR_D(ctx->opcode); 7061 7062 switch (op2) { 7063 case OPC2_32_RRR_CADD: 7064 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], 7065 cpu_gpr_d[r4], cpu_gpr_d[r3]); 7066 break; 7067 case OPC2_32_RRR_CADDN: 7068 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 7069 cpu_gpr_d[r3]); 7070 break; 7071 case OPC2_32_RRR_CSUB: 7072 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 7073 cpu_gpr_d[r3]); 7074 break; 7075 case OPC2_32_RRR_CSUBN: 7076 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4], 7077 cpu_gpr_d[r3]); 7078 break; 7079 case OPC2_32_RRR_SEL: 7080 temp = tcg_const_i32(0); 7081 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 7082 cpu_gpr_d[r1], cpu_gpr_d[r2]); 7083 tcg_temp_free(temp); 7084 break; 7085 case OPC2_32_RRR_SELN: 7086 temp = tcg_const_i32(0); 7087 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp, 7088 cpu_gpr_d[r1], cpu_gpr_d[r2]); 7089 tcg_temp_free(temp); 7090 break; 7091 default: 7092 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7093 } 7094 } 7095 7096 static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx) 7097 { 7098 uint32_t op2; 7099 7100 int r1, r2, r3, r4; 7101 7102 op2 = MASK_OP_RRR_OP2(ctx->opcode); 7103 r1 = MASK_OP_RRR_S1(ctx->opcode); 7104 r2 = MASK_OP_RRR_S2(ctx->opcode); 7105 r3 = MASK_OP_RRR_S3(ctx->opcode); 7106 r4 = MASK_OP_RRR_D(ctx->opcode); 7107 7108 switch (op2) { 7109 case OPC2_32_RRR_DVADJ: 7110 CHECK_REG_PAIR(r3); 7111 CHECK_REG_PAIR(r4); 7112 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7113 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7114 break; 7115 case OPC2_32_RRR_DVSTEP: 7116 CHECK_REG_PAIR(r3); 7117 CHECK_REG_PAIR(r4); 7118 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7119 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7120 break; 7121 case OPC2_32_RRR_DVSTEP_U: 7122 CHECK_REG_PAIR(r3); 7123 CHECK_REG_PAIR(r4); 7124 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7125 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7126 break; 7127 case OPC2_32_RRR_IXMAX: 7128 CHECK_REG_PAIR(r3); 7129 CHECK_REG_PAIR(r4); 7130 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7131 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7132 break; 7133 case OPC2_32_RRR_IXMAX_U: 7134 CHECK_REG_PAIR(r3); 7135 CHECK_REG_PAIR(r4); 7136 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7137 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7138 break; 7139 case OPC2_32_RRR_IXMIN: 7140 CHECK_REG_PAIR(r3); 7141 CHECK_REG_PAIR(r4); 7142 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7143 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7144 break; 7145 case OPC2_32_RRR_IXMIN_U: 7146 CHECK_REG_PAIR(r3); 7147 CHECK_REG_PAIR(r4); 7148 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7149 cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7150 break; 7151 case OPC2_32_RRR_PACK: 7152 CHECK_REG_PAIR(r3); 7153 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3], 7154 cpu_gpr_d[r3+1], cpu_gpr_d[r1]); 7155 break; 7156 case OPC2_32_RRR_ADD_F: 7157 gen_helper_fadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 7158 break; 7159 case OPC2_32_RRR_SUB_F: 7160 gen_helper_fsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r3]); 7161 break; 7162 case OPC2_32_RRR_MADD_F: 7163 gen_helper_fmadd(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7164 cpu_gpr_d[r2], cpu_gpr_d[r3]); 7165 break; 7166 case OPC2_32_RRR_MSUB_F: 7167 gen_helper_fmsub(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7168 cpu_gpr_d[r2], cpu_gpr_d[r3]); 7169 break; 7170 default: 7171 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7172 } 7173 } 7174 7175 /* RRR2 format */ 7176 static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx) 7177 { 7178 uint32_t op2; 7179 uint32_t r1, r2, r3, r4; 7180 7181 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 7182 r1 = MASK_OP_RRR2_S1(ctx->opcode); 7183 r2 = MASK_OP_RRR2_S2(ctx->opcode); 7184 r3 = MASK_OP_RRR2_S3(ctx->opcode); 7185 r4 = MASK_OP_RRR2_D(ctx->opcode); 7186 switch (op2) { 7187 case OPC2_32_RRR2_MADD_32: 7188 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 7189 cpu_gpr_d[r2]); 7190 break; 7191 case OPC2_32_RRR2_MADD_64: 7192 CHECK_REG_PAIR(r4); 7193 CHECK_REG_PAIR(r3); 7194 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7195 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7196 break; 7197 case OPC2_32_RRR2_MADDS_32: 7198 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7199 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7200 break; 7201 case OPC2_32_RRR2_MADDS_64: 7202 CHECK_REG_PAIR(r4); 7203 CHECK_REG_PAIR(r3); 7204 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7205 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7206 break; 7207 case OPC2_32_RRR2_MADD_U_64: 7208 CHECK_REG_PAIR(r4); 7209 CHECK_REG_PAIR(r3); 7210 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7211 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7212 break; 7213 case OPC2_32_RRR2_MADDS_U_32: 7214 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7215 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7216 break; 7217 case OPC2_32_RRR2_MADDS_U_64: 7218 CHECK_REG_PAIR(r4); 7219 CHECK_REG_PAIR(r3); 7220 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7221 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7222 break; 7223 default: 7224 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7225 } 7226 } 7227 7228 static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx) 7229 { 7230 uint32_t op2; 7231 uint32_t r1, r2, r3, r4; 7232 7233 op2 = MASK_OP_RRR2_OP2(ctx->opcode); 7234 r1 = MASK_OP_RRR2_S1(ctx->opcode); 7235 r2 = MASK_OP_RRR2_S2(ctx->opcode); 7236 r3 = MASK_OP_RRR2_S3(ctx->opcode); 7237 r4 = MASK_OP_RRR2_D(ctx->opcode); 7238 7239 switch (op2) { 7240 case OPC2_32_RRR2_MSUB_32: 7241 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], 7242 cpu_gpr_d[r2]); 7243 break; 7244 case OPC2_32_RRR2_MSUB_64: 7245 CHECK_REG_PAIR(r4); 7246 CHECK_REG_PAIR(r3); 7247 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7248 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7249 break; 7250 case OPC2_32_RRR2_MSUBS_32: 7251 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7252 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7253 break; 7254 case OPC2_32_RRR2_MSUBS_64: 7255 CHECK_REG_PAIR(r4); 7256 CHECK_REG_PAIR(r3); 7257 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7258 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7259 break; 7260 case OPC2_32_RRR2_MSUB_U_64: 7261 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7262 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7263 break; 7264 case OPC2_32_RRR2_MSUBS_U_32: 7265 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1], 7266 cpu_gpr_d[r3], cpu_gpr_d[r2]); 7267 break; 7268 case OPC2_32_RRR2_MSUBS_U_64: 7269 CHECK_REG_PAIR(r4); 7270 CHECK_REG_PAIR(r3); 7271 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1], 7272 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]); 7273 break; 7274 default: 7275 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7276 } 7277 } 7278 7279 /* RRR1 format */ 7280 static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx) 7281 { 7282 uint32_t op2; 7283 uint32_t r1, r2, r3, r4, n; 7284 7285 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7286 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7287 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7288 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7289 r4 = MASK_OP_RRR1_D(ctx->opcode); 7290 n = MASK_OP_RRR1_N(ctx->opcode); 7291 7292 switch (op2) { 7293 case OPC2_32_RRR1_MADD_H_LL: 7294 CHECK_REG_PAIR(r4); 7295 CHECK_REG_PAIR(r3); 7296 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7297 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7298 break; 7299 case OPC2_32_RRR1_MADD_H_LU: 7300 CHECK_REG_PAIR(r4); 7301 CHECK_REG_PAIR(r3); 7302 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7303 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7304 break; 7305 case OPC2_32_RRR1_MADD_H_UL: 7306 CHECK_REG_PAIR(r4); 7307 CHECK_REG_PAIR(r3); 7308 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7309 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7310 break; 7311 case OPC2_32_RRR1_MADD_H_UU: 7312 CHECK_REG_PAIR(r4); 7313 CHECK_REG_PAIR(r3); 7314 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7315 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7316 break; 7317 case OPC2_32_RRR1_MADDS_H_LL: 7318 CHECK_REG_PAIR(r4); 7319 CHECK_REG_PAIR(r3); 7320 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7321 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7322 break; 7323 case OPC2_32_RRR1_MADDS_H_LU: 7324 CHECK_REG_PAIR(r4); 7325 CHECK_REG_PAIR(r3); 7326 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7327 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7328 break; 7329 case OPC2_32_RRR1_MADDS_H_UL: 7330 CHECK_REG_PAIR(r4); 7331 CHECK_REG_PAIR(r3); 7332 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7333 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7334 break; 7335 case OPC2_32_RRR1_MADDS_H_UU: 7336 CHECK_REG_PAIR(r4); 7337 CHECK_REG_PAIR(r3); 7338 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7339 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7340 break; 7341 case OPC2_32_RRR1_MADDM_H_LL: 7342 CHECK_REG_PAIR(r4); 7343 CHECK_REG_PAIR(r3); 7344 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7345 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7346 break; 7347 case OPC2_32_RRR1_MADDM_H_LU: 7348 CHECK_REG_PAIR(r4); 7349 CHECK_REG_PAIR(r3); 7350 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7351 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7352 break; 7353 case OPC2_32_RRR1_MADDM_H_UL: 7354 CHECK_REG_PAIR(r4); 7355 CHECK_REG_PAIR(r3); 7356 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7357 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7358 break; 7359 case OPC2_32_RRR1_MADDM_H_UU: 7360 CHECK_REG_PAIR(r4); 7361 CHECK_REG_PAIR(r3); 7362 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7363 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7364 break; 7365 case OPC2_32_RRR1_MADDMS_H_LL: 7366 CHECK_REG_PAIR(r4); 7367 CHECK_REG_PAIR(r3); 7368 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7369 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7370 break; 7371 case OPC2_32_RRR1_MADDMS_H_LU: 7372 CHECK_REG_PAIR(r4); 7373 CHECK_REG_PAIR(r3); 7374 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7375 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7376 break; 7377 case OPC2_32_RRR1_MADDMS_H_UL: 7378 CHECK_REG_PAIR(r4); 7379 CHECK_REG_PAIR(r3); 7380 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7381 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7382 break; 7383 case OPC2_32_RRR1_MADDMS_H_UU: 7384 CHECK_REG_PAIR(r4); 7385 CHECK_REG_PAIR(r3); 7386 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7387 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7388 break; 7389 case OPC2_32_RRR1_MADDR_H_LL: 7390 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7391 cpu_gpr_d[r2], n, MODE_LL); 7392 break; 7393 case OPC2_32_RRR1_MADDR_H_LU: 7394 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7395 cpu_gpr_d[r2], n, MODE_LU); 7396 break; 7397 case OPC2_32_RRR1_MADDR_H_UL: 7398 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7399 cpu_gpr_d[r2], n, MODE_UL); 7400 break; 7401 case OPC2_32_RRR1_MADDR_H_UU: 7402 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7403 cpu_gpr_d[r2], n, MODE_UU); 7404 break; 7405 case OPC2_32_RRR1_MADDRS_H_LL: 7406 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7407 cpu_gpr_d[r2], n, MODE_LL); 7408 break; 7409 case OPC2_32_RRR1_MADDRS_H_LU: 7410 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7411 cpu_gpr_d[r2], n, MODE_LU); 7412 break; 7413 case OPC2_32_RRR1_MADDRS_H_UL: 7414 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7415 cpu_gpr_d[r2], n, MODE_UL); 7416 break; 7417 case OPC2_32_RRR1_MADDRS_H_UU: 7418 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7419 cpu_gpr_d[r2], n, MODE_UU); 7420 break; 7421 default: 7422 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7423 } 7424 } 7425 7426 static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx) 7427 { 7428 uint32_t op2; 7429 uint32_t r1, r2, r3, r4, n; 7430 TCGv temp, temp2; 7431 7432 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7433 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7434 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7435 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7436 r4 = MASK_OP_RRR1_D(ctx->opcode); 7437 n = MASK_OP_RRR1_N(ctx->opcode); 7438 7439 temp = tcg_const_i32(n); 7440 temp2 = tcg_temp_new(); 7441 7442 switch (op2) { 7443 case OPC2_32_RRR1_MADD_Q_32: 7444 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7445 cpu_gpr_d[r2], n, 32, env); 7446 break; 7447 case OPC2_32_RRR1_MADD_Q_64: 7448 CHECK_REG_PAIR(r4); 7449 CHECK_REG_PAIR(r3); 7450 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7451 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7452 n, env); 7453 break; 7454 case OPC2_32_RRR1_MADD_Q_32_L: 7455 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7456 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7457 temp, n, 16, env); 7458 break; 7459 case OPC2_32_RRR1_MADD_Q_64_L: 7460 CHECK_REG_PAIR(r4); 7461 CHECK_REG_PAIR(r3); 7462 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7463 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7464 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7465 n, env); 7466 break; 7467 case OPC2_32_RRR1_MADD_Q_32_U: 7468 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7469 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7470 temp, n, 16, env); 7471 break; 7472 case OPC2_32_RRR1_MADD_Q_64_U: 7473 CHECK_REG_PAIR(r4); 7474 CHECK_REG_PAIR(r3); 7475 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7476 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7477 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7478 n, env); 7479 break; 7480 case OPC2_32_RRR1_MADD_Q_32_LL: 7481 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7482 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7483 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7484 break; 7485 case OPC2_32_RRR1_MADD_Q_64_LL: 7486 CHECK_REG_PAIR(r4); 7487 CHECK_REG_PAIR(r3); 7488 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7489 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7490 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7491 cpu_gpr_d[r3+1], temp, temp2, n); 7492 break; 7493 case OPC2_32_RRR1_MADD_Q_32_UU: 7494 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7495 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7496 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7497 break; 7498 case OPC2_32_RRR1_MADD_Q_64_UU: 7499 CHECK_REG_PAIR(r4); 7500 CHECK_REG_PAIR(r3); 7501 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7502 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7503 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7504 cpu_gpr_d[r3+1], temp, temp2, n); 7505 break; 7506 case OPC2_32_RRR1_MADDS_Q_32: 7507 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7508 cpu_gpr_d[r2], n, 32); 7509 break; 7510 case OPC2_32_RRR1_MADDS_Q_64: 7511 CHECK_REG_PAIR(r4); 7512 CHECK_REG_PAIR(r3); 7513 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7514 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7515 n); 7516 break; 7517 case OPC2_32_RRR1_MADDS_Q_32_L: 7518 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7519 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7520 temp, n, 16); 7521 break; 7522 case OPC2_32_RRR1_MADDS_Q_64_L: 7523 CHECK_REG_PAIR(r4); 7524 CHECK_REG_PAIR(r3); 7525 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7526 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7527 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7528 n); 7529 break; 7530 case OPC2_32_RRR1_MADDS_Q_32_U: 7531 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7532 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7533 temp, n, 16); 7534 break; 7535 case OPC2_32_RRR1_MADDS_Q_64_U: 7536 CHECK_REG_PAIR(r4); 7537 CHECK_REG_PAIR(r3); 7538 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7539 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7540 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7541 n); 7542 break; 7543 case OPC2_32_RRR1_MADDS_Q_32_LL: 7544 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7545 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7546 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7547 break; 7548 case OPC2_32_RRR1_MADDS_Q_64_LL: 7549 CHECK_REG_PAIR(r4); 7550 CHECK_REG_PAIR(r3); 7551 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7552 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7553 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7554 cpu_gpr_d[r3+1], temp, temp2, n); 7555 break; 7556 case OPC2_32_RRR1_MADDS_Q_32_UU: 7557 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7558 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7559 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7560 break; 7561 case OPC2_32_RRR1_MADDS_Q_64_UU: 7562 CHECK_REG_PAIR(r4); 7563 CHECK_REG_PAIR(r3); 7564 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7565 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7566 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7567 cpu_gpr_d[r3+1], temp, temp2, n); 7568 break; 7569 case OPC2_32_RRR1_MADDR_H_64_UL: 7570 CHECK_REG_PAIR(r3); 7571 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7572 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7573 break; 7574 case OPC2_32_RRR1_MADDRS_H_64_UL: 7575 CHECK_REG_PAIR(r3); 7576 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 7577 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 7578 break; 7579 case OPC2_32_RRR1_MADDR_Q_32_LL: 7580 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7581 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7582 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7583 break; 7584 case OPC2_32_RRR1_MADDR_Q_32_UU: 7585 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7586 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7587 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7588 break; 7589 case OPC2_32_RRR1_MADDRS_Q_32_LL: 7590 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7591 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7592 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7593 break; 7594 case OPC2_32_RRR1_MADDRS_Q_32_UU: 7595 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7596 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7597 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7598 break; 7599 default: 7600 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7601 } 7602 tcg_temp_free(temp); 7603 tcg_temp_free(temp2); 7604 } 7605 7606 static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx) 7607 { 7608 uint32_t op2; 7609 uint32_t r1, r2, r3, r4, n; 7610 7611 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7612 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7613 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7614 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7615 r4 = MASK_OP_RRR1_D(ctx->opcode); 7616 n = MASK_OP_RRR1_N(ctx->opcode); 7617 7618 switch (op2) { 7619 case OPC2_32_RRR1_MADDSU_H_32_LL: 7620 CHECK_REG_PAIR(r4); 7621 CHECK_REG_PAIR(r3); 7622 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7623 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7624 break; 7625 case OPC2_32_RRR1_MADDSU_H_32_LU: 7626 CHECK_REG_PAIR(r4); 7627 CHECK_REG_PAIR(r3); 7628 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7629 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7630 break; 7631 case OPC2_32_RRR1_MADDSU_H_32_UL: 7632 CHECK_REG_PAIR(r4); 7633 CHECK_REG_PAIR(r3); 7634 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7635 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7636 break; 7637 case OPC2_32_RRR1_MADDSU_H_32_UU: 7638 CHECK_REG_PAIR(r4); 7639 CHECK_REG_PAIR(r3); 7640 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7641 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7642 break; 7643 case OPC2_32_RRR1_MADDSUS_H_32_LL: 7644 CHECK_REG_PAIR(r4); 7645 CHECK_REG_PAIR(r3); 7646 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7647 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7648 n, MODE_LL); 7649 break; 7650 case OPC2_32_RRR1_MADDSUS_H_32_LU: 7651 CHECK_REG_PAIR(r4); 7652 CHECK_REG_PAIR(r3); 7653 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7654 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7655 n, MODE_LU); 7656 break; 7657 case OPC2_32_RRR1_MADDSUS_H_32_UL: 7658 CHECK_REG_PAIR(r4); 7659 CHECK_REG_PAIR(r3); 7660 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7661 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7662 n, MODE_UL); 7663 break; 7664 case OPC2_32_RRR1_MADDSUS_H_32_UU: 7665 CHECK_REG_PAIR(r4); 7666 CHECK_REG_PAIR(r3); 7667 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7668 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7669 n, MODE_UU); 7670 break; 7671 case OPC2_32_RRR1_MADDSUM_H_64_LL: 7672 CHECK_REG_PAIR(r4); 7673 CHECK_REG_PAIR(r3); 7674 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7675 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7676 n, MODE_LL); 7677 break; 7678 case OPC2_32_RRR1_MADDSUM_H_64_LU: 7679 CHECK_REG_PAIR(r4); 7680 CHECK_REG_PAIR(r3); 7681 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7682 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7683 n, MODE_LU); 7684 break; 7685 case OPC2_32_RRR1_MADDSUM_H_64_UL: 7686 CHECK_REG_PAIR(r4); 7687 CHECK_REG_PAIR(r3); 7688 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7689 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7690 n, MODE_UL); 7691 break; 7692 case OPC2_32_RRR1_MADDSUM_H_64_UU: 7693 CHECK_REG_PAIR(r4); 7694 CHECK_REG_PAIR(r3); 7695 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7696 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7697 n, MODE_UU); 7698 break; 7699 case OPC2_32_RRR1_MADDSUMS_H_64_LL: 7700 CHECK_REG_PAIR(r4); 7701 CHECK_REG_PAIR(r3); 7702 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7703 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7704 n, MODE_LL); 7705 break; 7706 case OPC2_32_RRR1_MADDSUMS_H_64_LU: 7707 CHECK_REG_PAIR(r4); 7708 CHECK_REG_PAIR(r3); 7709 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7710 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7711 n, MODE_LU); 7712 break; 7713 case OPC2_32_RRR1_MADDSUMS_H_64_UL: 7714 CHECK_REG_PAIR(r4); 7715 CHECK_REG_PAIR(r3); 7716 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7717 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7718 n, MODE_UL); 7719 break; 7720 case OPC2_32_RRR1_MADDSUMS_H_64_UU: 7721 CHECK_REG_PAIR(r4); 7722 CHECK_REG_PAIR(r3); 7723 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7724 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7725 n, MODE_UU); 7726 break; 7727 case OPC2_32_RRR1_MADDSUR_H_16_LL: 7728 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7729 cpu_gpr_d[r2], n, MODE_LL); 7730 break; 7731 case OPC2_32_RRR1_MADDSUR_H_16_LU: 7732 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7733 cpu_gpr_d[r2], n, MODE_LU); 7734 break; 7735 case OPC2_32_RRR1_MADDSUR_H_16_UL: 7736 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7737 cpu_gpr_d[r2], n, MODE_UL); 7738 break; 7739 case OPC2_32_RRR1_MADDSUR_H_16_UU: 7740 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7741 cpu_gpr_d[r2], n, MODE_UU); 7742 break; 7743 case OPC2_32_RRR1_MADDSURS_H_16_LL: 7744 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7745 cpu_gpr_d[r2], n, MODE_LL); 7746 break; 7747 case OPC2_32_RRR1_MADDSURS_H_16_LU: 7748 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7749 cpu_gpr_d[r2], n, MODE_LU); 7750 break; 7751 case OPC2_32_RRR1_MADDSURS_H_16_UL: 7752 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7753 cpu_gpr_d[r2], n, MODE_UL); 7754 break; 7755 case OPC2_32_RRR1_MADDSURS_H_16_UU: 7756 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7757 cpu_gpr_d[r2], n, MODE_UU); 7758 break; 7759 default: 7760 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7761 } 7762 } 7763 7764 static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx) 7765 { 7766 uint32_t op2; 7767 uint32_t r1, r2, r3, r4, n; 7768 7769 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7770 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7771 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7772 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7773 r4 = MASK_OP_RRR1_D(ctx->opcode); 7774 n = MASK_OP_RRR1_N(ctx->opcode); 7775 7776 switch (op2) { 7777 case OPC2_32_RRR1_MSUB_H_LL: 7778 CHECK_REG_PAIR(r4); 7779 CHECK_REG_PAIR(r3); 7780 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7781 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7782 break; 7783 case OPC2_32_RRR1_MSUB_H_LU: 7784 CHECK_REG_PAIR(r4); 7785 CHECK_REG_PAIR(r3); 7786 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7787 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7788 break; 7789 case OPC2_32_RRR1_MSUB_H_UL: 7790 CHECK_REG_PAIR(r4); 7791 CHECK_REG_PAIR(r3); 7792 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7793 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7794 break; 7795 case OPC2_32_RRR1_MSUB_H_UU: 7796 CHECK_REG_PAIR(r4); 7797 CHECK_REG_PAIR(r3); 7798 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7799 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7800 break; 7801 case OPC2_32_RRR1_MSUBS_H_LL: 7802 CHECK_REG_PAIR(r4); 7803 CHECK_REG_PAIR(r3); 7804 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7805 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7806 break; 7807 case OPC2_32_RRR1_MSUBS_H_LU: 7808 CHECK_REG_PAIR(r4); 7809 CHECK_REG_PAIR(r3); 7810 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7811 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7812 break; 7813 case OPC2_32_RRR1_MSUBS_H_UL: 7814 CHECK_REG_PAIR(r4); 7815 CHECK_REG_PAIR(r3); 7816 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7817 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7818 break; 7819 case OPC2_32_RRR1_MSUBS_H_UU: 7820 CHECK_REG_PAIR(r4); 7821 CHECK_REG_PAIR(r3); 7822 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7823 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7824 break; 7825 case OPC2_32_RRR1_MSUBM_H_LL: 7826 CHECK_REG_PAIR(r4); 7827 CHECK_REG_PAIR(r3); 7828 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7829 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7830 break; 7831 case OPC2_32_RRR1_MSUBM_H_LU: 7832 CHECK_REG_PAIR(r4); 7833 CHECK_REG_PAIR(r3); 7834 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7835 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7836 break; 7837 case OPC2_32_RRR1_MSUBM_H_UL: 7838 CHECK_REG_PAIR(r4); 7839 CHECK_REG_PAIR(r3); 7840 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7841 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7842 break; 7843 case OPC2_32_RRR1_MSUBM_H_UU: 7844 CHECK_REG_PAIR(r4); 7845 CHECK_REG_PAIR(r3); 7846 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7847 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7848 break; 7849 case OPC2_32_RRR1_MSUBMS_H_LL: 7850 CHECK_REG_PAIR(r4); 7851 CHECK_REG_PAIR(r3); 7852 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7853 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 7854 break; 7855 case OPC2_32_RRR1_MSUBMS_H_LU: 7856 CHECK_REG_PAIR(r4); 7857 CHECK_REG_PAIR(r3); 7858 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7859 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 7860 break; 7861 case OPC2_32_RRR1_MSUBMS_H_UL: 7862 CHECK_REG_PAIR(r4); 7863 CHECK_REG_PAIR(r3); 7864 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7865 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 7866 break; 7867 case OPC2_32_RRR1_MSUBMS_H_UU: 7868 CHECK_REG_PAIR(r4); 7869 CHECK_REG_PAIR(r3); 7870 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7871 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 7872 break; 7873 case OPC2_32_RRR1_MSUBR_H_LL: 7874 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7875 cpu_gpr_d[r2], n, MODE_LL); 7876 break; 7877 case OPC2_32_RRR1_MSUBR_H_LU: 7878 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7879 cpu_gpr_d[r2], n, MODE_LU); 7880 break; 7881 case OPC2_32_RRR1_MSUBR_H_UL: 7882 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7883 cpu_gpr_d[r2], n, MODE_UL); 7884 break; 7885 case OPC2_32_RRR1_MSUBR_H_UU: 7886 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7887 cpu_gpr_d[r2], n, MODE_UU); 7888 break; 7889 case OPC2_32_RRR1_MSUBRS_H_LL: 7890 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7891 cpu_gpr_d[r2], n, MODE_LL); 7892 break; 7893 case OPC2_32_RRR1_MSUBRS_H_LU: 7894 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7895 cpu_gpr_d[r2], n, MODE_LU); 7896 break; 7897 case OPC2_32_RRR1_MSUBRS_H_UL: 7898 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7899 cpu_gpr_d[r2], n, MODE_UL); 7900 break; 7901 case OPC2_32_RRR1_MSUBRS_H_UU: 7902 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7903 cpu_gpr_d[r2], n, MODE_UU); 7904 break; 7905 default: 7906 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 7907 } 7908 } 7909 7910 static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx) 7911 { 7912 uint32_t op2; 7913 uint32_t r1, r2, r3, r4, n; 7914 TCGv temp, temp2; 7915 7916 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 7917 r1 = MASK_OP_RRR1_S1(ctx->opcode); 7918 r2 = MASK_OP_RRR1_S2(ctx->opcode); 7919 r3 = MASK_OP_RRR1_S3(ctx->opcode); 7920 r4 = MASK_OP_RRR1_D(ctx->opcode); 7921 n = MASK_OP_RRR1_N(ctx->opcode); 7922 7923 temp = tcg_const_i32(n); 7924 temp2 = tcg_temp_new(); 7925 7926 switch (op2) { 7927 case OPC2_32_RRR1_MSUB_Q_32: 7928 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7929 cpu_gpr_d[r2], n, 32, env); 7930 break; 7931 case OPC2_32_RRR1_MSUB_Q_64: 7932 CHECK_REG_PAIR(r4); 7933 CHECK_REG_PAIR(r3); 7934 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7935 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7936 n, env); 7937 break; 7938 case OPC2_32_RRR1_MSUB_Q_32_L: 7939 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7940 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7941 temp, n, 16, env); 7942 break; 7943 case OPC2_32_RRR1_MSUB_Q_64_L: 7944 CHECK_REG_PAIR(r4); 7945 CHECK_REG_PAIR(r3); 7946 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 7947 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7948 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7949 n, env); 7950 break; 7951 case OPC2_32_RRR1_MSUB_Q_32_U: 7952 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7953 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7954 temp, n, 16, env); 7955 break; 7956 case OPC2_32_RRR1_MSUB_Q_64_U: 7957 CHECK_REG_PAIR(r4); 7958 CHECK_REG_PAIR(r3); 7959 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 7960 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7961 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 7962 n, env); 7963 break; 7964 case OPC2_32_RRR1_MSUB_Q_32_LL: 7965 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7966 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7967 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7968 break; 7969 case OPC2_32_RRR1_MSUB_Q_64_LL: 7970 CHECK_REG_PAIR(r4); 7971 CHECK_REG_PAIR(r3); 7972 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 7973 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 7974 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7975 cpu_gpr_d[r3+1], temp, temp2, n); 7976 break; 7977 case OPC2_32_RRR1_MSUB_Q_32_UU: 7978 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7979 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7980 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 7981 break; 7982 case OPC2_32_RRR1_MSUB_Q_64_UU: 7983 CHECK_REG_PAIR(r4); 7984 CHECK_REG_PAIR(r3); 7985 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 7986 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 7987 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7988 cpu_gpr_d[r3+1], temp, temp2, n); 7989 break; 7990 case OPC2_32_RRR1_MSUBS_Q_32: 7991 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 7992 cpu_gpr_d[r2], n, 32); 7993 break; 7994 case OPC2_32_RRR1_MSUBS_Q_64: 7995 CHECK_REG_PAIR(r4); 7996 CHECK_REG_PAIR(r3); 7997 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 7998 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 7999 n); 8000 break; 8001 case OPC2_32_RRR1_MSUBS_Q_32_L: 8002 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 8003 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8004 temp, n, 16); 8005 break; 8006 case OPC2_32_RRR1_MSUBS_Q_64_L: 8007 CHECK_REG_PAIR(r4); 8008 CHECK_REG_PAIR(r3); 8009 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]); 8010 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8011 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 8012 n); 8013 break; 8014 case OPC2_32_RRR1_MSUBS_Q_32_U: 8015 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 8016 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8017 temp, n, 16); 8018 break; 8019 case OPC2_32_RRR1_MSUBS_Q_64_U: 8020 CHECK_REG_PAIR(r4); 8021 CHECK_REG_PAIR(r3); 8022 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16); 8023 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8024 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, 8025 n); 8026 break; 8027 case OPC2_32_RRR1_MSUBS_Q_32_LL: 8028 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 8029 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 8030 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8031 break; 8032 case OPC2_32_RRR1_MSUBS_Q_64_LL: 8033 CHECK_REG_PAIR(r4); 8034 CHECK_REG_PAIR(r3); 8035 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 8036 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 8037 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8038 cpu_gpr_d[r3+1], temp, temp2, n); 8039 break; 8040 case OPC2_32_RRR1_MSUBS_Q_32_UU: 8041 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 8042 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 8043 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8044 break; 8045 case OPC2_32_RRR1_MSUBS_Q_64_UU: 8046 CHECK_REG_PAIR(r4); 8047 CHECK_REG_PAIR(r3); 8048 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 8049 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 8050 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8051 cpu_gpr_d[r3+1], temp, temp2, n); 8052 break; 8053 case OPC2_32_RRR1_MSUBR_H_64_UL: 8054 CHECK_REG_PAIR(r3); 8055 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 8056 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 8057 break; 8058 case OPC2_32_RRR1_MSUBRS_H_64_UL: 8059 CHECK_REG_PAIR(r3); 8060 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1], 8061 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2); 8062 break; 8063 case OPC2_32_RRR1_MSUBR_Q_32_LL: 8064 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 8065 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 8066 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8067 break; 8068 case OPC2_32_RRR1_MSUBR_Q_32_UU: 8069 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 8070 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 8071 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8072 break; 8073 case OPC2_32_RRR1_MSUBRS_Q_32_LL: 8074 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]); 8075 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]); 8076 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8077 break; 8078 case OPC2_32_RRR1_MSUBRS_Q_32_UU: 8079 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16); 8080 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16); 8081 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n); 8082 break; 8083 default: 8084 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8085 } 8086 tcg_temp_free(temp); 8087 tcg_temp_free(temp2); 8088 } 8089 8090 static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx) 8091 { 8092 uint32_t op2; 8093 uint32_t r1, r2, r3, r4, n; 8094 8095 op2 = MASK_OP_RRR1_OP2(ctx->opcode); 8096 r1 = MASK_OP_RRR1_S1(ctx->opcode); 8097 r2 = MASK_OP_RRR1_S2(ctx->opcode); 8098 r3 = MASK_OP_RRR1_S3(ctx->opcode); 8099 r4 = MASK_OP_RRR1_D(ctx->opcode); 8100 n = MASK_OP_RRR1_N(ctx->opcode); 8101 8102 switch (op2) { 8103 case OPC2_32_RRR1_MSUBAD_H_32_LL: 8104 CHECK_REG_PAIR(r4); 8105 CHECK_REG_PAIR(r3); 8106 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8107 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL); 8108 break; 8109 case OPC2_32_RRR1_MSUBAD_H_32_LU: 8110 CHECK_REG_PAIR(r4); 8111 CHECK_REG_PAIR(r3); 8112 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8113 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU); 8114 break; 8115 case OPC2_32_RRR1_MSUBAD_H_32_UL: 8116 CHECK_REG_PAIR(r4); 8117 CHECK_REG_PAIR(r3); 8118 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8119 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL); 8120 break; 8121 case OPC2_32_RRR1_MSUBAD_H_32_UU: 8122 CHECK_REG_PAIR(r4); 8123 CHECK_REG_PAIR(r3); 8124 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8125 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU); 8126 break; 8127 case OPC2_32_RRR1_MSUBADS_H_32_LL: 8128 CHECK_REG_PAIR(r4); 8129 CHECK_REG_PAIR(r3); 8130 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8131 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8132 n, MODE_LL); 8133 break; 8134 case OPC2_32_RRR1_MSUBADS_H_32_LU: 8135 CHECK_REG_PAIR(r4); 8136 CHECK_REG_PAIR(r3); 8137 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8138 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8139 n, MODE_LU); 8140 break; 8141 case OPC2_32_RRR1_MSUBADS_H_32_UL: 8142 CHECK_REG_PAIR(r4); 8143 CHECK_REG_PAIR(r3); 8144 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8145 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8146 n, MODE_UL); 8147 break; 8148 case OPC2_32_RRR1_MSUBADS_H_32_UU: 8149 CHECK_REG_PAIR(r4); 8150 CHECK_REG_PAIR(r3); 8151 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8152 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8153 n, MODE_UU); 8154 break; 8155 case OPC2_32_RRR1_MSUBADM_H_64_LL: 8156 CHECK_REG_PAIR(r4); 8157 CHECK_REG_PAIR(r3); 8158 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8159 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8160 n, MODE_LL); 8161 break; 8162 case OPC2_32_RRR1_MSUBADM_H_64_LU: 8163 CHECK_REG_PAIR(r4); 8164 CHECK_REG_PAIR(r3); 8165 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8166 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8167 n, MODE_LU); 8168 break; 8169 case OPC2_32_RRR1_MSUBADM_H_64_UL: 8170 CHECK_REG_PAIR(r4); 8171 CHECK_REG_PAIR(r3); 8172 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8173 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8174 n, MODE_UL); 8175 break; 8176 case OPC2_32_RRR1_MSUBADM_H_64_UU: 8177 CHECK_REG_PAIR(r4); 8178 CHECK_REG_PAIR(r3); 8179 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8180 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8181 n, MODE_UU); 8182 break; 8183 case OPC2_32_RRR1_MSUBADMS_H_64_LL: 8184 CHECK_REG_PAIR(r4); 8185 CHECK_REG_PAIR(r3); 8186 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8187 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8188 n, MODE_LL); 8189 break; 8190 case OPC2_32_RRR1_MSUBADMS_H_64_LU: 8191 CHECK_REG_PAIR(r4); 8192 CHECK_REG_PAIR(r3); 8193 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8194 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8195 n, MODE_LU); 8196 break; 8197 case OPC2_32_RRR1_MSUBADMS_H_64_UL: 8198 CHECK_REG_PAIR(r4); 8199 CHECK_REG_PAIR(r3); 8200 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8201 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8202 n, MODE_UL); 8203 break; 8204 case OPC2_32_RRR1_MSUBADMS_H_64_UU: 8205 CHECK_REG_PAIR(r4); 8206 CHECK_REG_PAIR(r3); 8207 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3], 8208 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], 8209 n, MODE_UU); 8210 break; 8211 case OPC2_32_RRR1_MSUBADR_H_16_LL: 8212 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8213 cpu_gpr_d[r2], n, MODE_LL); 8214 break; 8215 case OPC2_32_RRR1_MSUBADR_H_16_LU: 8216 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8217 cpu_gpr_d[r2], n, MODE_LU); 8218 break; 8219 case OPC2_32_RRR1_MSUBADR_H_16_UL: 8220 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8221 cpu_gpr_d[r2], n, MODE_UL); 8222 break; 8223 case OPC2_32_RRR1_MSUBADR_H_16_UU: 8224 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8225 cpu_gpr_d[r2], n, MODE_UU); 8226 break; 8227 case OPC2_32_RRR1_MSUBADRS_H_16_LL: 8228 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8229 cpu_gpr_d[r2], n, MODE_LL); 8230 break; 8231 case OPC2_32_RRR1_MSUBADRS_H_16_LU: 8232 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8233 cpu_gpr_d[r2], n, MODE_LU); 8234 break; 8235 case OPC2_32_RRR1_MSUBADRS_H_16_UL: 8236 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8237 cpu_gpr_d[r2], n, MODE_UL); 8238 break; 8239 case OPC2_32_RRR1_MSUBADRS_H_16_UU: 8240 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1], 8241 cpu_gpr_d[r2], n, MODE_UU); 8242 break; 8243 default: 8244 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8245 } 8246 } 8247 8248 /* RRRR format */ 8249 static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx) 8250 { 8251 uint32_t op2; 8252 int r1, r2, r3, r4; 8253 TCGv tmp_width, tmp_pos; 8254 8255 r1 = MASK_OP_RRRR_S1(ctx->opcode); 8256 r2 = MASK_OP_RRRR_S2(ctx->opcode); 8257 r3 = MASK_OP_RRRR_S3(ctx->opcode); 8258 r4 = MASK_OP_RRRR_D(ctx->opcode); 8259 op2 = MASK_OP_RRRR_OP2(ctx->opcode); 8260 8261 tmp_pos = tcg_temp_new(); 8262 tmp_width = tcg_temp_new(); 8263 8264 switch (op2) { 8265 case OPC2_32_RRRR_DEXTR: 8266 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 8267 if (r1 == r2) { 8268 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 8269 } else { 8270 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos); 8271 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 8272 tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos); 8273 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos); 8274 } 8275 break; 8276 case OPC2_32_RRRR_EXTR: 8277 case OPC2_32_RRRR_EXTR_U: 8278 CHECK_REG_PAIR(r3); 8279 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 8280 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 8281 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width); 8282 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos); 8283 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos); 8284 tcg_gen_subfi_tl(tmp_width, 32, tmp_width); 8285 if (op2 == OPC2_32_RRRR_EXTR) { 8286 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 8287 } else { 8288 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width); 8289 } 8290 break; 8291 case OPC2_32_RRRR_INSERT: 8292 CHECK_REG_PAIR(r3); 8293 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f); 8294 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f); 8295 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width, 8296 tmp_pos); 8297 break; 8298 default: 8299 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8300 } 8301 tcg_temp_free(tmp_pos); 8302 tcg_temp_free(tmp_width); 8303 } 8304 8305 /* RRRW format */ 8306 static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) 8307 { 8308 uint32_t op2; 8309 int r1, r2, r3, r4; 8310 int32_t width; 8311 8312 TCGv temp, temp2; 8313 8314 op2 = MASK_OP_RRRW_OP2(ctx->opcode); 8315 r1 = MASK_OP_RRRW_S1(ctx->opcode); 8316 r2 = MASK_OP_RRRW_S2(ctx->opcode); 8317 r3 = MASK_OP_RRRW_S3(ctx->opcode); 8318 r4 = MASK_OP_RRRW_D(ctx->opcode); 8319 width = MASK_OP_RRRW_WIDTH(ctx->opcode); 8320 8321 temp = tcg_temp_new(); 8322 8323 switch (op2) { 8324 case OPC2_32_RRRW_EXTR: 8325 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 8326 tcg_gen_addi_tl(temp, temp, width); 8327 tcg_gen_subfi_tl(temp, 32, temp); 8328 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 8329 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width); 8330 break; 8331 case OPC2_32_RRRW_EXTR_U: 8332 if (width == 0) { 8333 tcg_gen_movi_tl(cpu_gpr_d[r4], 0); 8334 } else { 8335 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 8336 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp); 8337 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width)); 8338 } 8339 break; 8340 case OPC2_32_RRRW_IMASK: 8341 temp2 = tcg_temp_new(); 8342 8343 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f); 8344 tcg_gen_movi_tl(temp2, (1 << width) - 1); 8345 tcg_gen_shl_tl(temp2, temp2, temp); 8346 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp); 8347 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2); 8348 8349 tcg_temp_free(temp2); 8350 break; 8351 case OPC2_32_RRRW_INSERT: 8352 temp2 = tcg_temp_new(); 8353 8354 tcg_gen_movi_tl(temp, width); 8355 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f); 8356 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2); 8357 8358 tcg_temp_free(temp2); 8359 break; 8360 default: 8361 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8362 } 8363 tcg_temp_free(temp); 8364 } 8365 8366 /* SYS Format*/ 8367 static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx) 8368 { 8369 uint32_t op2; 8370 uint32_t r1; 8371 TCGLabel *l1; 8372 TCGv tmp; 8373 8374 op2 = MASK_OP_SYS_OP2(ctx->opcode); 8375 r1 = MASK_OP_SYS_S1D(ctx->opcode); 8376 8377 switch (op2) { 8378 case OPC2_32_SYS_DEBUG: 8379 /* raise EXCP_DEBUG */ 8380 break; 8381 case OPC2_32_SYS_DISABLE: 8382 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE_1_3); 8383 break; 8384 case OPC2_32_SYS_DSYNC: 8385 break; 8386 case OPC2_32_SYS_ENABLE: 8387 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE_1_3); 8388 break; 8389 case OPC2_32_SYS_ISYNC: 8390 break; 8391 case OPC2_32_SYS_NOP: 8392 break; 8393 case OPC2_32_SYS_RET: 8394 gen_compute_branch(ctx, op2, 0, 0, 0, 0); 8395 break; 8396 case OPC2_32_SYS_FRET: 8397 gen_fret(ctx); 8398 break; 8399 case OPC2_32_SYS_RFE: 8400 gen_helper_rfe(cpu_env); 8401 tcg_gen_exit_tb(NULL, 0); 8402 ctx->bstate = BS_BRANCH; 8403 break; 8404 case OPC2_32_SYS_RFM: 8405 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) { 8406 tmp = tcg_temp_new(); 8407 l1 = gen_new_label(); 8408 8409 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR)); 8410 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE); 8411 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1); 8412 gen_helper_rfm(cpu_env); 8413 gen_set_label(l1); 8414 tcg_gen_exit_tb(NULL, 0); 8415 ctx->bstate = BS_BRANCH; 8416 tcg_temp_free(tmp); 8417 } else { 8418 /* generate privilege trap */ 8419 } 8420 break; 8421 case OPC2_32_SYS_RSLCX: 8422 gen_helper_rslcx(cpu_env); 8423 break; 8424 case OPC2_32_SYS_SVLCX: 8425 gen_helper_svlcx(cpu_env); 8426 break; 8427 case OPC2_32_SYS_RESTORE: 8428 if (tricore_feature(env, TRICORE_FEATURE_16)) { 8429 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM || 8430 (ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_UM1) { 8431 tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); 8432 } /* else raise privilege trap */ 8433 } else { 8434 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8435 } 8436 break; 8437 case OPC2_32_SYS_TRAPSV: 8438 l1 = gen_new_label(); 8439 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_SV, 0, l1); 8440 generate_trap(ctx, TRAPC_ASSERT, TIN5_SOVF); 8441 gen_set_label(l1); 8442 break; 8443 case OPC2_32_SYS_TRAPV: 8444 l1 = gen_new_label(); 8445 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_PSW_V, 0, l1); 8446 generate_trap(ctx, TRAPC_ASSERT, TIN5_OVF); 8447 gen_set_label(l1); 8448 break; 8449 default: 8450 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8451 } 8452 } 8453 8454 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) 8455 { 8456 int op1; 8457 int32_t r1, r2, r3; 8458 int32_t address, const16; 8459 int8_t b, const4; 8460 int32_t bpos; 8461 TCGv temp, temp2, temp3; 8462 8463 op1 = MASK_OP_MAJOR(ctx->opcode); 8464 8465 /* handle JNZ.T opcode only being 7 bit long */ 8466 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) { 8467 op1 = OPCM_32_BRN_JTT; 8468 } 8469 8470 switch (op1) { 8471 /* ABS-format */ 8472 case OPCM_32_ABS_LDW: 8473 decode_abs_ldw(env, ctx); 8474 break; 8475 case OPCM_32_ABS_LDB: 8476 decode_abs_ldb(env, ctx); 8477 break; 8478 case OPCM_32_ABS_LDMST_SWAP: 8479 decode_abs_ldst_swap(env, ctx); 8480 break; 8481 case OPCM_32_ABS_LDST_CONTEXT: 8482 decode_abs_ldst_context(env, ctx); 8483 break; 8484 case OPCM_32_ABS_STORE: 8485 decode_abs_store(env, ctx); 8486 break; 8487 case OPCM_32_ABS_STOREB_H: 8488 decode_abs_storeb_h(env, ctx); 8489 break; 8490 case OPC1_32_ABS_STOREQ: 8491 address = MASK_OP_ABS_OFF18(ctx->opcode); 8492 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8493 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 8494 temp2 = tcg_temp_new(); 8495 8496 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16); 8497 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW); 8498 8499 tcg_temp_free(temp2); 8500 tcg_temp_free(temp); 8501 break; 8502 case OPC1_32_ABS_LD_Q: 8503 address = MASK_OP_ABS_OFF18(ctx->opcode); 8504 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8505 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 8506 8507 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW); 8508 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16); 8509 8510 tcg_temp_free(temp); 8511 break; 8512 case OPC1_32_ABS_LEA: 8513 address = MASK_OP_ABS_OFF18(ctx->opcode); 8514 r1 = MASK_OP_ABS_S1D(ctx->opcode); 8515 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address)); 8516 break; 8517 /* ABSB-format */ 8518 case OPC1_32_ABSB_ST_T: 8519 address = MASK_OP_ABS_OFF18(ctx->opcode); 8520 b = MASK_OP_ABSB_B(ctx->opcode); 8521 bpos = MASK_OP_ABSB_BPOS(ctx->opcode); 8522 8523 temp = tcg_const_i32(EA_ABS_FORMAT(address)); 8524 temp2 = tcg_temp_new(); 8525 8526 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB); 8527 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos)); 8528 tcg_gen_ori_tl(temp2, temp2, (b << bpos)); 8529 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB); 8530 8531 tcg_temp_free(temp); 8532 tcg_temp_free(temp2); 8533 break; 8534 /* B-format */ 8535 case OPC1_32_B_CALL: 8536 case OPC1_32_B_CALLA: 8537 case OPC1_32_B_FCALL: 8538 case OPC1_32_B_FCALLA: 8539 case OPC1_32_B_J: 8540 case OPC1_32_B_JA: 8541 case OPC1_32_B_JL: 8542 case OPC1_32_B_JLA: 8543 address = MASK_OP_B_DISP24_SEXT(ctx->opcode); 8544 gen_compute_branch(ctx, op1, 0, 0, 0, address); 8545 break; 8546 /* Bit-format */ 8547 case OPCM_32_BIT_ANDACC: 8548 decode_bit_andacc(env, ctx); 8549 break; 8550 case OPCM_32_BIT_LOGICAL_T1: 8551 decode_bit_logical_t(env, ctx); 8552 break; 8553 case OPCM_32_BIT_INSERT: 8554 decode_bit_insert(env, ctx); 8555 break; 8556 case OPCM_32_BIT_LOGICAL_T2: 8557 decode_bit_logical_t2(env, ctx); 8558 break; 8559 case OPCM_32_BIT_ORAND: 8560 decode_bit_orand(env, ctx); 8561 break; 8562 case OPCM_32_BIT_SH_LOGIC1: 8563 decode_bit_sh_logic1(env, ctx); 8564 break; 8565 case OPCM_32_BIT_SH_LOGIC2: 8566 decode_bit_sh_logic2(env, ctx); 8567 break; 8568 /* BO Format */ 8569 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE: 8570 decode_bo_addrmode_post_pre_base(env, ctx); 8571 break; 8572 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR: 8573 decode_bo_addrmode_bitreverse_circular(env, ctx); 8574 break; 8575 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE: 8576 decode_bo_addrmode_ld_post_pre_base(env, ctx); 8577 break; 8578 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR: 8579 decode_bo_addrmode_ld_bitreverse_circular(env, ctx); 8580 break; 8581 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE: 8582 decode_bo_addrmode_stctx_post_pre_base(env, ctx); 8583 break; 8584 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR: 8585 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx); 8586 break; 8587 /* BOL-format */ 8588 case OPC1_32_BOL_LD_A_LONGOFF: 8589 case OPC1_32_BOL_LD_W_LONGOFF: 8590 case OPC1_32_BOL_LEA_LONGOFF: 8591 case OPC1_32_BOL_ST_W_LONGOFF: 8592 case OPC1_32_BOL_ST_A_LONGOFF: 8593 case OPC1_32_BOL_LD_B_LONGOFF: 8594 case OPC1_32_BOL_LD_BU_LONGOFF: 8595 case OPC1_32_BOL_LD_H_LONGOFF: 8596 case OPC1_32_BOL_LD_HU_LONGOFF: 8597 case OPC1_32_BOL_ST_B_LONGOFF: 8598 case OPC1_32_BOL_ST_H_LONGOFF: 8599 decode_bol_opc(env, ctx, op1); 8600 break; 8601 /* BRC Format */ 8602 case OPCM_32_BRC_EQ_NEQ: 8603 case OPCM_32_BRC_GE: 8604 case OPCM_32_BRC_JLT: 8605 case OPCM_32_BRC_JNE: 8606 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode); 8607 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode); 8608 r1 = MASK_OP_BRC_S1(ctx->opcode); 8609 gen_compute_branch(ctx, op1, r1, 0, const4, address); 8610 break; 8611 /* BRN Format */ 8612 case OPCM_32_BRN_JTT: 8613 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode); 8614 r1 = MASK_OP_BRN_S1(ctx->opcode); 8615 gen_compute_branch(ctx, op1, r1, 0, 0, address); 8616 break; 8617 /* BRR Format */ 8618 case OPCM_32_BRR_EQ_NEQ: 8619 case OPCM_32_BRR_ADDR_EQ_NEQ: 8620 case OPCM_32_BRR_GE: 8621 case OPCM_32_BRR_JLT: 8622 case OPCM_32_BRR_JNE: 8623 case OPCM_32_BRR_JNZ: 8624 case OPCM_32_BRR_LOOP: 8625 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode); 8626 r2 = MASK_OP_BRR_S2(ctx->opcode); 8627 r1 = MASK_OP_BRR_S1(ctx->opcode); 8628 gen_compute_branch(ctx, op1, r1, r2, 0, address); 8629 break; 8630 /* RC Format */ 8631 case OPCM_32_RC_LOGICAL_SHIFT: 8632 decode_rc_logical_shift(env, ctx); 8633 break; 8634 case OPCM_32_RC_ACCUMULATOR: 8635 decode_rc_accumulator(env, ctx); 8636 break; 8637 case OPCM_32_RC_SERVICEROUTINE: 8638 decode_rc_serviceroutine(env, ctx); 8639 break; 8640 case OPCM_32_RC_MUL: 8641 decode_rc_mul(env, ctx); 8642 break; 8643 /* RCPW Format */ 8644 case OPCM_32_RCPW_MASK_INSERT: 8645 decode_rcpw_insert(env, ctx); 8646 break; 8647 /* RCRR Format */ 8648 case OPC1_32_RCRR_INSERT: 8649 r1 = MASK_OP_RCRR_S1(ctx->opcode); 8650 r2 = MASK_OP_RCRR_S3(ctx->opcode); 8651 r3 = MASK_OP_RCRR_D(ctx->opcode); 8652 const16 = MASK_OP_RCRR_CONST4(ctx->opcode); 8653 temp = tcg_const_i32(const16); 8654 temp2 = tcg_temp_new(); /* width*/ 8655 temp3 = tcg_temp_new(); /* pos */ 8656 8657 CHECK_REG_PAIR(r3); 8658 8659 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f); 8660 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); 8661 8662 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); 8663 8664 tcg_temp_free(temp); 8665 tcg_temp_free(temp2); 8666 tcg_temp_free(temp3); 8667 break; 8668 /* RCRW Format */ 8669 case OPCM_32_RCRW_MASK_INSERT: 8670 decode_rcrw_insert(env, ctx); 8671 break; 8672 /* RCR Format */ 8673 case OPCM_32_RCR_COND_SELECT: 8674 decode_rcr_cond_select(env, ctx); 8675 break; 8676 case OPCM_32_RCR_MADD: 8677 decode_rcr_madd(env, ctx); 8678 break; 8679 case OPCM_32_RCR_MSUB: 8680 decode_rcr_msub(env, ctx); 8681 break; 8682 /* RLC Format */ 8683 case OPC1_32_RLC_ADDI: 8684 case OPC1_32_RLC_ADDIH: 8685 case OPC1_32_RLC_ADDIH_A: 8686 case OPC1_32_RLC_MFCR: 8687 case OPC1_32_RLC_MOV: 8688 case OPC1_32_RLC_MOV_64: 8689 case OPC1_32_RLC_MOV_U: 8690 case OPC1_32_RLC_MOV_H: 8691 case OPC1_32_RLC_MOVH_A: 8692 case OPC1_32_RLC_MTCR: 8693 decode_rlc_opc(env, ctx, op1); 8694 break; 8695 /* RR Format */ 8696 case OPCM_32_RR_ACCUMULATOR: 8697 decode_rr_accumulator(env, ctx); 8698 break; 8699 case OPCM_32_RR_LOGICAL_SHIFT: 8700 decode_rr_logical_shift(env, ctx); 8701 break; 8702 case OPCM_32_RR_ADDRESS: 8703 decode_rr_address(env, ctx); 8704 break; 8705 case OPCM_32_RR_IDIRECT: 8706 decode_rr_idirect(env, ctx); 8707 break; 8708 case OPCM_32_RR_DIVIDE: 8709 decode_rr_divide(env, ctx); 8710 break; 8711 /* RR1 Format */ 8712 case OPCM_32_RR1_MUL: 8713 decode_rr1_mul(env, ctx); 8714 break; 8715 case OPCM_32_RR1_MULQ: 8716 decode_rr1_mulq(env, ctx); 8717 break; 8718 /* RR2 format */ 8719 case OPCM_32_RR2_MUL: 8720 decode_rr2_mul(env, ctx); 8721 break; 8722 /* RRPW format */ 8723 case OPCM_32_RRPW_EXTRACT_INSERT: 8724 decode_rrpw_extract_insert(env, ctx); 8725 break; 8726 case OPC1_32_RRPW_DEXTR: 8727 r1 = MASK_OP_RRPW_S1(ctx->opcode); 8728 r2 = MASK_OP_RRPW_S2(ctx->opcode); 8729 r3 = MASK_OP_RRPW_D(ctx->opcode); 8730 const16 = MASK_OP_RRPW_POS(ctx->opcode); 8731 if (r1 == r2) { 8732 tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16); 8733 } else { 8734 temp = tcg_temp_new(); 8735 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16); 8736 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16); 8737 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp); 8738 tcg_temp_free(temp); 8739 } 8740 break; 8741 /* RRR Format */ 8742 case OPCM_32_RRR_COND_SELECT: 8743 decode_rrr_cond_select(env, ctx); 8744 break; 8745 case OPCM_32_RRR_DIVIDE: 8746 decode_rrr_divide(env, ctx); 8747 break; 8748 /* RRR2 Format */ 8749 case OPCM_32_RRR2_MADD: 8750 decode_rrr2_madd(env, ctx); 8751 break; 8752 case OPCM_32_RRR2_MSUB: 8753 decode_rrr2_msub(env, ctx); 8754 break; 8755 /* RRR1 format */ 8756 case OPCM_32_RRR1_MADD: 8757 decode_rrr1_madd(env, ctx); 8758 break; 8759 case OPCM_32_RRR1_MADDQ_H: 8760 decode_rrr1_maddq_h(env, ctx); 8761 break; 8762 case OPCM_32_RRR1_MADDSU_H: 8763 decode_rrr1_maddsu_h(env, ctx); 8764 break; 8765 case OPCM_32_RRR1_MSUB_H: 8766 decode_rrr1_msub(env, ctx); 8767 break; 8768 case OPCM_32_RRR1_MSUB_Q: 8769 decode_rrr1_msubq_h(env, ctx); 8770 break; 8771 case OPCM_32_RRR1_MSUBAD_H: 8772 decode_rrr1_msubad_h(env, ctx); 8773 break; 8774 /* RRRR format */ 8775 case OPCM_32_RRRR_EXTRACT_INSERT: 8776 decode_rrrr_extract_insert(env, ctx); 8777 break; 8778 /* RRRW format */ 8779 case OPCM_32_RRRW_EXTRACT_INSERT: 8780 decode_rrrw_extract_insert(env, ctx); 8781 break; 8782 /* SYS format */ 8783 case OPCM_32_SYS_INTERRUPTS: 8784 decode_sys_interrupts(env, ctx); 8785 break; 8786 case OPC1_32_SYS_RSTV: 8787 tcg_gen_movi_tl(cpu_PSW_V, 0); 8788 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V); 8789 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V); 8790 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V); 8791 break; 8792 default: 8793 generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); 8794 } 8795 } 8796 8797 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch) 8798 { 8799 /* 16-Bit Instruction */ 8800 if ((ctx->opcode & 0x1) == 0) { 8801 ctx->next_pc = ctx->pc + 2; 8802 decode_16Bit_opc(env, ctx); 8803 /* 32-Bit Instruction */ 8804 } else { 8805 ctx->next_pc = ctx->pc + 4; 8806 decode_32Bit_opc(env, ctx); 8807 } 8808 } 8809 8810 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 8811 { 8812 CPUTriCoreState *env = cs->env_ptr; 8813 DisasContext ctx; 8814 target_ulong pc_start; 8815 int num_insns = 0; 8816 8817 pc_start = tb->pc; 8818 ctx.pc = pc_start; 8819 ctx.saved_pc = -1; 8820 ctx.tb = tb; 8821 ctx.singlestep_enabled = cs->singlestep_enabled; 8822 ctx.bstate = BS_NONE; 8823 ctx.mem_idx = cpu_mmu_index(env, false); 8824 8825 tcg_clear_temp_count(); 8826 gen_tb_start(tb); 8827 while (ctx.bstate == BS_NONE) { 8828 tcg_gen_insn_start(ctx.pc); 8829 num_insns++; 8830 8831 ctx.opcode = cpu_ldl_code(env, ctx.pc); 8832 decode_opc(env, &ctx, 0); 8833 8834 if (num_insns >= max_insns || tcg_op_buf_full()) { 8835 gen_save_pc(ctx.next_pc); 8836 tcg_gen_exit_tb(NULL, 0); 8837 break; 8838 } 8839 ctx.pc = ctx.next_pc; 8840 } 8841 8842 gen_tb_end(tb, num_insns); 8843 tb->size = ctx.pc - pc_start; 8844 tb->icount = num_insns; 8845 8846 if (tcg_check_temp_count()) { 8847 printf("LEAK at %08x\n", env->PC); 8848 } 8849 8850 #ifdef DEBUG_DISAS 8851 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 8852 && qemu_log_in_addr_range(pc_start)) { 8853 qemu_log_lock(); 8854 qemu_log("IN: %s\n", lookup_symbol(pc_start)); 8855 log_target_disas(cs, pc_start, ctx.pc - pc_start); 8856 qemu_log("\n"); 8857 qemu_log_unlock(); 8858 } 8859 #endif 8860 } 8861 8862 void 8863 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, 8864 target_ulong *data) 8865 { 8866 env->PC = data[0]; 8867 } 8868 /* 8869 * 8870 * Initialization 8871 * 8872 */ 8873 8874 void cpu_state_reset(CPUTriCoreState *env) 8875 { 8876 /* Reset Regs to Default Value */ 8877 env->PSW = 0xb80; 8878 fpu_set_state(env); 8879 } 8880 8881 static void tricore_tcg_init_csfr(void) 8882 { 8883 cpu_PCXI = tcg_global_mem_new(cpu_env, 8884 offsetof(CPUTriCoreState, PCXI), "PCXI"); 8885 cpu_PSW = tcg_global_mem_new(cpu_env, 8886 offsetof(CPUTriCoreState, PSW), "PSW"); 8887 cpu_PC = tcg_global_mem_new(cpu_env, 8888 offsetof(CPUTriCoreState, PC), "PC"); 8889 cpu_ICR = tcg_global_mem_new(cpu_env, 8890 offsetof(CPUTriCoreState, ICR), "ICR"); 8891 } 8892 8893 void tricore_tcg_init(void) 8894 { 8895 int i; 8896 8897 /* reg init */ 8898 for (i = 0 ; i < 16 ; i++) { 8899 cpu_gpr_a[i] = tcg_global_mem_new(cpu_env, 8900 offsetof(CPUTriCoreState, gpr_a[i]), 8901 regnames_a[i]); 8902 } 8903 for (i = 0 ; i < 16 ; i++) { 8904 cpu_gpr_d[i] = tcg_global_mem_new(cpu_env, 8905 offsetof(CPUTriCoreState, gpr_d[i]), 8906 regnames_d[i]); 8907 } 8908 tricore_tcg_init_csfr(); 8909 /* init PSW flag cache */ 8910 cpu_PSW_C = tcg_global_mem_new(cpu_env, 8911 offsetof(CPUTriCoreState, PSW_USB_C), 8912 "PSW_C"); 8913 cpu_PSW_V = tcg_global_mem_new(cpu_env, 8914 offsetof(CPUTriCoreState, PSW_USB_V), 8915 "PSW_V"); 8916 cpu_PSW_SV = tcg_global_mem_new(cpu_env, 8917 offsetof(CPUTriCoreState, PSW_USB_SV), 8918 "PSW_SV"); 8919 cpu_PSW_AV = tcg_global_mem_new(cpu_env, 8920 offsetof(CPUTriCoreState, PSW_USB_AV), 8921 "PSW_AV"); 8922 cpu_PSW_SAV = tcg_global_mem_new(cpu_env, 8923 offsetof(CPUTriCoreState, PSW_USB_SAV), 8924 "PSW_SAV"); 8925 } 8926