xref: /qemu/target/xtensa/core-dc232b.c (revision fcf5ef2a)
1*fcf5ef2aSThomas Huth /*
2*fcf5ef2aSThomas Huth  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3*fcf5ef2aSThomas Huth  * All rights reserved.
4*fcf5ef2aSThomas Huth  *
5*fcf5ef2aSThomas Huth  * Redistribution and use in source and binary forms, with or without
6*fcf5ef2aSThomas Huth  * modification, are permitted provided that the following conditions are met:
7*fcf5ef2aSThomas Huth  *     * Redistributions of source code must retain the above copyright
8*fcf5ef2aSThomas Huth  *       notice, this list of conditions and the following disclaimer.
9*fcf5ef2aSThomas Huth  *     * Redistributions in binary form must reproduce the above copyright
10*fcf5ef2aSThomas Huth  *       notice, this list of conditions and the following disclaimer in the
11*fcf5ef2aSThomas Huth  *       documentation and/or other materials provided with the distribution.
12*fcf5ef2aSThomas Huth  *     * Neither the name of the Open Source and Linux Lab nor the
13*fcf5ef2aSThomas Huth  *       names of its contributors may be used to endorse or promote products
14*fcf5ef2aSThomas Huth  *       derived from this software without specific prior written permission.
15*fcf5ef2aSThomas Huth  *
16*fcf5ef2aSThomas Huth  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17*fcf5ef2aSThomas Huth  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18*fcf5ef2aSThomas Huth  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19*fcf5ef2aSThomas Huth  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20*fcf5ef2aSThomas Huth  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21*fcf5ef2aSThomas Huth  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22*fcf5ef2aSThomas Huth  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23*fcf5ef2aSThomas Huth  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24*fcf5ef2aSThomas Huth  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25*fcf5ef2aSThomas Huth  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26*fcf5ef2aSThomas Huth  */
27*fcf5ef2aSThomas Huth 
28*fcf5ef2aSThomas Huth #include "qemu/osdep.h"
29*fcf5ef2aSThomas Huth #include "cpu.h"
30*fcf5ef2aSThomas Huth #include "exec/exec-all.h"
31*fcf5ef2aSThomas Huth #include "exec/gdbstub.h"
32*fcf5ef2aSThomas Huth #include "qemu/host-utils.h"
33*fcf5ef2aSThomas Huth 
34*fcf5ef2aSThomas Huth #include "core-dc232b/core-isa.h"
35*fcf5ef2aSThomas Huth #include "overlay_tool.h"
36*fcf5ef2aSThomas Huth 
37*fcf5ef2aSThomas Huth static XtensaConfig dc232b __attribute__((unused)) = {
38*fcf5ef2aSThomas Huth     .name = "dc232b",
39*fcf5ef2aSThomas Huth     .gdb_regmap = {
40*fcf5ef2aSThomas Huth         .num_regs = 120,
41*fcf5ef2aSThomas Huth         .num_core_regs = 52,
42*fcf5ef2aSThomas Huth         .reg = {
43*fcf5ef2aSThomas Huth #include "core-dc232b/gdb-config.c"
44*fcf5ef2aSThomas Huth         }
45*fcf5ef2aSThomas Huth     },
46*fcf5ef2aSThomas Huth     .clock_freq_khz = 10000,
47*fcf5ef2aSThomas Huth     DEFAULT_SECTIONS
48*fcf5ef2aSThomas Huth };
49*fcf5ef2aSThomas Huth 
50*fcf5ef2aSThomas Huth REGISTER_CORE(dc232b)
51