1*fcf5ef2aSThomas Huth /* 2*fcf5ef2aSThomas Huth * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 3*fcf5ef2aSThomas Huth * processor CORE configuration 4*fcf5ef2aSThomas Huth * 5*fcf5ef2aSThomas Huth * See <xtensa/config/core.h>, which includes this file, for more details. 6*fcf5ef2aSThomas Huth */ 7*fcf5ef2aSThomas Huth 8*fcf5ef2aSThomas Huth /* Xtensa processor core configuration information. 9*fcf5ef2aSThomas Huth 10*fcf5ef2aSThomas Huth Copyright (c) 1999-2010 Tensilica Inc. 11*fcf5ef2aSThomas Huth 12*fcf5ef2aSThomas Huth Permission is hereby granted, free of charge, to any person obtaining 13*fcf5ef2aSThomas Huth a copy of this software and associated documentation files (the 14*fcf5ef2aSThomas Huth "Software"), to deal in the Software without restriction, including 15*fcf5ef2aSThomas Huth without limitation the rights to use, copy, modify, merge, publish, 16*fcf5ef2aSThomas Huth distribute, sublicense, and/or sell copies of the Software, and to 17*fcf5ef2aSThomas Huth permit persons to whom the Software is furnished to do so, subject to 18*fcf5ef2aSThomas Huth the following conditions: 19*fcf5ef2aSThomas Huth 20*fcf5ef2aSThomas Huth The above copyright notice and this permission notice shall be included 21*fcf5ef2aSThomas Huth in all copies or substantial portions of the Software. 22*fcf5ef2aSThomas Huth 23*fcf5ef2aSThomas Huth THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24*fcf5ef2aSThomas Huth EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25*fcf5ef2aSThomas Huth MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 26*fcf5ef2aSThomas Huth IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 27*fcf5ef2aSThomas Huth CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28*fcf5ef2aSThomas Huth TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29*fcf5ef2aSThomas Huth SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 30*fcf5ef2aSThomas Huth 31*fcf5ef2aSThomas Huth #ifndef XTENSA_DC233C_CORE_ISA_H 32*fcf5ef2aSThomas Huth #define XTENSA_DC233C_CORE_ISA_H 33*fcf5ef2aSThomas Huth 34*fcf5ef2aSThomas Huth /**************************************************************************** 35*fcf5ef2aSThomas Huth Parameters Useful for Any Code, USER or PRIVILEGED 36*fcf5ef2aSThomas Huth ****************************************************************************/ 37*fcf5ef2aSThomas Huth 38*fcf5ef2aSThomas Huth /* 39*fcf5ef2aSThomas Huth * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 40*fcf5ef2aSThomas Huth * configured, and a value of 0 otherwise. These macros are always defined. 41*fcf5ef2aSThomas Huth */ 42*fcf5ef2aSThomas Huth 43*fcf5ef2aSThomas Huth 44*fcf5ef2aSThomas Huth /*---------------------------------------------------------------------- 45*fcf5ef2aSThomas Huth ISA 46*fcf5ef2aSThomas Huth ----------------------------------------------------------------------*/ 47*fcf5ef2aSThomas Huth 48*fcf5ef2aSThomas Huth #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 49*fcf5ef2aSThomas Huth #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 50*fcf5ef2aSThomas Huth #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 51*fcf5ef2aSThomas Huth #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 52*fcf5ef2aSThomas Huth #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ 53*fcf5ef2aSThomas Huth #define XCHAL_HAVE_DEBUG 1 /* debug option */ 54*fcf5ef2aSThomas Huth #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 55*fcf5ef2aSThomas Huth #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 56*fcf5ef2aSThomas Huth #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 57*fcf5ef2aSThomas Huth #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 58*fcf5ef2aSThomas Huth #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 59*fcf5ef2aSThomas Huth #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 60*fcf5ef2aSThomas Huth #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 61*fcf5ef2aSThomas Huth #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 62*fcf5ef2aSThomas Huth #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ 63*fcf5ef2aSThomas Huth #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 64*fcf5ef2aSThomas Huth #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 65*fcf5ef2aSThomas Huth #define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ 66*fcf5ef2aSThomas Huth #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 67*fcf5ef2aSThomas Huth #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 68*fcf5ef2aSThomas Huth #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 69*fcf5ef2aSThomas Huth #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 70*fcf5ef2aSThomas Huth #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 71*fcf5ef2aSThomas Huth #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 72*fcf5ef2aSThomas Huth /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 73*fcf5ef2aSThomas Huth /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 74*fcf5ef2aSThomas Huth #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 75*fcf5ef2aSThomas Huth #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 76*fcf5ef2aSThomas Huth #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 77*fcf5ef2aSThomas Huth #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 78*fcf5ef2aSThomas Huth #define XCHAL_NUM_CONTEXTS 1 /* */ 79*fcf5ef2aSThomas Huth #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 80*fcf5ef2aSThomas Huth #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 81*fcf5ef2aSThomas Huth #define XCHAL_HAVE_PRID 1 /* processor ID register */ 82*fcf5ef2aSThomas Huth #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 83*fcf5ef2aSThomas Huth #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 84*fcf5ef2aSThomas Huth #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 85*fcf5ef2aSThomas Huth #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 86*fcf5ef2aSThomas Huth #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ 87*fcf5ef2aSThomas Huth #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 88*fcf5ef2aSThomas Huth #define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ 89*fcf5ef2aSThomas Huth #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 90*fcf5ef2aSThomas Huth #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 91*fcf5ef2aSThomas Huth #define XCHAL_HAVE_FP 0 /* floating point pkg */ 92*fcf5ef2aSThomas Huth #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 93*fcf5ef2aSThomas Huth #define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ 94*fcf5ef2aSThomas Huth #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 95*fcf5ef2aSThomas Huth #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 96*fcf5ef2aSThomas Huth #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 97*fcf5ef2aSThomas Huth #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 98*fcf5ef2aSThomas Huth #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 99*fcf5ef2aSThomas Huth #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 100*fcf5ef2aSThomas Huth #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 101*fcf5ef2aSThomas Huth #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 102*fcf5ef2aSThomas Huth #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 103*fcf5ef2aSThomas Huth #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 104*fcf5ef2aSThomas Huth #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 105*fcf5ef2aSThomas Huth #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 106*fcf5ef2aSThomas Huth #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 107*fcf5ef2aSThomas Huth #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 108*fcf5ef2aSThomas Huth #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 109*fcf5ef2aSThomas Huth 110*fcf5ef2aSThomas Huth 111*fcf5ef2aSThomas Huth /*---------------------------------------------------------------------- 112*fcf5ef2aSThomas Huth MISC 113*fcf5ef2aSThomas Huth ----------------------------------------------------------------------*/ 114*fcf5ef2aSThomas Huth 115*fcf5ef2aSThomas Huth #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 116*fcf5ef2aSThomas Huth #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ 117*fcf5ef2aSThomas Huth #define XCHAL_DATA_WIDTH 4 /* data width in bytes */ 118*fcf5ef2aSThomas Huth /* In T1050, applies to selected core load and store instructions (see ISA): */ 119*fcf5ef2aSThomas Huth #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 120*fcf5ef2aSThomas Huth #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 121*fcf5ef2aSThomas Huth #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 122*fcf5ef2aSThomas Huth #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 123*fcf5ef2aSThomas Huth 124*fcf5ef2aSThomas Huth #define XCHAL_SW_VERSION 900001 /* sw version of this header */ 125*fcf5ef2aSThomas Huth 126*fcf5ef2aSThomas Huth #define XCHAL_CORE_ID "dc233c" /* alphanum core name 127*fcf5ef2aSThomas Huth (CoreID) set in the Xtensa 128*fcf5ef2aSThomas Huth Processor Generator */ 129*fcf5ef2aSThomas Huth 130*fcf5ef2aSThomas Huth #define XCHAL_CORE_DESCRIPTION "dc233c" 131*fcf5ef2aSThomas Huth #define XCHAL_BUILD_UNIQUE_ID 0x00004B21 /* 22-bit sw build ID */ 132*fcf5ef2aSThomas Huth 133*fcf5ef2aSThomas Huth /* 134*fcf5ef2aSThomas Huth * These definitions describe the hardware targeted by this software. 135*fcf5ef2aSThomas Huth */ 136*fcf5ef2aSThomas Huth #define XCHAL_HW_CONFIGID0 0xC56707FE /* ConfigID hi 32 bits*/ 137*fcf5ef2aSThomas Huth #define XCHAL_HW_CONFIGID1 0x14404B21 /* ConfigID lo 32 bits*/ 138*fcf5ef2aSThomas Huth #define XCHAL_HW_VERSION_NAME "LX4.0.1" /* full version name */ 139*fcf5ef2aSThomas Huth #define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */ 140*fcf5ef2aSThomas Huth #define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ 141*fcf5ef2aSThomas Huth #define XCHAL_HW_VERSION 240001 /* major*100+minor */ 142*fcf5ef2aSThomas Huth #define XCHAL_HW_REL_LX4 1 143*fcf5ef2aSThomas Huth #define XCHAL_HW_REL_LX4_0 1 144*fcf5ef2aSThomas Huth #define XCHAL_HW_REL_LX4_0_1 1 145*fcf5ef2aSThomas Huth #define XCHAL_HW_CONFIGID_RELIABLE 1 146*fcf5ef2aSThomas Huth /* If software targets a *range* of hardware versions, these are the bounds: */ 147*fcf5ef2aSThomas Huth #define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */ 148*fcf5ef2aSThomas Huth #define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ 149*fcf5ef2aSThomas Huth #define XCHAL_HW_MIN_VERSION 240001 /* earliest targeted hw */ 150*fcf5ef2aSThomas Huth #define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */ 151*fcf5ef2aSThomas Huth #define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ 152*fcf5ef2aSThomas Huth #define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */ 153*fcf5ef2aSThomas Huth 154*fcf5ef2aSThomas Huth 155*fcf5ef2aSThomas Huth /*---------------------------------------------------------------------- 156*fcf5ef2aSThomas Huth CACHE 157*fcf5ef2aSThomas Huth ----------------------------------------------------------------------*/ 158*fcf5ef2aSThomas Huth 159*fcf5ef2aSThomas Huth #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ 160*fcf5ef2aSThomas Huth #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ 161*fcf5ef2aSThomas Huth #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ 162*fcf5ef2aSThomas Huth #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ 163*fcf5ef2aSThomas Huth 164*fcf5ef2aSThomas Huth #define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ 165*fcf5ef2aSThomas Huth #define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ 166*fcf5ef2aSThomas Huth 167*fcf5ef2aSThomas Huth #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 168*fcf5ef2aSThomas Huth #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 169*fcf5ef2aSThomas Huth 170*fcf5ef2aSThomas Huth #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 171*fcf5ef2aSThomas Huth 172*fcf5ef2aSThomas Huth 173*fcf5ef2aSThomas Huth 174*fcf5ef2aSThomas Huth 175*fcf5ef2aSThomas Huth /**************************************************************************** 176*fcf5ef2aSThomas Huth Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 177*fcf5ef2aSThomas Huth ****************************************************************************/ 178*fcf5ef2aSThomas Huth 179*fcf5ef2aSThomas Huth 180*fcf5ef2aSThomas Huth #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 181*fcf5ef2aSThomas Huth 182*fcf5ef2aSThomas Huth /*---------------------------------------------------------------------- 183*fcf5ef2aSThomas Huth CACHE 184*fcf5ef2aSThomas Huth ----------------------------------------------------------------------*/ 185*fcf5ef2aSThomas Huth 186*fcf5ef2aSThomas Huth #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 187*fcf5ef2aSThomas Huth 188*fcf5ef2aSThomas Huth /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 189*fcf5ef2aSThomas Huth 190*fcf5ef2aSThomas Huth /* Number of cache sets in log2(lines per way): */ 191*fcf5ef2aSThomas Huth #define XCHAL_ICACHE_SETWIDTH 7 192*fcf5ef2aSThomas Huth #define XCHAL_DCACHE_SETWIDTH 7 193*fcf5ef2aSThomas Huth 194*fcf5ef2aSThomas Huth /* Cache set associativity (number of ways): */ 195*fcf5ef2aSThomas Huth #define XCHAL_ICACHE_WAYS 4 196*fcf5ef2aSThomas Huth #define XCHAL_DCACHE_WAYS 4 197*fcf5ef2aSThomas Huth 198*fcf5ef2aSThomas Huth /* Cache features: */ 199*fcf5ef2aSThomas Huth #define XCHAL_ICACHE_LINE_LOCKABLE 1 200*fcf5ef2aSThomas Huth #define XCHAL_DCACHE_LINE_LOCKABLE 1 201*fcf5ef2aSThomas Huth #define XCHAL_ICACHE_ECC_PARITY 0 202*fcf5ef2aSThomas Huth #define XCHAL_DCACHE_ECC_PARITY 0 203*fcf5ef2aSThomas Huth 204*fcf5ef2aSThomas Huth /* Cache access size in bytes (affects operation of SICW instruction): */ 205*fcf5ef2aSThomas Huth #define XCHAL_ICACHE_ACCESS_SIZE 4 206*fcf5ef2aSThomas Huth #define XCHAL_DCACHE_ACCESS_SIZE 4 207*fcf5ef2aSThomas Huth 208*fcf5ef2aSThomas Huth /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 209*fcf5ef2aSThomas Huth #define XCHAL_CA_BITS 4 210*fcf5ef2aSThomas Huth 211*fcf5ef2aSThomas Huth 212*fcf5ef2aSThomas Huth /*---------------------------------------------------------------------- 213*fcf5ef2aSThomas Huth INTERNAL I/D RAM/ROMs and XLMI 214*fcf5ef2aSThomas Huth ----------------------------------------------------------------------*/ 215*fcf5ef2aSThomas Huth 216*fcf5ef2aSThomas Huth #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 217*fcf5ef2aSThomas Huth #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ 218*fcf5ef2aSThomas Huth #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 219*fcf5ef2aSThomas Huth #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ 220*fcf5ef2aSThomas Huth #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 221*fcf5ef2aSThomas Huth #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ 222*fcf5ef2aSThomas Huth 223*fcf5ef2aSThomas Huth #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 224*fcf5ef2aSThomas Huth 225*fcf5ef2aSThomas Huth 226*fcf5ef2aSThomas Huth /*---------------------------------------------------------------------- 227*fcf5ef2aSThomas Huth INTERRUPTS and TIMERS 228*fcf5ef2aSThomas Huth ----------------------------------------------------------------------*/ 229*fcf5ef2aSThomas Huth 230*fcf5ef2aSThomas Huth #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 231*fcf5ef2aSThomas Huth #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 232*fcf5ef2aSThomas Huth #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 233*fcf5ef2aSThomas Huth #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 234*fcf5ef2aSThomas Huth #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 235*fcf5ef2aSThomas Huth #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ 236*fcf5ef2aSThomas Huth #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 237*fcf5ef2aSThomas Huth #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ 238*fcf5ef2aSThomas Huth #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 239*fcf5ef2aSThomas Huth (not including level zero) */ 240*fcf5ef2aSThomas Huth #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 241*fcf5ef2aSThomas Huth /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 242*fcf5ef2aSThomas Huth 243*fcf5ef2aSThomas Huth /* Masks of interrupts at each interrupt level: */ 244*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL1_MASK 0x001F80FF 245*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL2_MASK 0x00000100 246*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL3_MASK 0x00200E00 247*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL4_MASK 0x00001000 248*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL5_MASK 0x00002000 249*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL6_MASK 0x00000000 250*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL7_MASK 0x00004000 251*fcf5ef2aSThomas Huth 252*fcf5ef2aSThomas Huth /* Masks of interrupts at each range 1..n of interrupt levels: */ 253*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF 254*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF 255*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF 256*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF 257*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF 258*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF 259*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF 260*fcf5ef2aSThomas Huth 261*fcf5ef2aSThomas Huth /* Level of each interrupt: */ 262*fcf5ef2aSThomas Huth #define XCHAL_INT0_LEVEL 1 263*fcf5ef2aSThomas Huth #define XCHAL_INT1_LEVEL 1 264*fcf5ef2aSThomas Huth #define XCHAL_INT2_LEVEL 1 265*fcf5ef2aSThomas Huth #define XCHAL_INT3_LEVEL 1 266*fcf5ef2aSThomas Huth #define XCHAL_INT4_LEVEL 1 267*fcf5ef2aSThomas Huth #define XCHAL_INT5_LEVEL 1 268*fcf5ef2aSThomas Huth #define XCHAL_INT6_LEVEL 1 269*fcf5ef2aSThomas Huth #define XCHAL_INT7_LEVEL 1 270*fcf5ef2aSThomas Huth #define XCHAL_INT8_LEVEL 2 271*fcf5ef2aSThomas Huth #define XCHAL_INT9_LEVEL 3 272*fcf5ef2aSThomas Huth #define XCHAL_INT10_LEVEL 3 273*fcf5ef2aSThomas Huth #define XCHAL_INT11_LEVEL 3 274*fcf5ef2aSThomas Huth #define XCHAL_INT12_LEVEL 4 275*fcf5ef2aSThomas Huth #define XCHAL_INT13_LEVEL 5 276*fcf5ef2aSThomas Huth #define XCHAL_INT14_LEVEL 7 277*fcf5ef2aSThomas Huth #define XCHAL_INT15_LEVEL 1 278*fcf5ef2aSThomas Huth #define XCHAL_INT16_LEVEL 1 279*fcf5ef2aSThomas Huth #define XCHAL_INT17_LEVEL 1 280*fcf5ef2aSThomas Huth #define XCHAL_INT18_LEVEL 1 281*fcf5ef2aSThomas Huth #define XCHAL_INT19_LEVEL 1 282*fcf5ef2aSThomas Huth #define XCHAL_INT20_LEVEL 1 283*fcf5ef2aSThomas Huth #define XCHAL_INT21_LEVEL 3 284*fcf5ef2aSThomas Huth #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 285*fcf5ef2aSThomas Huth #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 286*fcf5ef2aSThomas Huth #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 287*fcf5ef2aSThomas Huth EXCSAVE/EPS/EPC_n, RFI n) */ 288*fcf5ef2aSThomas Huth 289*fcf5ef2aSThomas Huth /* Type of each interrupt: */ 290*fcf5ef2aSThomas Huth #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 291*fcf5ef2aSThomas Huth #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 292*fcf5ef2aSThomas Huth #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 293*fcf5ef2aSThomas Huth #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 294*fcf5ef2aSThomas Huth #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 295*fcf5ef2aSThomas Huth #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 296*fcf5ef2aSThomas Huth #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 297*fcf5ef2aSThomas Huth #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 298*fcf5ef2aSThomas Huth #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 299*fcf5ef2aSThomas Huth #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 300*fcf5ef2aSThomas Huth #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER 301*fcf5ef2aSThomas Huth #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE 302*fcf5ef2aSThomas Huth #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 303*fcf5ef2aSThomas Huth #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER 304*fcf5ef2aSThomas Huth #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 305*fcf5ef2aSThomas Huth #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE 306*fcf5ef2aSThomas Huth #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE 307*fcf5ef2aSThomas Huth #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE 308*fcf5ef2aSThomas Huth #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE 309*fcf5ef2aSThomas Huth #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE 310*fcf5ef2aSThomas Huth #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE 311*fcf5ef2aSThomas Huth #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE 312*fcf5ef2aSThomas Huth 313*fcf5ef2aSThomas Huth /* Masks of interrupts for each type of interrupt: */ 314*fcf5ef2aSThomas Huth #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 315*fcf5ef2aSThomas Huth #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 316*fcf5ef2aSThomas Huth #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 317*fcf5ef2aSThomas Huth #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F 318*fcf5ef2aSThomas Huth #define XCHAL_INTTYPE_MASK_TIMER 0x00002440 319*fcf5ef2aSThomas Huth #define XCHAL_INTTYPE_MASK_NMI 0x00004000 320*fcf5ef2aSThomas Huth #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 321*fcf5ef2aSThomas Huth 322*fcf5ef2aSThomas Huth /* Interrupt numbers assigned to specific interrupt sources: */ 323*fcf5ef2aSThomas Huth #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 324*fcf5ef2aSThomas Huth #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ 325*fcf5ef2aSThomas Huth #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ 326*fcf5ef2aSThomas Huth #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 327*fcf5ef2aSThomas Huth #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 328*fcf5ef2aSThomas Huth 329*fcf5ef2aSThomas Huth /* Interrupt numbers for levels at which only one interrupt is configured: */ 330*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL2_NUM 8 331*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL4_NUM 12 332*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL5_NUM 13 333*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL7_NUM 14 334*fcf5ef2aSThomas Huth /* (There are many interrupts each at level(s) 1, 3.) */ 335*fcf5ef2aSThomas Huth 336*fcf5ef2aSThomas Huth 337*fcf5ef2aSThomas Huth /* 338*fcf5ef2aSThomas Huth * External interrupt vectors/levels. 339*fcf5ef2aSThomas Huth * These macros describe how Xtensa processor interrupt numbers 340*fcf5ef2aSThomas Huth * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 341*fcf5ef2aSThomas Huth * map to external BInterrupt<n> pins, for those interrupts 342*fcf5ef2aSThomas Huth * configured as external (level-triggered, edge-triggered, or NMI). 343*fcf5ef2aSThomas Huth * See the Xtensa processor databook for more details. 344*fcf5ef2aSThomas Huth */ 345*fcf5ef2aSThomas Huth 346*fcf5ef2aSThomas Huth /* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ 347*fcf5ef2aSThomas Huth #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 348*fcf5ef2aSThomas Huth #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 349*fcf5ef2aSThomas Huth #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 350*fcf5ef2aSThomas Huth #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 351*fcf5ef2aSThomas Huth #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 352*fcf5ef2aSThomas Huth #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 353*fcf5ef2aSThomas Huth #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ 354*fcf5ef2aSThomas Huth #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ 355*fcf5ef2aSThomas Huth #define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ 356*fcf5ef2aSThomas Huth #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ 357*fcf5ef2aSThomas Huth #define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ 358*fcf5ef2aSThomas Huth #define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ 359*fcf5ef2aSThomas Huth #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ 360*fcf5ef2aSThomas Huth #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ 361*fcf5ef2aSThomas Huth #define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ 362*fcf5ef2aSThomas Huth #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ 363*fcf5ef2aSThomas Huth #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ 364*fcf5ef2aSThomas Huth 365*fcf5ef2aSThomas Huth 366*fcf5ef2aSThomas Huth /*---------------------------------------------------------------------- 367*fcf5ef2aSThomas Huth EXCEPTIONS and VECTORS 368*fcf5ef2aSThomas Huth ----------------------------------------------------------------------*/ 369*fcf5ef2aSThomas Huth 370*fcf5ef2aSThomas Huth #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 371*fcf5ef2aSThomas Huth number: 1 == XEA1 (old) 372*fcf5ef2aSThomas Huth 2 == XEA2 (new) 373*fcf5ef2aSThomas Huth 0 == XEAX (extern) or TX */ 374*fcf5ef2aSThomas Huth #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 375*fcf5ef2aSThomas Huth #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 376*fcf5ef2aSThomas Huth #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 377*fcf5ef2aSThomas Huth #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 378*fcf5ef2aSThomas Huth #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 379*fcf5ef2aSThomas Huth #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 380*fcf5ef2aSThomas Huth #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 381*fcf5ef2aSThomas Huth #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 382*fcf5ef2aSThomas Huth #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 383*fcf5ef2aSThomas Huth #define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ 384*fcf5ef2aSThomas Huth #define XCHAL_VECBASE_RESET_PADDR 0x00002000 385*fcf5ef2aSThomas Huth #define XCHAL_RESET_VECBASE_OVERLAP 0 386*fcf5ef2aSThomas Huth 387*fcf5ef2aSThomas Huth #define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 388*fcf5ef2aSThomas Huth #define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 389*fcf5ef2aSThomas Huth #define XCHAL_RESET_VECTOR1_VADDR 0x00001000 390*fcf5ef2aSThomas Huth #define XCHAL_RESET_VECTOR1_PADDR 0x00001000 391*fcf5ef2aSThomas Huth #define XCHAL_RESET_VECTOR_VADDR 0xFE000000 392*fcf5ef2aSThomas Huth #define XCHAL_RESET_VECTOR_PADDR 0xFE000000 393*fcf5ef2aSThomas Huth #define XCHAL_USER_VECOFS 0x00000340 394*fcf5ef2aSThomas Huth #define XCHAL_USER_VECTOR_VADDR 0x00002340 395*fcf5ef2aSThomas Huth #define XCHAL_USER_VECTOR_PADDR 0x00002340 396*fcf5ef2aSThomas Huth #define XCHAL_KERNEL_VECOFS 0x00000300 397*fcf5ef2aSThomas Huth #define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 398*fcf5ef2aSThomas Huth #define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 399*fcf5ef2aSThomas Huth #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 400*fcf5ef2aSThomas Huth #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 401*fcf5ef2aSThomas Huth #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 402*fcf5ef2aSThomas Huth #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 403*fcf5ef2aSThomas Huth #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 404*fcf5ef2aSThomas Huth #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 405*fcf5ef2aSThomas Huth #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 406*fcf5ef2aSThomas Huth #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 407*fcf5ef2aSThomas Huth #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 408*fcf5ef2aSThomas Huth #define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 409*fcf5ef2aSThomas Huth #define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 410*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL2_VECOFS 0x00000180 411*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 412*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 413*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 414*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 415*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 416*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL4_VECOFS 0x00000200 417*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 418*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 419*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL5_VECOFS 0x00000240 420*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 421*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 422*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL6_VECOFS 0x00000280 423*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 424*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 425*fcf5ef2aSThomas Huth #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 426*fcf5ef2aSThomas Huth #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 427*fcf5ef2aSThomas Huth #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 428*fcf5ef2aSThomas Huth #define XCHAL_NMI_VECOFS 0x000002C0 429*fcf5ef2aSThomas Huth #define XCHAL_NMI_VECTOR_VADDR 0x000022C0 430*fcf5ef2aSThomas Huth #define XCHAL_NMI_VECTOR_PADDR 0x000022C0 431*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 432*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 433*fcf5ef2aSThomas Huth #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 434*fcf5ef2aSThomas Huth 435*fcf5ef2aSThomas Huth 436*fcf5ef2aSThomas Huth /*---------------------------------------------------------------------- 437*fcf5ef2aSThomas Huth DEBUG 438*fcf5ef2aSThomas Huth ----------------------------------------------------------------------*/ 439*fcf5ef2aSThomas Huth 440*fcf5ef2aSThomas Huth #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 441*fcf5ef2aSThomas Huth #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 442*fcf5ef2aSThomas Huth #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 443*fcf5ef2aSThomas Huth #define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ 444*fcf5ef2aSThomas Huth 445*fcf5ef2aSThomas Huth 446*fcf5ef2aSThomas Huth /*---------------------------------------------------------------------- 447*fcf5ef2aSThomas Huth MMU 448*fcf5ef2aSThomas Huth ----------------------------------------------------------------------*/ 449*fcf5ef2aSThomas Huth 450*fcf5ef2aSThomas Huth /* See core-matmap.h header file for more details. */ 451*fcf5ef2aSThomas Huth 452*fcf5ef2aSThomas Huth #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 453*fcf5ef2aSThomas Huth #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 454*fcf5ef2aSThomas Huth #define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ 455*fcf5ef2aSThomas Huth #define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ 456*fcf5ef2aSThomas Huth #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 457*fcf5ef2aSThomas Huth #define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ 458*fcf5ef2aSThomas Huth #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 459*fcf5ef2aSThomas Huth #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table 460*fcf5ef2aSThomas Huth [autorefill] and protection) 461*fcf5ef2aSThomas Huth usable for an MMU-based OS */ 462*fcf5ef2aSThomas Huth /* If none of the above last 4 are set, it's a custom TLB configuration. */ 463*fcf5ef2aSThomas Huth #define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 464*fcf5ef2aSThomas Huth #define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ 465*fcf5ef2aSThomas Huth 466*fcf5ef2aSThomas Huth #define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ 467*fcf5ef2aSThomas Huth #define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ 468*fcf5ef2aSThomas Huth #define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ 469*fcf5ef2aSThomas Huth 470*fcf5ef2aSThomas Huth #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 471*fcf5ef2aSThomas Huth 472*fcf5ef2aSThomas Huth 473*fcf5ef2aSThomas Huth #endif /* XTENSA_DC233C_CORE_ISA_H */ 474