17ddaee6dSMax Filippov /* 27ddaee6dSMax Filippov * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 37ddaee6dSMax Filippov * processor CORE configuration 47ddaee6dSMax Filippov * 57ddaee6dSMax Filippov * See <xtensa/config/core.h>, which includes this file, for more details. 67ddaee6dSMax Filippov */ 77ddaee6dSMax Filippov 87ddaee6dSMax Filippov /* Xtensa processor core configuration information. 97ddaee6dSMax Filippov 107ddaee6dSMax Filippov Copyright (c) 1999-2015 Tensilica Inc. 117ddaee6dSMax Filippov 127ddaee6dSMax Filippov Permission is hereby granted, free of charge, to any person obtaining 137ddaee6dSMax Filippov a copy of this software and associated documentation files (the 147ddaee6dSMax Filippov "Software"), to deal in the Software without restriction, including 157ddaee6dSMax Filippov without limitation the rights to use, copy, modify, merge, publish, 167ddaee6dSMax Filippov distribute, sublicense, and/or sell copies of the Software, and to 177ddaee6dSMax Filippov permit persons to whom the Software is furnished to do so, subject to 187ddaee6dSMax Filippov the following conditions: 197ddaee6dSMax Filippov 207ddaee6dSMax Filippov The above copyright notice and this permission notice shall be included 217ddaee6dSMax Filippov in all copies or substantial portions of the Software. 227ddaee6dSMax Filippov 237ddaee6dSMax Filippov THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 247ddaee6dSMax Filippov EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 257ddaee6dSMax Filippov MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 267ddaee6dSMax Filippov IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 277ddaee6dSMax Filippov CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 287ddaee6dSMax Filippov TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 297ddaee6dSMax Filippov SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 307ddaee6dSMax Filippov 31*81416747SMarkus Armbruster #ifndef XTENSA_CORE_DE212_CORE_ISA_H 32*81416747SMarkus Armbruster #define XTENSA_CORE_DE212_CORE_ISA_H 337ddaee6dSMax Filippov 347ddaee6dSMax Filippov /**************************************************************************** 357ddaee6dSMax Filippov Parameters Useful for Any Code, USER or PRIVILEGED 367ddaee6dSMax Filippov ****************************************************************************/ 377ddaee6dSMax Filippov 387ddaee6dSMax Filippov /* 397ddaee6dSMax Filippov * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 407ddaee6dSMax Filippov * configured, and a value of 0 otherwise. These macros are always defined. 417ddaee6dSMax Filippov */ 427ddaee6dSMax Filippov 437ddaee6dSMax Filippov 447ddaee6dSMax Filippov /*---------------------------------------------------------------------- 457ddaee6dSMax Filippov ISA 467ddaee6dSMax Filippov ----------------------------------------------------------------------*/ 477ddaee6dSMax Filippov 487ddaee6dSMax Filippov #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 497ddaee6dSMax Filippov #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 507ddaee6dSMax Filippov #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 517ddaee6dSMax Filippov #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 527ddaee6dSMax Filippov #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ 537ddaee6dSMax Filippov #define XCHAL_HAVE_DEBUG 1 /* debug option */ 547ddaee6dSMax Filippov #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 557ddaee6dSMax Filippov #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 567ddaee6dSMax Filippov #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 577ddaee6dSMax Filippov #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 587ddaee6dSMax Filippov #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 597ddaee6dSMax Filippov #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 607ddaee6dSMax Filippov #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ 617ddaee6dSMax Filippov #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 627ddaee6dSMax Filippov #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 637ddaee6dSMax Filippov #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 647ddaee6dSMax Filippov #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ 657ddaee6dSMax Filippov #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 667ddaee6dSMax Filippov #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 677ddaee6dSMax Filippov #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ 687ddaee6dSMax Filippov #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 697ddaee6dSMax Filippov #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 707ddaee6dSMax Filippov #define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */ 717ddaee6dSMax Filippov #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 727ddaee6dSMax Filippov #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 737ddaee6dSMax Filippov #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 747ddaee6dSMax Filippov #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 757ddaee6dSMax Filippov /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 767ddaee6dSMax Filippov /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 777ddaee6dSMax Filippov #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 787ddaee6dSMax Filippov #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 797ddaee6dSMax Filippov #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 807ddaee6dSMax Filippov #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 817ddaee6dSMax Filippov #define XCHAL_NUM_CONTEXTS 1 /* */ 827ddaee6dSMax Filippov #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 837ddaee6dSMax Filippov #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 847ddaee6dSMax Filippov #define XCHAL_HAVE_PRID 1 /* processor ID register */ 857ddaee6dSMax Filippov #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 867ddaee6dSMax Filippov #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ 877ddaee6dSMax Filippov #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 887ddaee6dSMax Filippov #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 897ddaee6dSMax Filippov #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ 907ddaee6dSMax Filippov #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ 917ddaee6dSMax Filippov #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ 927ddaee6dSMax Filippov #define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */ 937ddaee6dSMax Filippov #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ 947ddaee6dSMax Filippov #define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ 957ddaee6dSMax Filippov #define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */ 967ddaee6dSMax Filippov #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 977ddaee6dSMax Filippov 987ddaee6dSMax Filippov #define XCHAL_HAVE_FUSION 0 /* Fusion*/ 997ddaee6dSMax Filippov #define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ 1007ddaee6dSMax Filippov #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ 1017ddaee6dSMax Filippov #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ 1027ddaee6dSMax Filippov #define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ 1037ddaee6dSMax Filippov #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ 1047ddaee6dSMax Filippov #define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ 1057ddaee6dSMax Filippov #define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ 1067ddaee6dSMax Filippov #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ 1077ddaee6dSMax Filippov #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 1087ddaee6dSMax Filippov #define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ 1097ddaee6dSMax Filippov #define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ 1107ddaee6dSMax Filippov #define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ 1117ddaee6dSMax Filippov #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ 1127ddaee6dSMax Filippov #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 1137ddaee6dSMax Filippov #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 1147ddaee6dSMax Filippov #define XCHAL_HAVE_HIFI_MINI 0 1157ddaee6dSMax Filippov 1167ddaee6dSMax Filippov 1177ddaee6dSMax Filippov 1187ddaee6dSMax Filippov #define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ 1197ddaee6dSMax Filippov #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ 1207ddaee6dSMax Filippov #define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ 1217ddaee6dSMax Filippov #define XCHAL_HAVE_FP 0 /* single prec floating point */ 1227ddaee6dSMax Filippov #define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ 1237ddaee6dSMax Filippov #define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ 1247ddaee6dSMax Filippov #define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ 1257ddaee6dSMax Filippov #define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ 1267ddaee6dSMax Filippov #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 1277ddaee6dSMax Filippov #define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ 1287ddaee6dSMax Filippov #define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ 1297ddaee6dSMax Filippov #define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ 1307ddaee6dSMax Filippov #define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ 1317ddaee6dSMax Filippov #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ 1327ddaee6dSMax Filippov #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ 1337ddaee6dSMax Filippov 1347ddaee6dSMax Filippov #define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ 1357ddaee6dSMax Filippov #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ 1367ddaee6dSMax Filippov #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 1377ddaee6dSMax Filippov #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 1387ddaee6dSMax Filippov #define XCHAL_HAVE_PDX4 0 /* PDX4 */ 1397ddaee6dSMax Filippov #define XCHAL_HAVE_PDX8 0 /* PDX8 */ 1407ddaee6dSMax Filippov #define XCHAL_HAVE_PDX16 0 /* PDX16 */ 1417ddaee6dSMax Filippov #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 1427ddaee6dSMax Filippov #define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ 1437ddaee6dSMax Filippov #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 1447ddaee6dSMax Filippov #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 1457ddaee6dSMax Filippov #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 1467ddaee6dSMax Filippov #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 1477ddaee6dSMax Filippov #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ 1487ddaee6dSMax Filippov #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 1497ddaee6dSMax Filippov #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ 1507ddaee6dSMax Filippov #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 1517ddaee6dSMax Filippov #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 1527ddaee6dSMax Filippov #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 1537ddaee6dSMax Filippov #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 1547ddaee6dSMax Filippov #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ 1557ddaee6dSMax Filippov #define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */ 1567ddaee6dSMax Filippov #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ 1577ddaee6dSMax Filippov 1587ddaee6dSMax Filippov #define XCHAL_HAVE_VISION 0 /* Vision */ 1597ddaee6dSMax Filippov #define XCHAL_VISION_TYPE 0 /* Vision P5 or P3 */ 1607ddaee6dSMax Filippov #define XCHAL_VISION_SIMD16 0 /* Vision simd16 */ 1617ddaee6dSMax Filippov #define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision */ 1627ddaee6dSMax Filippov #define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision */ 1637ddaee6dSMax Filippov 1647ddaee6dSMax Filippov 1657ddaee6dSMax Filippov /*---------------------------------------------------------------------- 1667ddaee6dSMax Filippov MISC 1677ddaee6dSMax Filippov ----------------------------------------------------------------------*/ 1687ddaee6dSMax Filippov 1697ddaee6dSMax Filippov #define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ 1707ddaee6dSMax Filippov #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 1717ddaee6dSMax Filippov #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ 1727ddaee6dSMax Filippov #define XCHAL_DATA_WIDTH 4 /* data width in bytes */ 1737ddaee6dSMax Filippov #define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay 1747ddaee6dSMax Filippov (1 = 5-stage, 2 = 7-stage) */ 1757ddaee6dSMax Filippov #define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */ 1767ddaee6dSMax Filippov #define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */ 1777ddaee6dSMax Filippov /* In T1050, applies to selected core load and store instructions (see ISA): */ 1787ddaee6dSMax Filippov #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 1797ddaee6dSMax Filippov #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 1807ddaee6dSMax Filippov #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 1817ddaee6dSMax Filippov #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 1827ddaee6dSMax Filippov 1837ddaee6dSMax Filippov #define XCHAL_SW_VERSION 1200000 /* sw version of this header */ 1847ddaee6dSMax Filippov 1857ddaee6dSMax Filippov #define XCHAL_CORE_ID "de212_371077" /* alphanum core name 1867ddaee6dSMax Filippov (CoreID) set in the Xtensa 1877ddaee6dSMax Filippov Processor Generator */ 1887ddaee6dSMax Filippov 1897ddaee6dSMax Filippov #define XCHAL_BUILD_UNIQUE_ID 0x0005A9EB /* 22-bit sw build ID */ 1907ddaee6dSMax Filippov 1917ddaee6dSMax Filippov /* 1927ddaee6dSMax Filippov * These definitions describe the hardware targeted by this software. 1937ddaee6dSMax Filippov */ 1947ddaee6dSMax Filippov #define XCHAL_HW_CONFIGID0 0xC283DFFE /* ConfigID hi 32 bits*/ 1957ddaee6dSMax Filippov #define XCHAL_HW_CONFIGID1 0x1C85A985 /* ConfigID lo 32 bits*/ 1967ddaee6dSMax Filippov #define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */ 1977ddaee6dSMax Filippov #define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ 1987ddaee6dSMax Filippov #define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */ 1997ddaee6dSMax Filippov #define XCHAL_HW_VERSION 260002 /* major*100+minor */ 2007ddaee6dSMax Filippov #define XCHAL_HW_REL_LX6 1 2017ddaee6dSMax Filippov #define XCHAL_HW_REL_LX6_0 1 2027ddaee6dSMax Filippov #define XCHAL_HW_REL_LX6_0_2 1 2037ddaee6dSMax Filippov #define XCHAL_HW_CONFIGID_RELIABLE 1 2047ddaee6dSMax Filippov /* If software targets a *range* of hardware versions, these are the bounds: */ 2057ddaee6dSMax Filippov #define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ 2067ddaee6dSMax Filippov #define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */ 2077ddaee6dSMax Filippov #define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */ 2087ddaee6dSMax Filippov #define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ 2097ddaee6dSMax Filippov #define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ 2107ddaee6dSMax Filippov #define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */ 2117ddaee6dSMax Filippov 2127ddaee6dSMax Filippov 2137ddaee6dSMax Filippov /*---------------------------------------------------------------------- 2147ddaee6dSMax Filippov CACHE 2157ddaee6dSMax Filippov ----------------------------------------------------------------------*/ 2167ddaee6dSMax Filippov 2177ddaee6dSMax Filippov #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ 2187ddaee6dSMax Filippov #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ 2197ddaee6dSMax Filippov #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ 2207ddaee6dSMax Filippov #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ 2217ddaee6dSMax Filippov 2227ddaee6dSMax Filippov #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ 2237ddaee6dSMax Filippov #define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */ 2247ddaee6dSMax Filippov 2257ddaee6dSMax Filippov #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 2267ddaee6dSMax Filippov #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 2277ddaee6dSMax Filippov 2287ddaee6dSMax Filippov #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 2297ddaee6dSMax Filippov #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ 2307ddaee6dSMax Filippov #define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ 2317ddaee6dSMax Filippov #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ 2327ddaee6dSMax Filippov #define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ 2337ddaee6dSMax Filippov #define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ 2347ddaee6dSMax Filippov #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ 2357ddaee6dSMax Filippov #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ 2367ddaee6dSMax Filippov #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ 2377ddaee6dSMax Filippov #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ 2387ddaee6dSMax Filippov 2397ddaee6dSMax Filippov 2407ddaee6dSMax Filippov 2417ddaee6dSMax Filippov 2427ddaee6dSMax Filippov /**************************************************************************** 2437ddaee6dSMax Filippov Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 2447ddaee6dSMax Filippov ****************************************************************************/ 2457ddaee6dSMax Filippov 2467ddaee6dSMax Filippov 2477ddaee6dSMax Filippov #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 2487ddaee6dSMax Filippov 2497ddaee6dSMax Filippov /*---------------------------------------------------------------------- 2507ddaee6dSMax Filippov CACHE 2517ddaee6dSMax Filippov ----------------------------------------------------------------------*/ 2527ddaee6dSMax Filippov 2537ddaee6dSMax Filippov #define XCHAL_HAVE_PIF 1 /* any outbound bus present */ 2547ddaee6dSMax Filippov #define XCHAL_HAVE_AXI 0 /* AXI bus */ 2557ddaee6dSMax Filippov #define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */ 2567ddaee6dSMax Filippov #define XCHAL_HAVE_ACELITE 0 /* ACELite bus */ 2577ddaee6dSMax Filippov 2587ddaee6dSMax Filippov /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 2597ddaee6dSMax Filippov 2607ddaee6dSMax Filippov /* Number of cache sets in log2(lines per way): */ 2617ddaee6dSMax Filippov #define XCHAL_ICACHE_SETWIDTH 7 2627ddaee6dSMax Filippov #define XCHAL_DCACHE_SETWIDTH 7 2637ddaee6dSMax Filippov 2647ddaee6dSMax Filippov /* Cache set associativity (number of ways): */ 2657ddaee6dSMax Filippov #define XCHAL_ICACHE_WAYS 2 2667ddaee6dSMax Filippov #define XCHAL_DCACHE_WAYS 2 2677ddaee6dSMax Filippov 2687ddaee6dSMax Filippov /* Cache features: */ 2697ddaee6dSMax Filippov #define XCHAL_ICACHE_LINE_LOCKABLE 1 2707ddaee6dSMax Filippov #define XCHAL_DCACHE_LINE_LOCKABLE 1 2717ddaee6dSMax Filippov #define XCHAL_ICACHE_ECC_PARITY 0 2727ddaee6dSMax Filippov #define XCHAL_DCACHE_ECC_PARITY 0 2737ddaee6dSMax Filippov 2747ddaee6dSMax Filippov /* Cache access size in bytes (affects operation of SICW instruction): */ 2757ddaee6dSMax Filippov #define XCHAL_ICACHE_ACCESS_SIZE 4 2767ddaee6dSMax Filippov #define XCHAL_DCACHE_ACCESS_SIZE 4 2777ddaee6dSMax Filippov 2787ddaee6dSMax Filippov #define XCHAL_DCACHE_BANKS 1 /* number of banks */ 2797ddaee6dSMax Filippov 2807ddaee6dSMax Filippov /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 2817ddaee6dSMax Filippov #define XCHAL_CA_BITS 4 2827ddaee6dSMax Filippov 2837ddaee6dSMax Filippov 2847ddaee6dSMax Filippov /*---------------------------------------------------------------------- 2857ddaee6dSMax Filippov INTERNAL I/D RAM/ROMs and XLMI 2867ddaee6dSMax Filippov ----------------------------------------------------------------------*/ 2877ddaee6dSMax Filippov #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 2887ddaee6dSMax Filippov #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ 2897ddaee6dSMax Filippov #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 2907ddaee6dSMax Filippov #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ 2917ddaee6dSMax Filippov #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 2927ddaee6dSMax Filippov #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ 2937ddaee6dSMax Filippov 2947ddaee6dSMax Filippov /* Instruction RAM 0: */ 2957ddaee6dSMax Filippov #define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ 2967ddaee6dSMax Filippov #define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ 2977ddaee6dSMax Filippov #define XCHAL_INSTRAM0_SIZE 131072 /* size in bytes */ 2987ddaee6dSMax Filippov #define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 2997ddaee6dSMax Filippov #define XCHAL_HAVE_INSTRAM0 3007ddaee6dSMax Filippov #define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */ 3017ddaee6dSMax Filippov 3027ddaee6dSMax Filippov /* Data RAM 0: */ 3037ddaee6dSMax Filippov #define XCHAL_DATARAM0_VADDR 0x3FFE0000 /* virtual address */ 3047ddaee6dSMax Filippov #define XCHAL_DATARAM0_PADDR 0x3FFE0000 /* physical address */ 3057ddaee6dSMax Filippov #define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */ 3067ddaee6dSMax Filippov #define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 3077ddaee6dSMax Filippov #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ 3087ddaee6dSMax Filippov #define XCHAL_HAVE_DATARAM0 3097ddaee6dSMax Filippov #define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */ 3107ddaee6dSMax Filippov 3117ddaee6dSMax Filippov /* XLMI Port 0: */ 3127ddaee6dSMax Filippov #define XCHAL_XLMI0_VADDR 0x3FFC0000 /* virtual address */ 3137ddaee6dSMax Filippov #define XCHAL_XLMI0_PADDR 0x3FFC0000 /* physical address */ 3147ddaee6dSMax Filippov #define XCHAL_XLMI0_SIZE 131072 /* size in bytes */ 3157ddaee6dSMax Filippov #define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 3167ddaee6dSMax Filippov 3177ddaee6dSMax Filippov #define XCHAL_HAVE_IDMA 0 3187ddaee6dSMax Filippov #define XCHAL_HAVE_IDMA_TRANSPOSE 0 3197ddaee6dSMax Filippov 3207ddaee6dSMax Filippov #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 3217ddaee6dSMax Filippov 3227ddaee6dSMax Filippov 3237ddaee6dSMax Filippov /*---------------------------------------------------------------------- 3247ddaee6dSMax Filippov INTERRUPTS and TIMERS 3257ddaee6dSMax Filippov ----------------------------------------------------------------------*/ 3267ddaee6dSMax Filippov 3277ddaee6dSMax Filippov #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 3287ddaee6dSMax Filippov #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 3297ddaee6dSMax Filippov #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 3307ddaee6dSMax Filippov #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 3317ddaee6dSMax Filippov #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 3327ddaee6dSMax Filippov #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ 3337ddaee6dSMax Filippov #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 3347ddaee6dSMax Filippov #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ 3357ddaee6dSMax Filippov #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 3367ddaee6dSMax Filippov (not including level zero) */ 3377ddaee6dSMax Filippov #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 3387ddaee6dSMax Filippov /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 3397ddaee6dSMax Filippov 3407ddaee6dSMax Filippov /* Masks of interrupts at each interrupt level: */ 3417ddaee6dSMax Filippov #define XCHAL_INTLEVEL1_MASK 0x001F80FF 3427ddaee6dSMax Filippov #define XCHAL_INTLEVEL2_MASK 0x00000100 3437ddaee6dSMax Filippov #define XCHAL_INTLEVEL3_MASK 0x00200E00 3447ddaee6dSMax Filippov #define XCHAL_INTLEVEL4_MASK 0x00001000 3457ddaee6dSMax Filippov #define XCHAL_INTLEVEL5_MASK 0x00002000 3467ddaee6dSMax Filippov #define XCHAL_INTLEVEL6_MASK 0x00000000 3477ddaee6dSMax Filippov #define XCHAL_INTLEVEL7_MASK 0x00004000 3487ddaee6dSMax Filippov 3497ddaee6dSMax Filippov /* Masks of interrupts at each range 1..n of interrupt levels: */ 3507ddaee6dSMax Filippov #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF 3517ddaee6dSMax Filippov #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF 3527ddaee6dSMax Filippov #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF 3537ddaee6dSMax Filippov #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF 3547ddaee6dSMax Filippov #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF 3557ddaee6dSMax Filippov #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF 3567ddaee6dSMax Filippov #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF 3577ddaee6dSMax Filippov 3587ddaee6dSMax Filippov /* Level of each interrupt: */ 3597ddaee6dSMax Filippov #define XCHAL_INT0_LEVEL 1 3607ddaee6dSMax Filippov #define XCHAL_INT1_LEVEL 1 3617ddaee6dSMax Filippov #define XCHAL_INT2_LEVEL 1 3627ddaee6dSMax Filippov #define XCHAL_INT3_LEVEL 1 3637ddaee6dSMax Filippov #define XCHAL_INT4_LEVEL 1 3647ddaee6dSMax Filippov #define XCHAL_INT5_LEVEL 1 3657ddaee6dSMax Filippov #define XCHAL_INT6_LEVEL 1 3667ddaee6dSMax Filippov #define XCHAL_INT7_LEVEL 1 3677ddaee6dSMax Filippov #define XCHAL_INT8_LEVEL 2 3687ddaee6dSMax Filippov #define XCHAL_INT9_LEVEL 3 3697ddaee6dSMax Filippov #define XCHAL_INT10_LEVEL 3 3707ddaee6dSMax Filippov #define XCHAL_INT11_LEVEL 3 3717ddaee6dSMax Filippov #define XCHAL_INT12_LEVEL 4 3727ddaee6dSMax Filippov #define XCHAL_INT13_LEVEL 5 3737ddaee6dSMax Filippov #define XCHAL_INT14_LEVEL 7 3747ddaee6dSMax Filippov #define XCHAL_INT15_LEVEL 1 3757ddaee6dSMax Filippov #define XCHAL_INT16_LEVEL 1 3767ddaee6dSMax Filippov #define XCHAL_INT17_LEVEL 1 3777ddaee6dSMax Filippov #define XCHAL_INT18_LEVEL 1 3787ddaee6dSMax Filippov #define XCHAL_INT19_LEVEL 1 3797ddaee6dSMax Filippov #define XCHAL_INT20_LEVEL 1 3807ddaee6dSMax Filippov #define XCHAL_INT21_LEVEL 3 3817ddaee6dSMax Filippov #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 3827ddaee6dSMax Filippov #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 3837ddaee6dSMax Filippov #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 3847ddaee6dSMax Filippov EXCSAVE/EPS/EPC_n, RFI n) */ 3857ddaee6dSMax Filippov 3867ddaee6dSMax Filippov /* Type of each interrupt: */ 3877ddaee6dSMax Filippov #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3887ddaee6dSMax Filippov #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3897ddaee6dSMax Filippov #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3907ddaee6dSMax Filippov #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3917ddaee6dSMax Filippov #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3927ddaee6dSMax Filippov #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3937ddaee6dSMax Filippov #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 3947ddaee6dSMax Filippov #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 3957ddaee6dSMax Filippov #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3967ddaee6dSMax Filippov #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 3977ddaee6dSMax Filippov #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER 3987ddaee6dSMax Filippov #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE 3997ddaee6dSMax Filippov #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 4007ddaee6dSMax Filippov #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER 4017ddaee6dSMax Filippov #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 4027ddaee6dSMax Filippov #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE 4037ddaee6dSMax Filippov #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE 4047ddaee6dSMax Filippov #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE 4057ddaee6dSMax Filippov #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE 4067ddaee6dSMax Filippov #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE 4077ddaee6dSMax Filippov #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE 4087ddaee6dSMax Filippov #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE 4097ddaee6dSMax Filippov 4107ddaee6dSMax Filippov /* Masks of interrupts for each type of interrupt: */ 4117ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 4127ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 4137ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 4147ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F 4157ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_TIMER 0x00002440 4167ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_NMI 0x00004000 4177ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 4187ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 4197ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 4207ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 4217ddaee6dSMax Filippov #define XCHAL_INTTYPE_MASK_SG_ERR 0x00000000 4227ddaee6dSMax Filippov 4237ddaee6dSMax Filippov /* Interrupt numbers assigned to specific interrupt sources: */ 4247ddaee6dSMax Filippov #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 4257ddaee6dSMax Filippov #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ 4267ddaee6dSMax Filippov #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ 4277ddaee6dSMax Filippov #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 4287ddaee6dSMax Filippov #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 4297ddaee6dSMax Filippov 4307ddaee6dSMax Filippov /* Interrupt numbers for levels at which only one interrupt is configured: */ 4317ddaee6dSMax Filippov #define XCHAL_INTLEVEL2_NUM 8 4327ddaee6dSMax Filippov #define XCHAL_INTLEVEL4_NUM 12 4337ddaee6dSMax Filippov #define XCHAL_INTLEVEL5_NUM 13 4347ddaee6dSMax Filippov #define XCHAL_INTLEVEL7_NUM 14 4357ddaee6dSMax Filippov /* (There are many interrupts each at level(s) 1, 3.) */ 4367ddaee6dSMax Filippov 4377ddaee6dSMax Filippov 4387ddaee6dSMax Filippov /* 4397ddaee6dSMax Filippov * External interrupt mapping. 4407ddaee6dSMax Filippov * These macros describe how Xtensa processor interrupt numbers 4417ddaee6dSMax Filippov * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 4427ddaee6dSMax Filippov * map to external BInterrupt<n> pins, for those interrupts 4437ddaee6dSMax Filippov * configured as external (level-triggered, edge-triggered, or NMI). 4447ddaee6dSMax Filippov * See the Xtensa processor databook for more details. 4457ddaee6dSMax Filippov */ 4467ddaee6dSMax Filippov 4477ddaee6dSMax Filippov /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ 4487ddaee6dSMax Filippov #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 4497ddaee6dSMax Filippov #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 4507ddaee6dSMax Filippov #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 4517ddaee6dSMax Filippov #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 4527ddaee6dSMax Filippov #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 4537ddaee6dSMax Filippov #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 4547ddaee6dSMax Filippov #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ 4557ddaee6dSMax Filippov #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ 4567ddaee6dSMax Filippov #define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ 4577ddaee6dSMax Filippov #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ 4587ddaee6dSMax Filippov #define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ 4597ddaee6dSMax Filippov #define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ 4607ddaee6dSMax Filippov #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ 4617ddaee6dSMax Filippov #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ 4627ddaee6dSMax Filippov #define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ 4637ddaee6dSMax Filippov #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ 4647ddaee6dSMax Filippov #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ 4657ddaee6dSMax Filippov /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ 4667ddaee6dSMax Filippov #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ 4677ddaee6dSMax Filippov #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ 4687ddaee6dSMax Filippov #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ 4697ddaee6dSMax Filippov #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ 4707ddaee6dSMax Filippov #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ 4717ddaee6dSMax Filippov #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ 4727ddaee6dSMax Filippov #define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ 4737ddaee6dSMax Filippov #define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ 4747ddaee6dSMax Filippov #define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ 4757ddaee6dSMax Filippov #define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ 4767ddaee6dSMax Filippov #define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */ 4777ddaee6dSMax Filippov #define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */ 4787ddaee6dSMax Filippov #define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ 4797ddaee6dSMax Filippov #define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ 4807ddaee6dSMax Filippov #define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */ 4817ddaee6dSMax Filippov #define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ 4827ddaee6dSMax Filippov #define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */ 4837ddaee6dSMax Filippov 4847ddaee6dSMax Filippov 4857ddaee6dSMax Filippov /*---------------------------------------------------------------------- 4867ddaee6dSMax Filippov EXCEPTIONS and VECTORS 4877ddaee6dSMax Filippov ----------------------------------------------------------------------*/ 4887ddaee6dSMax Filippov 4897ddaee6dSMax Filippov #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 4907ddaee6dSMax Filippov number: 1 == XEA1 (old) 4917ddaee6dSMax Filippov 2 == XEA2 (new) 4927ddaee6dSMax Filippov 0 == XEAX (extern) or TX */ 4937ddaee6dSMax Filippov #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 4947ddaee6dSMax Filippov #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 4957ddaee6dSMax Filippov #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 4967ddaee6dSMax Filippov #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 4977ddaee6dSMax Filippov #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 4987ddaee6dSMax Filippov #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 4997ddaee6dSMax Filippov #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 5007ddaee6dSMax Filippov #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 5017ddaee6dSMax Filippov #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 5027ddaee6dSMax Filippov #define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */ 5037ddaee6dSMax Filippov #define XCHAL_VECBASE_RESET_PADDR 0x60000000 5047ddaee6dSMax Filippov #define XCHAL_RESET_VECBASE_OVERLAP 0 5057ddaee6dSMax Filippov 5067ddaee6dSMax Filippov #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 5077ddaee6dSMax Filippov #define XCHAL_RESET_VECTOR0_PADDR 0x50000000 5087ddaee6dSMax Filippov #define XCHAL_RESET_VECTOR1_VADDR 0x40000400 5097ddaee6dSMax Filippov #define XCHAL_RESET_VECTOR1_PADDR 0x40000400 5107ddaee6dSMax Filippov #define XCHAL_RESET_VECTOR_VADDR 0x50000000 5117ddaee6dSMax Filippov #define XCHAL_RESET_VECTOR_PADDR 0x50000000 5127ddaee6dSMax Filippov #define XCHAL_USER_VECOFS 0x00000340 5137ddaee6dSMax Filippov #define XCHAL_USER_VECTOR_VADDR 0x60000340 5147ddaee6dSMax Filippov #define XCHAL_USER_VECTOR_PADDR 0x60000340 5157ddaee6dSMax Filippov #define XCHAL_KERNEL_VECOFS 0x00000300 5167ddaee6dSMax Filippov #define XCHAL_KERNEL_VECTOR_VADDR 0x60000300 5177ddaee6dSMax Filippov #define XCHAL_KERNEL_VECTOR_PADDR 0x60000300 5187ddaee6dSMax Filippov #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 5197ddaee6dSMax Filippov #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x600003C0 5207ddaee6dSMax Filippov #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x600003C0 5217ddaee6dSMax Filippov #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 5227ddaee6dSMax Filippov #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 5237ddaee6dSMax Filippov #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 5247ddaee6dSMax Filippov #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 5257ddaee6dSMax Filippov #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 5267ddaee6dSMax Filippov #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 5277ddaee6dSMax Filippov #define XCHAL_WINDOW_VECTORS_VADDR 0x60000000 5287ddaee6dSMax Filippov #define XCHAL_WINDOW_VECTORS_PADDR 0x60000000 5297ddaee6dSMax Filippov #define XCHAL_INTLEVEL2_VECOFS 0x00000180 5307ddaee6dSMax Filippov #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x60000180 5317ddaee6dSMax Filippov #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x60000180 5327ddaee6dSMax Filippov #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 5337ddaee6dSMax Filippov #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x600001C0 5347ddaee6dSMax Filippov #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x600001C0 5357ddaee6dSMax Filippov #define XCHAL_INTLEVEL4_VECOFS 0x00000200 5367ddaee6dSMax Filippov #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x60000200 5377ddaee6dSMax Filippov #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x60000200 5387ddaee6dSMax Filippov #define XCHAL_INTLEVEL5_VECOFS 0x00000240 5397ddaee6dSMax Filippov #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x60000240 5407ddaee6dSMax Filippov #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x60000240 5417ddaee6dSMax Filippov #define XCHAL_INTLEVEL6_VECOFS 0x00000280 5427ddaee6dSMax Filippov #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x60000280 5437ddaee6dSMax Filippov #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x60000280 5447ddaee6dSMax Filippov #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 5457ddaee6dSMax Filippov #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 5467ddaee6dSMax Filippov #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 5477ddaee6dSMax Filippov #define XCHAL_NMI_VECOFS 0x000002C0 5487ddaee6dSMax Filippov #define XCHAL_NMI_VECTOR_VADDR 0x600002C0 5497ddaee6dSMax Filippov #define XCHAL_NMI_VECTOR_PADDR 0x600002C0 5507ddaee6dSMax Filippov #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 5517ddaee6dSMax Filippov #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 5527ddaee6dSMax Filippov #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 5537ddaee6dSMax Filippov 5547ddaee6dSMax Filippov 5557ddaee6dSMax Filippov /*---------------------------------------------------------------------- 5567ddaee6dSMax Filippov DEBUG MODULE 5577ddaee6dSMax Filippov ----------------------------------------------------------------------*/ 5587ddaee6dSMax Filippov 5597ddaee6dSMax Filippov /* Misc */ 5607ddaee6dSMax Filippov #define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ 5617ddaee6dSMax Filippov #define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ 5627ddaee6dSMax Filippov #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ 5637ddaee6dSMax Filippov 5647ddaee6dSMax Filippov /* On-Chip Debug (OCD) */ 5657ddaee6dSMax Filippov #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 5667ddaee6dSMax Filippov #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 5677ddaee6dSMax Filippov #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 5687ddaee6dSMax Filippov #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ 5697ddaee6dSMax Filippov #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ 5707ddaee6dSMax Filippov 5717ddaee6dSMax Filippov /* TRAX (in core) */ 5727ddaee6dSMax Filippov #define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ 5737ddaee6dSMax Filippov #define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */ 5747ddaee6dSMax Filippov #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ 5757ddaee6dSMax Filippov #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ 5767ddaee6dSMax Filippov #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ 5777ddaee6dSMax Filippov 5787ddaee6dSMax Filippov /* Perf counters */ 5797ddaee6dSMax Filippov #define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ 5807ddaee6dSMax Filippov 5817ddaee6dSMax Filippov 5827ddaee6dSMax Filippov /*---------------------------------------------------------------------- 5837ddaee6dSMax Filippov MMU 5847ddaee6dSMax Filippov ----------------------------------------------------------------------*/ 5857ddaee6dSMax Filippov 5867ddaee6dSMax Filippov /* See core-matmap.h header file for more details. */ 5877ddaee6dSMax Filippov 5887ddaee6dSMax Filippov #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 5897ddaee6dSMax Filippov #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 5907ddaee6dSMax Filippov #define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ 5917ddaee6dSMax Filippov #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ 5927ddaee6dSMax Filippov #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 5937ddaee6dSMax Filippov #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ 5947ddaee6dSMax Filippov #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 5957ddaee6dSMax Filippov #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table 5967ddaee6dSMax Filippov [autorefill] and protection) 5977ddaee6dSMax Filippov usable for an MMU-based OS */ 5987ddaee6dSMax Filippov 5997ddaee6dSMax Filippov /* If none of the above last 5 are set, it's a custom TLB configuration. */ 6007ddaee6dSMax Filippov 6017ddaee6dSMax Filippov #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ 6027ddaee6dSMax Filippov #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ 6037ddaee6dSMax Filippov #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ 6047ddaee6dSMax Filippov 6057ddaee6dSMax Filippov /*---------------------------------------------------------------------- 6067ddaee6dSMax Filippov MPU 6077ddaee6dSMax Filippov ----------------------------------------------------------------------*/ 6087ddaee6dSMax Filippov #define XCHAL_HAVE_MPU 0 6097ddaee6dSMax Filippov #define XCHAL_MPU_ENTRIES 0 6107ddaee6dSMax Filippov 6117ddaee6dSMax Filippov #define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */ 6127ddaee6dSMax Filippov #define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in background map */ 6137ddaee6dSMax Filippov 6147ddaee6dSMax Filippov #define XCHAL_MPU_ALIGN_BITS 0 6157ddaee6dSMax Filippov #define XCHAL_MPU_ALIGN 0 6167ddaee6dSMax Filippov 6177ddaee6dSMax Filippov #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 6187ddaee6dSMax Filippov 6197ddaee6dSMax Filippov 620*81416747SMarkus Armbruster #endif /* XTENSA_CORE_DE212_CORE_ISA_H */ 621