1/* Xtensa configuration-specific ISA information. 2 3 Copyright (c) 2003-2015 Tensilica Inc. 4 5 Permission is hereby granted, free of charge, to any person obtaining 6 a copy of this software and associated documentation files (the 7 "Software"), to deal in the Software without restriction, including 8 without limitation the rights to use, copy, modify, merge, publish, 9 distribute, sublicense, and/or sell copies of the Software, and to 10 permit persons to whom the Software is furnished to do so, subject to 11 the following conditions: 12 13 The above copyright notice and this permission notice shall be included 14 in all copies or substantial portions of the Software. 15 16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 17 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 19 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 20 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "qemu/osdep.h" 25#include "xtensa-isa.h" 26#include "xtensa-isa-internal.h" 27 28 29/* Sysregs. */ 30 31static xtensa_sysreg_internal sysregs[] = { 32 { "LBEG", 0, 0 }, 33 { "LEND", 1, 0 }, 34 { "LCOUNT", 2, 0 }, 35 { "ACCLO", 16, 0 }, 36 { "ACCHI", 17, 0 }, 37 { "M0", 32, 0 }, 38 { "M1", 33, 0 }, 39 { "M2", 34, 0 }, 40 { "M3", 35, 0 }, 41 { "MMID", 89, 0 }, 42 { "DDR", 104, 0 }, 43 { "CONFIGID0", 176, 0 }, 44 { "CONFIGID1", 208, 0 }, 45 { "INTERRUPT", 226, 0 }, 46 { "INTCLEAR", 227, 0 }, 47 { "CCOUNT", 234, 0 }, 48 { "PRID", 235, 0 }, 49 { "ICOUNT", 236, 0 }, 50 { "CCOMPARE0", 240, 0 }, 51 { "CCOMPARE1", 241, 0 }, 52 { "CCOMPARE2", 242, 0 }, 53 { "VECBASE", 231, 0 }, 54 { "EPC1", 177, 0 }, 55 { "EPC2", 178, 0 }, 56 { "EPC3", 179, 0 }, 57 { "EPC4", 180, 0 }, 58 { "EPC5", 181, 0 }, 59 { "EPC6", 182, 0 }, 60 { "EPC7", 183, 0 }, 61 { "EXCSAVE1", 209, 0 }, 62 { "EXCSAVE2", 210, 0 }, 63 { "EXCSAVE3", 211, 0 }, 64 { "EXCSAVE4", 212, 0 }, 65 { "EXCSAVE5", 213, 0 }, 66 { "EXCSAVE6", 214, 0 }, 67 { "EXCSAVE7", 215, 0 }, 68 { "EPS2", 194, 0 }, 69 { "EPS3", 195, 0 }, 70 { "EPS4", 196, 0 }, 71 { "EPS5", 197, 0 }, 72 { "EPS6", 198, 0 }, 73 { "EPS7", 199, 0 }, 74 { "EXCCAUSE", 232, 0 }, 75 { "DEPC", 192, 0 }, 76 { "EXCVADDR", 238, 0 }, 77 { "WINDOWBASE", 72, 0 }, 78 { "WINDOWSTART", 73, 0 }, 79 { "SAR", 3, 0 }, 80 { "PS", 230, 0 }, 81 { "MISC0", 244, 0 }, 82 { "MISC1", 245, 0 }, 83 { "INTENABLE", 228, 0 }, 84 { "DBREAKA0", 144, 0 }, 85 { "DBREAKC0", 160, 0 }, 86 { "DBREAKA1", 145, 0 }, 87 { "DBREAKC1", 161, 0 }, 88 { "IBREAKA0", 128, 0 }, 89 { "IBREAKA1", 129, 0 }, 90 { "IBREAKENABLE", 96, 0 }, 91 { "ICOUNTLEVEL", 237, 0 }, 92 { "DEBUGCAUSE", 233, 0 }, 93 { "SCOMPARE1", 12, 0 }, 94 { "ATOMCTL", 99, 0 }, 95 { "EXPSTATE", 230, 1 } 96}; 97 98#define NUM_SYSREGS 64 99#define MAX_SPECIAL_REG 245 100#define MAX_USER_REG 230 101 102 103/* Processor states. */ 104 105static xtensa_state_internal states[] = { 106 { "LCOUNT", 32, 0 }, 107 { "PC", 32, 0 }, 108 { "ICOUNT", 32, 0 }, 109 { "DDR", 32, 0 }, 110 { "INTERRUPT", 22, 0 }, 111 { "CCOUNT", 32, 0 }, 112 { "XTSYNC", 1, 0 }, 113 { "VECBASE", 22, 0 }, 114 { "EPC1", 32, 0 }, 115 { "EPC2", 32, 0 }, 116 { "EPC3", 32, 0 }, 117 { "EPC4", 32, 0 }, 118 { "EPC5", 32, 0 }, 119 { "EPC6", 32, 0 }, 120 { "EPC7", 32, 0 }, 121 { "EXCSAVE1", 32, 0 }, 122 { "EXCSAVE2", 32, 0 }, 123 { "EXCSAVE3", 32, 0 }, 124 { "EXCSAVE4", 32, 0 }, 125 { "EXCSAVE5", 32, 0 }, 126 { "EXCSAVE6", 32, 0 }, 127 { "EXCSAVE7", 32, 0 }, 128 { "EPS2", 13, 0 }, 129 { "EPS3", 13, 0 }, 130 { "EPS4", 13, 0 }, 131 { "EPS5", 13, 0 }, 132 { "EPS6", 13, 0 }, 133 { "EPS7", 13, 0 }, 134 { "EXCCAUSE", 6, 0 }, 135 { "PSINTLEVEL", 4, 0 }, 136 { "PSUM", 1, 0 }, 137 { "PSWOE", 1, 0 }, 138 { "PSEXCM", 1, 0 }, 139 { "DEPC", 32, 0 }, 140 { "EXCVADDR", 32, 0 }, 141 { "WindowBase", 3, 0 }, 142 { "WindowStart", 8, 0 }, 143 { "PSCALLINC", 2, 0 }, 144 { "PSOWB", 4, 0 }, 145 { "LBEG", 32, 0 }, 146 { "LEND", 32, 0 }, 147 { "SAR", 6, 0 }, 148 { "MISC0", 32, 0 }, 149 { "MISC1", 32, 0 }, 150 { "ACC", 40, 0 }, 151 { "InOCDMode", 1, 0 }, 152 { "INTENABLE", 22, 0 }, 153 { "DBREAKA0", 32, 0 }, 154 { "DBREAKC0", 8, 0 }, 155 { "DBREAKA1", 32, 0 }, 156 { "DBREAKC1", 8, 0 }, 157 { "IBREAKA0", 32, 0 }, 158 { "IBREAKA1", 32, 0 }, 159 { "IBREAKENABLE", 2, 0 }, 160 { "ICOUNTLEVEL", 4, 0 }, 161 { "DEBUGCAUSE", 6, 0 }, 162 { "DBNUM", 4, 0 }, 163 { "CCOMPARE0", 32, 0 }, 164 { "CCOMPARE1", 32, 0 }, 165 { "CCOMPARE2", 32, 0 }, 166 { "SCOMPARE1", 32, 0 }, 167 { "ATOMCTL", 6, 0 }, 168 { "ERI_RAW_INTERLOCK", 1, 0 }, 169 { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } 170}; 171 172#define NUM_STATES 64 173 174enum xtensa_state_id { 175 STATE_LCOUNT, 176 STATE_PC, 177 STATE_ICOUNT, 178 STATE_DDR, 179 STATE_INTERRUPT, 180 STATE_CCOUNT, 181 STATE_XTSYNC, 182 STATE_VECBASE, 183 STATE_EPC1, 184 STATE_EPC2, 185 STATE_EPC3, 186 STATE_EPC4, 187 STATE_EPC5, 188 STATE_EPC6, 189 STATE_EPC7, 190 STATE_EXCSAVE1, 191 STATE_EXCSAVE2, 192 STATE_EXCSAVE3, 193 STATE_EXCSAVE4, 194 STATE_EXCSAVE5, 195 STATE_EXCSAVE6, 196 STATE_EXCSAVE7, 197 STATE_EPS2, 198 STATE_EPS3, 199 STATE_EPS4, 200 STATE_EPS5, 201 STATE_EPS6, 202 STATE_EPS7, 203 STATE_EXCCAUSE, 204 STATE_PSINTLEVEL, 205 STATE_PSUM, 206 STATE_PSWOE, 207 STATE_PSEXCM, 208 STATE_DEPC, 209 STATE_EXCVADDR, 210 STATE_WindowBase, 211 STATE_WindowStart, 212 STATE_PSCALLINC, 213 STATE_PSOWB, 214 STATE_LBEG, 215 STATE_LEND, 216 STATE_SAR, 217 STATE_MISC0, 218 STATE_MISC1, 219 STATE_ACC, 220 STATE_InOCDMode, 221 STATE_INTENABLE, 222 STATE_DBREAKA0, 223 STATE_DBREAKC0, 224 STATE_DBREAKA1, 225 STATE_DBREAKC1, 226 STATE_IBREAKA0, 227 STATE_IBREAKA1, 228 STATE_IBREAKENABLE, 229 STATE_ICOUNTLEVEL, 230 STATE_DEBUGCAUSE, 231 STATE_DBNUM, 232 STATE_CCOMPARE0, 233 STATE_CCOMPARE1, 234 STATE_CCOMPARE2, 235 STATE_SCOMPARE1, 236 STATE_ATOMCTL, 237 STATE_ERI_RAW_INTERLOCK, 238 STATE_EXPSTATE 239}; 240 241 242/* Field definitions. */ 243 244static unsigned 245Field_t_Slot_inst_get (const xtensa_insnbuf insn) 246{ 247 unsigned tie_t = 0; 248 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 249 return tie_t; 250} 251 252static void 253Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 254{ 255 uint32 tie_t; 256 tie_t = (val << 28) >> 28; 257 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 258} 259 260static unsigned 261Field_s_Slot_inst_get (const xtensa_insnbuf insn) 262{ 263 unsigned tie_t = 0; 264 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 265 return tie_t; 266} 267 268static void 269Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 270{ 271 uint32 tie_t; 272 tie_t = (val << 28) >> 28; 273 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 274} 275 276static unsigned 277Field_r_Slot_inst_get (const xtensa_insnbuf insn) 278{ 279 unsigned tie_t = 0; 280 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 281 return tie_t; 282} 283 284static void 285Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 286{ 287 uint32 tie_t; 288 tie_t = (val << 28) >> 28; 289 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 290} 291 292static unsigned 293Field_op2_Slot_inst_get (const xtensa_insnbuf insn) 294{ 295 unsigned tie_t = 0; 296 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); 297 return tie_t; 298} 299 300static void 301Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 302{ 303 uint32 tie_t; 304 tie_t = (val << 28) >> 28; 305 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); 306} 307 308static unsigned 309Field_op1_Slot_inst_get (const xtensa_insnbuf insn) 310{ 311 unsigned tie_t = 0; 312 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 313 return tie_t; 314} 315 316static void 317Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 318{ 319 uint32 tie_t; 320 tie_t = (val << 28) >> 28; 321 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 322} 323 324static unsigned 325Field_op0_Slot_inst_get (const xtensa_insnbuf insn) 326{ 327 unsigned tie_t = 0; 328 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 329 return tie_t; 330} 331 332static void 333Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 334{ 335 uint32 tie_t; 336 tie_t = (val << 28) >> 28; 337 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 338} 339 340static unsigned 341Field_n_Slot_inst_get (const xtensa_insnbuf insn) 342{ 343 unsigned tie_t = 0; 344 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 345 return tie_t; 346} 347 348static void 349Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 350{ 351 uint32 tie_t; 352 tie_t = (val << 30) >> 30; 353 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 354} 355 356static unsigned 357Field_m_Slot_inst_get (const xtensa_insnbuf insn) 358{ 359 unsigned tie_t = 0; 360 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); 361 return tie_t; 362} 363 364static void 365Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 366{ 367 uint32 tie_t; 368 tie_t = (val << 30) >> 30; 369 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); 370} 371 372static unsigned 373Field_sr_Slot_inst_get (const xtensa_insnbuf insn) 374{ 375 unsigned tie_t = 0; 376 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 377 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 378 return tie_t; 379} 380 381static void 382Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 383{ 384 uint32 tie_t; 385 tie_t = (val << 28) >> 28; 386 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 387 tie_t = (val << 24) >> 28; 388 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 389} 390 391static unsigned 392Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) 393{ 394 unsigned tie_t = 0; 395 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); 396 return tie_t; 397} 398 399static void 400Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 401{ 402 uint32 tie_t; 403 tie_t = (val << 29) >> 29; 404 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); 405} 406 407static unsigned 408Field_t3_Slot_inst_get (const xtensa_insnbuf insn) 409{ 410 unsigned tie_t = 0; 411 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 412 return tie_t; 413} 414 415static void 416Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 417{ 418 uint32 tie_t; 419 tie_t = (val << 31) >> 31; 420 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 421} 422 423static unsigned 424Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) 425{ 426 unsigned tie_t = 0; 427 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 428 return tie_t; 429} 430 431static void 432Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 433{ 434 uint32 tie_t; 435 tie_t = (val << 30) >> 30; 436 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 437} 438 439static unsigned 440Field_w_Slot_inst_get (const xtensa_insnbuf insn) 441{ 442 unsigned tie_t = 0; 443 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 444 return tie_t; 445} 446 447static void 448Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 449{ 450 uint32 tie_t; 451 tie_t = (val << 30) >> 30; 452 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 453} 454 455static unsigned 456Field_r3_Slot_inst_get (const xtensa_insnbuf insn) 457{ 458 unsigned tie_t = 0; 459 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 460 return tie_t; 461} 462 463static void 464Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 465{ 466 uint32 tie_t; 467 tie_t = (val << 31) >> 31; 468 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 469} 470 471static unsigned 472Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) 473{ 474 unsigned tie_t = 0; 475 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 476 return tie_t; 477} 478 479static void 480Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 481{ 482 uint32 tie_t; 483 tie_t = (val << 30) >> 30; 484 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 485} 486 487static unsigned 488Field_st_Slot_inst_get (const xtensa_insnbuf insn) 489{ 490 unsigned tie_t = 0; 491 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 492 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 493 return tie_t; 494} 495 496static void 497Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 498{ 499 uint32 tie_t; 500 tie_t = (val << 28) >> 28; 501 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 502 tie_t = (val << 24) >> 28; 503 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 504} 505 506static unsigned 507Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) 508{ 509 unsigned tie_t = 0; 510 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 511 return tie_t; 512} 513 514static void 515Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 516{ 517 uint32 tie_t; 518 tie_t = (val << 29) >> 29; 519 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 520} 521 522static unsigned 523Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) 524{ 525 unsigned tie_t = 0; 526 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 527 return tie_t; 528} 529 530static void 531Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 532{ 533 uint32 tie_t; 534 tie_t = (val << 28) >> 28; 535 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 536} 537 538static unsigned 539Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) 540{ 541 unsigned tie_t = 0; 542 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 543 return tie_t; 544} 545 546static void 547Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 548{ 549 uint32 tie_t; 550 tie_t = (val << 28) >> 28; 551 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 552} 553 554static unsigned 555Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) 556{ 557 unsigned tie_t = 0; 558 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 559 return tie_t; 560} 561 562static void 563Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 564{ 565 uint32 tie_t; 566 tie_t = (val << 28) >> 28; 567 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 568} 569 570static unsigned 571Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) 572{ 573 unsigned tie_t = 0; 574 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 575 return tie_t; 576} 577 578static void 579Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 580{ 581 uint32 tie_t; 582 tie_t = (val << 28) >> 28; 583 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 584} 585 586static unsigned 587Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) 588{ 589 unsigned tie_t = 0; 590 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 591 return tie_t; 592} 593 594static void 595Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 596{ 597 uint32 tie_t; 598 tie_t = (val << 31) >> 31; 599 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 600} 601 602static unsigned 603Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) 604{ 605 unsigned tie_t = 0; 606 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 607 return tie_t; 608} 609 610static void 611Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 612{ 613 uint32 tie_t; 614 tie_t = (val << 31) >> 31; 615 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 616} 617 618static unsigned 619Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) 620{ 621 unsigned tie_t = 0; 622 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 623 return tie_t; 624} 625 626static void 627Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 628{ 629 uint32 tie_t; 630 tie_t = (val << 28) >> 28; 631 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 632} 633 634static unsigned 635Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) 636{ 637 unsigned tie_t = 0; 638 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 639 return tie_t; 640} 641 642static void 643Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 644{ 645 uint32 tie_t; 646 tie_t = (val << 28) >> 28; 647 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 648} 649 650static unsigned 651Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) 652{ 653 unsigned tie_t = 0; 654 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); 655 return tie_t; 656} 657 658static void 659Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 660{ 661 uint32 tie_t; 662 tie_t = (val << 31) >> 31; 663 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); 664} 665 666static unsigned 667Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) 668{ 669 unsigned tie_t = 0; 670 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); 671 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 672 return tie_t; 673} 674 675static void 676Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 677{ 678 uint32 tie_t; 679 tie_t = (val << 28) >> 28; 680 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 681 tie_t = (val << 27) >> 31; 682 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); 683} 684 685static unsigned 686Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) 687{ 688 unsigned tie_t = 0; 689 tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20); 690 return tie_t; 691} 692 693static void 694Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 695{ 696 uint32 tie_t; 697 tie_t = (val << 20) >> 20; 698 insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12); 699} 700 701static unsigned 702Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) 703{ 704 unsigned tie_t = 0; 705 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); 706 return tie_t; 707} 708 709static void 710Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 711{ 712 uint32 tie_t; 713 tie_t = (val << 24) >> 24; 714 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); 715} 716 717static unsigned 718Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) 719{ 720 unsigned tie_t = 0; 721 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 722 return tie_t; 723} 724 725static void 726Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 727{ 728 uint32 tie_t; 729 tie_t = (val << 28) >> 28; 730 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 731} 732 733static unsigned 734Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) 735{ 736 unsigned tie_t = 0; 737 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 738 tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24); 739 return tie_t; 740} 741 742static void 743Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 744{ 745 uint32 tie_t; 746 tie_t = (val << 24) >> 24; 747 insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16); 748 tie_t = (val << 20) >> 28; 749 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 750} 751 752static unsigned 753Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) 754{ 755 unsigned tie_t = 0; 756 tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16); 757 return tie_t; 758} 759 760static void 761Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 762{ 763 uint32 tie_t; 764 tie_t = (val << 16) >> 16; 765 insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8); 766} 767 768static unsigned 769Field_offset_Slot_inst_get (const xtensa_insnbuf insn) 770{ 771 unsigned tie_t = 0; 772 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); 773 return tie_t; 774} 775 776static void 777Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 778{ 779 uint32 tie_t; 780 tie_t = (val << 14) >> 14; 781 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); 782} 783 784static unsigned 785Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) 786{ 787 unsigned tie_t = 0; 788 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 789 return tie_t; 790} 791 792static void 793Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 794{ 795 uint32 tie_t; 796 tie_t = (val << 28) >> 28; 797 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 798} 799 800static unsigned 801Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) 802{ 803 unsigned tie_t = 0; 804 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 805 return tie_t; 806} 807 808static void 809Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 810{ 811 uint32 tie_t; 812 tie_t = (val << 31) >> 31; 813 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 814} 815 816static unsigned 817Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) 818{ 819 unsigned tie_t = 0; 820 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 821 return tie_t; 822} 823 824static void 825Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 826{ 827 uint32 tie_t; 828 tie_t = (val << 31) >> 31; 829 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 830} 831 832static unsigned 833Field_sae_Slot_inst_get (const xtensa_insnbuf insn) 834{ 835 unsigned tie_t = 0; 836 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 837 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 838 return tie_t; 839} 840 841static void 842Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 843{ 844 uint32 tie_t; 845 tie_t = (val << 28) >> 28; 846 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 847 tie_t = (val << 27) >> 31; 848 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 849} 850 851static unsigned 852Field_sal_Slot_inst_get (const xtensa_insnbuf insn) 853{ 854 unsigned tie_t = 0; 855 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 856 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 857 return tie_t; 858} 859 860static void 861Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 862{ 863 uint32 tie_t; 864 tie_t = (val << 28) >> 28; 865 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 866 tie_t = (val << 27) >> 31; 867 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 868} 869 870static unsigned 871Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) 872{ 873 unsigned tie_t = 0; 874 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 875 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 876 return tie_t; 877} 878 879static void 880Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 881{ 882 uint32 tie_t; 883 tie_t = (val << 28) >> 28; 884 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 885 tie_t = (val << 27) >> 31; 886 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 887} 888 889static unsigned 890Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) 891{ 892 unsigned tie_t = 0; 893 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 894 return tie_t; 895} 896 897static void 898Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 899{ 900 uint32 tie_t; 901 tie_t = (val << 31) >> 31; 902 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 903} 904 905static unsigned 906Field_sas_Slot_inst_get (const xtensa_insnbuf insn) 907{ 908 unsigned tie_t = 0; 909 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 910 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 911 return tie_t; 912} 913 914static void 915Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 916{ 917 uint32 tie_t; 918 tie_t = (val << 28) >> 28; 919 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 920 tie_t = (val << 27) >> 31; 921 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 922} 923 924static unsigned 925Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) 926{ 927 unsigned tie_t = 0; 928 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 929 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 930 return tie_t; 931} 932 933static void 934Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 935{ 936 uint32 tie_t; 937 tie_t = (val << 28) >> 28; 938 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 939 tie_t = (val << 24) >> 28; 940 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 941} 942 943static unsigned 944Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) 945{ 946 unsigned tie_t = 0; 947 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 948 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 949 return tie_t; 950} 951 952static void 953Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 954{ 955 uint32 tie_t; 956 tie_t = (val << 28) >> 28; 957 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 958 tie_t = (val << 24) >> 28; 959 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 960} 961 962static unsigned 963Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) 964{ 965 unsigned tie_t = 0; 966 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 967 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 968 return tie_t; 969} 970 971static void 972Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 973{ 974 uint32 tie_t; 975 tie_t = (val << 28) >> 28; 976 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 977 tie_t = (val << 24) >> 28; 978 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 979} 980 981static unsigned 982Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) 983{ 984 unsigned tie_t = 0; 985 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 986 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 987 return tie_t; 988} 989 990static void 991Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 992{ 993 uint32 tie_t; 994 tie_t = (val << 28) >> 28; 995 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 996 tie_t = (val << 24) >> 28; 997 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 998} 999 1000static unsigned 1001Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) 1002{ 1003 unsigned tie_t = 0; 1004 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1005 return tie_t; 1006} 1007 1008static void 1009Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1010{ 1011 uint32 tie_t; 1012 tie_t = (val << 28) >> 28; 1013 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1014} 1015 1016static unsigned 1017Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) 1018{ 1019 unsigned tie_t = 0; 1020 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1021 return tie_t; 1022} 1023 1024static void 1025Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1026{ 1027 uint32 tie_t; 1028 tie_t = (val << 28) >> 28; 1029 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1030} 1031 1032static unsigned 1033Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) 1034{ 1035 unsigned tie_t = 0; 1036 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1037 return tie_t; 1038} 1039 1040static void 1041Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1042{ 1043 uint32 tie_t; 1044 tie_t = (val << 28) >> 28; 1045 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1046} 1047 1048static unsigned 1049Field_mn_Slot_inst_get (const xtensa_insnbuf insn) 1050{ 1051 unsigned tie_t = 0; 1052 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); 1053 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1054 return tie_t; 1055} 1056 1057static void 1058Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1059{ 1060 uint32 tie_t; 1061 tie_t = (val << 30) >> 30; 1062 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1063 tie_t = (val << 28) >> 30; 1064 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); 1065} 1066 1067static unsigned 1068Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) 1069{ 1070 unsigned tie_t = 0; 1071 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 1072 return tie_t; 1073} 1074 1075static void 1076Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1077{ 1078 uint32 tie_t; 1079 tie_t = (val << 31) >> 31; 1080 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 1081} 1082 1083static unsigned 1084Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) 1085{ 1086 unsigned tie_t = 0; 1087 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1088 return tie_t; 1089} 1090 1091static void 1092Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1093{ 1094 uint32 tie_t; 1095 tie_t = (val << 28) >> 28; 1096 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1097} 1098 1099static unsigned 1100Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) 1101{ 1102 unsigned tie_t = 0; 1103 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1104 return tie_t; 1105} 1106 1107static void 1108Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1109{ 1110 uint32 tie_t; 1111 tie_t = (val << 28) >> 28; 1112 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1113} 1114 1115static unsigned 1116Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) 1117{ 1118 unsigned tie_t = 0; 1119 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1120 return tie_t; 1121} 1122 1123static void 1124Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1125{ 1126 uint32 tie_t; 1127 tie_t = (val << 30) >> 30; 1128 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1129} 1130 1131static unsigned 1132Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) 1133{ 1134 unsigned tie_t = 0; 1135 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1136 return tie_t; 1137} 1138 1139static void 1140Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1141{ 1142 uint32 tie_t; 1143 tie_t = (val << 30) >> 30; 1144 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1145} 1146 1147static unsigned 1148Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) 1149{ 1150 unsigned tie_t = 0; 1151 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1152 return tie_t; 1153} 1154 1155static void 1156Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1157{ 1158 uint32 tie_t; 1159 tie_t = (val << 28) >> 28; 1160 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1161} 1162 1163static unsigned 1164Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) 1165{ 1166 unsigned tie_t = 0; 1167 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1168 return tie_t; 1169} 1170 1171static void 1172Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1173{ 1174 uint32 tie_t; 1175 tie_t = (val << 28) >> 28; 1176 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1177} 1178 1179static unsigned 1180Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) 1181{ 1182 unsigned tie_t = 0; 1183 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1184 return tie_t; 1185} 1186 1187static void 1188Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1189{ 1190 uint32 tie_t; 1191 tie_t = (val << 29) >> 29; 1192 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1193} 1194 1195static unsigned 1196Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) 1197{ 1198 unsigned tie_t = 0; 1199 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1200 return tie_t; 1201} 1202 1203static void 1204Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1205{ 1206 uint32 tie_t; 1207 tie_t = (val << 29) >> 29; 1208 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1209} 1210 1211static unsigned 1212Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) 1213{ 1214 unsigned tie_t = 0; 1215 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1216 return tie_t; 1217} 1218 1219static void 1220Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1221{ 1222 uint32 tie_t; 1223 tie_t = (val << 31) >> 31; 1224 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1225} 1226 1227static unsigned 1228Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) 1229{ 1230 unsigned tie_t = 0; 1231 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1232 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1233 return tie_t; 1234} 1235 1236static void 1237Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1238{ 1239 uint32 tie_t; 1240 tie_t = (val << 28) >> 28; 1241 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1242 tie_t = (val << 26) >> 30; 1243 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1244} 1245 1246static unsigned 1247Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) 1248{ 1249 unsigned tie_t = 0; 1250 tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30); 1251 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1252 return tie_t; 1253} 1254 1255static void 1256Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1257{ 1258 uint32 tie_t; 1259 tie_t = (val << 28) >> 28; 1260 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1261 tie_t = (val << 26) >> 30; 1262 insn[0] = (insn[0] & ~0x30) | (tie_t << 4); 1263} 1264 1265static unsigned 1266Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) 1267{ 1268 unsigned tie_t = 0; 1269 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1270 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1271 return tie_t; 1272} 1273 1274static void 1275Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1276{ 1277 uint32 tie_t; 1278 tie_t = (val << 28) >> 28; 1279 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1280 tie_t = (val << 25) >> 29; 1281 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1282} 1283 1284static unsigned 1285Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) 1286{ 1287 unsigned tie_t = 0; 1288 tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29); 1289 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1290 return tie_t; 1291} 1292 1293static void 1294Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1295{ 1296 uint32 tie_t; 1297 tie_t = (val << 28) >> 28; 1298 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1299 tie_t = (val << 25) >> 29; 1300 insn[0] = (insn[0] & ~0x70) | (tie_t << 4); 1301} 1302 1303static unsigned 1304Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) 1305{ 1306 unsigned tie_t = 0; 1307 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 1308 return tie_t; 1309} 1310 1311static void 1312Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1313{ 1314 uint32 tie_t; 1315 tie_t = (val << 31) >> 31; 1316 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 1317} 1318 1319static unsigned 1320Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) 1321{ 1322 unsigned tie_t = 0; 1323 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1324 return tie_t; 1325} 1326 1327static void 1328Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1329{ 1330 uint32 tie_t; 1331 tie_t = (val << 31) >> 31; 1332 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1333} 1334 1335static unsigned 1336Field_y_Slot_inst_get (const xtensa_insnbuf insn) 1337{ 1338 unsigned tie_t = 0; 1339 tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31); 1340 return tie_t; 1341} 1342 1343static void 1344Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1345{ 1346 uint32 tie_t; 1347 tie_t = (val << 31) >> 31; 1348 insn[0] = (insn[0] & ~0x40) | (tie_t << 6); 1349} 1350 1351static unsigned 1352Field_x_Slot_inst_get (const xtensa_insnbuf insn) 1353{ 1354 unsigned tie_t = 0; 1355 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 1356 return tie_t; 1357} 1358 1359static void 1360Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1361{ 1362 uint32 tie_t; 1363 tie_t = (val << 31) >> 31; 1364 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 1365} 1366 1367static unsigned 1368Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) 1369{ 1370 unsigned tie_t = 0; 1371 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); 1372 return tie_t; 1373} 1374 1375static void 1376Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1377{ 1378 uint32 tie_t; 1379 tie_t = (val << 17) >> 17; 1380 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); 1381} 1382 1383static unsigned 1384Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) 1385{ 1386 unsigned tie_t = 0; 1387 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); 1388 return tie_t; 1389} 1390 1391static void 1392Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1393{ 1394 uint32 tie_t; 1395 tie_t = (val << 14) >> 14; 1396 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); 1397} 1398 1399static unsigned 1400Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) 1401{ 1402 unsigned tie_t = 0; 1403 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 1404 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 1405 return tie_t; 1406} 1407 1408static void 1409Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 1410{ 1411 uint32 tie_t; 1412 tie_t = (val << 28) >> 28; 1413 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 1414 tie_t = (val << 27) >> 31; 1415 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 1416} 1417 1418static unsigned 1419Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) 1420{ 1421 unsigned tie_t = 0; 1422 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 1423 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 1424 return tie_t; 1425} 1426 1427static void 1428Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1429{ 1430 uint32 tie_t; 1431 tie_t = (val << 28) >> 28; 1432 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 1433 tie_t = (val << 27) >> 31; 1434 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 1435} 1436 1437static unsigned 1438Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) 1439{ 1440 unsigned tie_t = 0; 1441 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 1442 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 1443 return tie_t; 1444} 1445 1446static void 1447Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1448{ 1449 uint32 tie_t; 1450 tie_t = (val << 28) >> 28; 1451 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 1452 tie_t = (val << 27) >> 31; 1453 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 1454} 1455 1456static unsigned 1457Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) 1458{ 1459 unsigned tie_t = 0; 1460 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 1461 return tie_t; 1462} 1463 1464static void 1465Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 1466{ 1467 uint32 tie_t; 1468 tie_t = (val << 29) >> 29; 1469 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 1470} 1471 1472static unsigned 1473Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) 1474{ 1475 unsigned tie_t = 0; 1476 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 1477 return tie_t; 1478} 1479 1480static void 1481Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 1482{ 1483 uint32 tie_t; 1484 tie_t = (val << 29) >> 29; 1485 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 1486} 1487 1488static void 1489Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, 1490 uint32 val ATTRIBUTE_UNUSED) 1491{ 1492 /* Do nothing. */ 1493} 1494 1495static unsigned 1496Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1497{ 1498 return 0; 1499} 1500 1501static unsigned 1502Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1503{ 1504 return 4; 1505} 1506 1507static unsigned 1508Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1509{ 1510 return 8; 1511} 1512 1513static unsigned 1514Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1515{ 1516 return 12; 1517} 1518 1519static unsigned 1520Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1521{ 1522 return 0; 1523} 1524 1525static unsigned 1526Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1527{ 1528 return 1; 1529} 1530 1531static unsigned 1532Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1533{ 1534 return 2; 1535} 1536 1537static unsigned 1538Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 1539{ 1540 return 3; 1541} 1542 1543enum xtensa_field_id { 1544 FIELD_t, 1545 FIELD_bbi4, 1546 FIELD_bbi, 1547 FIELD_imm12, 1548 FIELD_imm8, 1549 FIELD_s, 1550 FIELD_imm12b, 1551 FIELD_imm16, 1552 FIELD_m, 1553 FIELD_n, 1554 FIELD_offset, 1555 FIELD_op0, 1556 FIELD_op1, 1557 FIELD_op2, 1558 FIELD_r, 1559 FIELD_sa4, 1560 FIELD_sae4, 1561 FIELD_sae, 1562 FIELD_sal, 1563 FIELD_sargt, 1564 FIELD_sas4, 1565 FIELD_sas, 1566 FIELD_sr, 1567 FIELD_st, 1568 FIELD_thi3, 1569 FIELD_imm4, 1570 FIELD_mn, 1571 FIELD_i, 1572 FIELD_imm6lo, 1573 FIELD_imm6hi, 1574 FIELD_imm7lo, 1575 FIELD_imm7hi, 1576 FIELD_z, 1577 FIELD_imm6, 1578 FIELD_imm7, 1579 FIELD_r3, 1580 FIELD_rbit2, 1581 FIELD_rhi, 1582 FIELD_t3, 1583 FIELD_tbit2, 1584 FIELD_tlo, 1585 FIELD_w, 1586 FIELD_y, 1587 FIELD_x, 1588 FIELD_xt_wbr15_imm, 1589 FIELD_xt_wbr18_imm, 1590 FIELD_bitindex, 1591 FIELD_s3to1, 1592 FIELD__ar0, 1593 FIELD__ar4, 1594 FIELD__ar8, 1595 FIELD__ar12, 1596 FIELD__mr0, 1597 FIELD__mr1, 1598 FIELD__mr2, 1599 FIELD__mr3 1600}; 1601 1602 1603/* Functional units. */ 1604 1605#define funcUnits 0 1606 1607 1608/* Register files. */ 1609 1610enum xtensa_regfile_id { 1611 REGFILE_AR, 1612 REGFILE_MR 1613}; 1614 1615static xtensa_regfile_internal regfiles[] = { 1616 { "AR", "a", REGFILE_AR, 32, 32 }, 1617 { "MR", "m", REGFILE_MR, 32, 4 } 1618}; 1619 1620 1621/* Interfaces. */ 1622 1623static xtensa_interface_internal interfaces[] = { 1624 { "ERI_RD_Out", 14, 0, 0, 'o' }, 1625 { "ERI_RD_In", 32, 0, 1, 'i' }, 1626 { "ERI_RD_Rdy", 1, 0, 0, 'i' }, 1627 { "ERI_WR_Out", 46, 0, 2, 'o' }, 1628 { "ERI_WR_In", 1, 0, 3, 'i' }, 1629 { "IMPWIRE", 32, 0, 4, 'i' } 1630}; 1631 1632enum xtensa_interface_id { 1633 INTERFACE_ERI_RD_Out, 1634 INTERFACE_ERI_RD_In, 1635 INTERFACE_ERI_RD_Rdy, 1636 INTERFACE_ERI_WR_Out, 1637 INTERFACE_ERI_WR_In, 1638 INTERFACE_IMPWIRE 1639}; 1640 1641 1642/* Constant tables. */ 1643 1644/* constant table ai4c */ 1645static const unsigned CONST_TBL_ai4c_0[] = { 1646 0xffffffff, 1647 0x1, 1648 0x2, 1649 0x3, 1650 0x4, 1651 0x5, 1652 0x6, 1653 0x7, 1654 0x8, 1655 0x9, 1656 0xa, 1657 0xb, 1658 0xc, 1659 0xd, 1660 0xe, 1661 0xf, 1662 0 1663}; 1664 1665/* constant table b4c */ 1666static const unsigned CONST_TBL_b4c_0[] = { 1667 0xffffffff, 1668 0x1, 1669 0x2, 1670 0x3, 1671 0x4, 1672 0x5, 1673 0x6, 1674 0x7, 1675 0x8, 1676 0xa, 1677 0xc, 1678 0x10, 1679 0x20, 1680 0x40, 1681 0x80, 1682 0x100, 1683 0 1684}; 1685 1686/* constant table b4cu */ 1687static const unsigned CONST_TBL_b4cu_0[] = { 1688 0x8000, 1689 0x10000, 1690 0x2, 1691 0x3, 1692 0x4, 1693 0x5, 1694 0x6, 1695 0x7, 1696 0x8, 1697 0xa, 1698 0xc, 1699 0x10, 1700 0x20, 1701 0x40, 1702 0x80, 1703 0x100, 1704 0 1705}; 1706 1707 1708/* Instruction operands. */ 1709 1710static int 1711OperandSem_opnd_sem_MR_0_decode (uint32 *valp) 1712{ 1713 *valp += 2; 1714 return 0; 1715} 1716 1717static int 1718OperandSem_opnd_sem_MR_0_encode (uint32 *valp) 1719{ 1720 int error; 1721 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); 1722 *valp = *valp & 1; 1723 return error; 1724} 1725 1726static int 1727OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) 1728{ 1729 unsigned soffsetx4_out_0; 1730 unsigned soffsetx4_in_0; 1731 soffsetx4_in_0 = *valp & 0x3ffff; 1732 soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); 1733 *valp = soffsetx4_out_0; 1734 return 0; 1735} 1736 1737static int 1738OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) 1739{ 1740 unsigned soffsetx4_in_0; 1741 unsigned soffsetx4_out_0; 1742 soffsetx4_out_0 = *valp; 1743 soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; 1744 *valp = soffsetx4_in_0; 1745 return 0; 1746} 1747 1748static int 1749OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) 1750{ 1751 unsigned uimm12x8_out_0; 1752 unsigned uimm12x8_in_0; 1753 uimm12x8_in_0 = *valp & 0xfff; 1754 uimm12x8_out_0 = uimm12x8_in_0 << 3; 1755 *valp = uimm12x8_out_0; 1756 return 0; 1757} 1758 1759static int 1760OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) 1761{ 1762 unsigned uimm12x8_in_0; 1763 unsigned uimm12x8_out_0; 1764 uimm12x8_out_0 = *valp; 1765 uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); 1766 *valp = uimm12x8_in_0; 1767 return 0; 1768} 1769 1770static int 1771OperandSem_opnd_sem_simm4_decode (uint32 *valp) 1772{ 1773 unsigned simm4_out_0; 1774 unsigned simm4_in_0; 1775 simm4_in_0 = *valp & 0xf; 1776 simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; 1777 *valp = simm4_out_0; 1778 return 0; 1779} 1780 1781static int 1782OperandSem_opnd_sem_simm4_encode (uint32 *valp) 1783{ 1784 unsigned simm4_in_0; 1785 unsigned simm4_out_0; 1786 simm4_out_0 = *valp; 1787 simm4_in_0 = (simm4_out_0 & 0xf); 1788 *valp = simm4_in_0; 1789 return 0; 1790} 1791 1792static int 1793OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) 1794{ 1795 return 0; 1796} 1797 1798static int 1799OperandSem_opnd_sem_AR_encode (uint32 *valp) 1800{ 1801 return (*valp >= 32); 1802} 1803 1804static int 1805OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) 1806{ 1807 return 0; 1808} 1809 1810static int 1811OperandSem_opnd_sem_AR_0_encode (uint32 *valp) 1812{ 1813 return (*valp >= 32); 1814} 1815 1816static int 1817OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) 1818{ 1819 return 0; 1820} 1821 1822static int 1823OperandSem_opnd_sem_AR_1_encode (uint32 *valp) 1824{ 1825 return (*valp >= 32); 1826} 1827 1828static int 1829OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) 1830{ 1831 return 0; 1832} 1833 1834static int 1835OperandSem_opnd_sem_AR_2_encode (uint32 *valp) 1836{ 1837 return (*valp >= 32); 1838} 1839 1840static int 1841OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) 1842{ 1843 return 0; 1844} 1845 1846static int 1847OperandSem_opnd_sem_AR_3_encode (uint32 *valp) 1848{ 1849 return (*valp >= 32); 1850} 1851 1852static int 1853OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) 1854{ 1855 return 0; 1856} 1857 1858static int 1859OperandSem_opnd_sem_AR_4_encode (uint32 *valp) 1860{ 1861 return (*valp >= 32); 1862} 1863 1864static int 1865OperandSem_opnd_sem_immrx4_decode (uint32 *valp) 1866{ 1867 unsigned immrx4_out_0; 1868 unsigned immrx4_in_0; 1869 immrx4_in_0 = *valp & 0xf; 1870 immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; 1871 *valp = immrx4_out_0; 1872 return 0; 1873} 1874 1875static int 1876OperandSem_opnd_sem_immrx4_encode (uint32 *valp) 1877{ 1878 unsigned immrx4_in_0; 1879 unsigned immrx4_out_0; 1880 immrx4_out_0 = *valp; 1881 immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); 1882 *valp = immrx4_in_0; 1883 return 0; 1884} 1885 1886static int 1887OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) 1888{ 1889 unsigned lsi4x4_out_0; 1890 unsigned lsi4x4_in_0; 1891 lsi4x4_in_0 = *valp & 0xf; 1892 lsi4x4_out_0 = lsi4x4_in_0 << 2; 1893 *valp = lsi4x4_out_0; 1894 return 0; 1895} 1896 1897static int 1898OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) 1899{ 1900 unsigned lsi4x4_in_0; 1901 unsigned lsi4x4_out_0; 1902 lsi4x4_out_0 = *valp; 1903 lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); 1904 *valp = lsi4x4_in_0; 1905 return 0; 1906} 1907 1908static int 1909OperandSem_opnd_sem_simm7_decode (uint32 *valp) 1910{ 1911 unsigned simm7_out_0; 1912 unsigned simm7_in_0; 1913 simm7_in_0 = *valp & 0x7f; 1914 simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; 1915 *valp = simm7_out_0; 1916 return 0; 1917} 1918 1919static int 1920OperandSem_opnd_sem_simm7_encode (uint32 *valp) 1921{ 1922 unsigned simm7_in_0; 1923 unsigned simm7_out_0; 1924 simm7_out_0 = *valp; 1925 simm7_in_0 = (simm7_out_0 & 0x7f); 1926 *valp = simm7_in_0; 1927 return 0; 1928} 1929 1930static int 1931OperandSem_opnd_sem_uimm6_decode (uint32 *valp) 1932{ 1933 unsigned uimm6_out_0; 1934 unsigned uimm6_in_0; 1935 uimm6_in_0 = *valp & 0x3f; 1936 uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); 1937 *valp = uimm6_out_0; 1938 return 0; 1939} 1940 1941static int 1942OperandSem_opnd_sem_uimm6_encode (uint32 *valp) 1943{ 1944 unsigned uimm6_in_0; 1945 unsigned uimm6_out_0; 1946 uimm6_out_0 = *valp; 1947 uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; 1948 *valp = uimm6_in_0; 1949 return 0; 1950} 1951 1952static int 1953OperandSem_opnd_sem_ai4const_decode (uint32 *valp) 1954{ 1955 unsigned ai4const_out_0; 1956 unsigned ai4const_in_0; 1957 ai4const_in_0 = *valp & 0xf; 1958 ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; 1959 *valp = ai4const_out_0; 1960 return 0; 1961} 1962 1963static int 1964OperandSem_opnd_sem_ai4const_encode (uint32 *valp) 1965{ 1966 unsigned ai4const_in_0; 1967 unsigned ai4const_out_0; 1968 ai4const_out_0 = *valp; 1969 switch (ai4const_out_0) 1970 { 1971 case 0xffffffff: ai4const_in_0 = 0; break; 1972 case 0x1: ai4const_in_0 = 0x1; break; 1973 case 0x2: ai4const_in_0 = 0x2; break; 1974 case 0x3: ai4const_in_0 = 0x3; break; 1975 case 0x4: ai4const_in_0 = 0x4; break; 1976 case 0x5: ai4const_in_0 = 0x5; break; 1977 case 0x6: ai4const_in_0 = 0x6; break; 1978 case 0x7: ai4const_in_0 = 0x7; break; 1979 case 0x8: ai4const_in_0 = 0x8; break; 1980 case 0x9: ai4const_in_0 = 0x9; break; 1981 case 0xa: ai4const_in_0 = 0xa; break; 1982 case 0xb: ai4const_in_0 = 0xb; break; 1983 case 0xc: ai4const_in_0 = 0xc; break; 1984 case 0xd: ai4const_in_0 = 0xd; break; 1985 case 0xe: ai4const_in_0 = 0xe; break; 1986 default: ai4const_in_0 = 0xf; break; 1987 } 1988 *valp = ai4const_in_0; 1989 return 0; 1990} 1991 1992static int 1993OperandSem_opnd_sem_b4const_decode (uint32 *valp) 1994{ 1995 unsigned b4const_out_0; 1996 unsigned b4const_in_0; 1997 b4const_in_0 = *valp & 0xf; 1998 b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; 1999 *valp = b4const_out_0; 2000 return 0; 2001} 2002 2003static int 2004OperandSem_opnd_sem_b4const_encode (uint32 *valp) 2005{ 2006 unsigned b4const_in_0; 2007 unsigned b4const_out_0; 2008 b4const_out_0 = *valp; 2009 switch (b4const_out_0) 2010 { 2011 case 0xffffffff: b4const_in_0 = 0; break; 2012 case 0x1: b4const_in_0 = 0x1; break; 2013 case 0x2: b4const_in_0 = 0x2; break; 2014 case 0x3: b4const_in_0 = 0x3; break; 2015 case 0x4: b4const_in_0 = 0x4; break; 2016 case 0x5: b4const_in_0 = 0x5; break; 2017 case 0x6: b4const_in_0 = 0x6; break; 2018 case 0x7: b4const_in_0 = 0x7; break; 2019 case 0x8: b4const_in_0 = 0x8; break; 2020 case 0xa: b4const_in_0 = 0x9; break; 2021 case 0xc: b4const_in_0 = 0xa; break; 2022 case 0x10: b4const_in_0 = 0xb; break; 2023 case 0x20: b4const_in_0 = 0xc; break; 2024 case 0x40: b4const_in_0 = 0xd; break; 2025 case 0x80: b4const_in_0 = 0xe; break; 2026 default: b4const_in_0 = 0xf; break; 2027 } 2028 *valp = b4const_in_0; 2029 return 0; 2030} 2031 2032static int 2033OperandSem_opnd_sem_b4constu_decode (uint32 *valp) 2034{ 2035 unsigned b4constu_out_0; 2036 unsigned b4constu_in_0; 2037 b4constu_in_0 = *valp & 0xf; 2038 b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; 2039 *valp = b4constu_out_0; 2040 return 0; 2041} 2042 2043static int 2044OperandSem_opnd_sem_b4constu_encode (uint32 *valp) 2045{ 2046 unsigned b4constu_in_0; 2047 unsigned b4constu_out_0; 2048 b4constu_out_0 = *valp; 2049 switch (b4constu_out_0) 2050 { 2051 case 0x8000: b4constu_in_0 = 0; break; 2052 case 0x10000: b4constu_in_0 = 0x1; break; 2053 case 0x2: b4constu_in_0 = 0x2; break; 2054 case 0x3: b4constu_in_0 = 0x3; break; 2055 case 0x4: b4constu_in_0 = 0x4; break; 2056 case 0x5: b4constu_in_0 = 0x5; break; 2057 case 0x6: b4constu_in_0 = 0x6; break; 2058 case 0x7: b4constu_in_0 = 0x7; break; 2059 case 0x8: b4constu_in_0 = 0x8; break; 2060 case 0xa: b4constu_in_0 = 0x9; break; 2061 case 0xc: b4constu_in_0 = 0xa; break; 2062 case 0x10: b4constu_in_0 = 0xb; break; 2063 case 0x20: b4constu_in_0 = 0xc; break; 2064 case 0x40: b4constu_in_0 = 0xd; break; 2065 case 0x80: b4constu_in_0 = 0xe; break; 2066 default: b4constu_in_0 = 0xf; break; 2067 } 2068 *valp = b4constu_in_0; 2069 return 0; 2070} 2071 2072static int 2073OperandSem_opnd_sem_uimm8_decode (uint32 *valp) 2074{ 2075 unsigned uimm8_out_0; 2076 unsigned uimm8_in_0; 2077 uimm8_in_0 = *valp & 0xff; 2078 uimm8_out_0 = uimm8_in_0; 2079 *valp = uimm8_out_0; 2080 return 0; 2081} 2082 2083static int 2084OperandSem_opnd_sem_uimm8_encode (uint32 *valp) 2085{ 2086 unsigned uimm8_in_0; 2087 unsigned uimm8_out_0; 2088 uimm8_out_0 = *valp; 2089 uimm8_in_0 = (uimm8_out_0 & 0xff); 2090 *valp = uimm8_in_0; 2091 return 0; 2092} 2093 2094static int 2095OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) 2096{ 2097 unsigned uimm8x2_out_0; 2098 unsigned uimm8x2_in_0; 2099 uimm8x2_in_0 = *valp & 0xff; 2100 uimm8x2_out_0 = uimm8x2_in_0 << 1; 2101 *valp = uimm8x2_out_0; 2102 return 0; 2103} 2104 2105static int 2106OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) 2107{ 2108 unsigned uimm8x2_in_0; 2109 unsigned uimm8x2_out_0; 2110 uimm8x2_out_0 = *valp; 2111 uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); 2112 *valp = uimm8x2_in_0; 2113 return 0; 2114} 2115 2116static int 2117OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) 2118{ 2119 unsigned uimm8x4_out_0; 2120 unsigned uimm8x4_in_0; 2121 uimm8x4_in_0 = *valp & 0xff; 2122 uimm8x4_out_0 = uimm8x4_in_0 << 2; 2123 *valp = uimm8x4_out_0; 2124 return 0; 2125} 2126 2127static int 2128OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) 2129{ 2130 unsigned uimm8x4_in_0; 2131 unsigned uimm8x4_out_0; 2132 uimm8x4_out_0 = *valp; 2133 uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); 2134 *valp = uimm8x4_in_0; 2135 return 0; 2136} 2137 2138static int 2139OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) 2140{ 2141 unsigned uimm4x16_out_0; 2142 unsigned uimm4x16_in_0; 2143 uimm4x16_in_0 = *valp & 0xf; 2144 uimm4x16_out_0 = uimm4x16_in_0 << 4; 2145 *valp = uimm4x16_out_0; 2146 return 0; 2147} 2148 2149static int 2150OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) 2151{ 2152 unsigned uimm4x16_in_0; 2153 unsigned uimm4x16_out_0; 2154 uimm4x16_out_0 = *valp; 2155 uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); 2156 *valp = uimm4x16_in_0; 2157 return 0; 2158} 2159 2160static int 2161OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp) 2162{ 2163 unsigned uimmrx4_out_0; 2164 unsigned uimmrx4_in_0; 2165 uimmrx4_in_0 = *valp & 0xf; 2166 uimmrx4_out_0 = uimmrx4_in_0 << 2; 2167 *valp = uimmrx4_out_0; 2168 return 0; 2169} 2170 2171static int 2172OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp) 2173{ 2174 unsigned uimmrx4_in_0; 2175 unsigned uimmrx4_out_0; 2176 uimmrx4_out_0 = *valp; 2177 uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf); 2178 *valp = uimmrx4_in_0; 2179 return 0; 2180} 2181 2182static int 2183OperandSem_opnd_sem_simm8_decode (uint32 *valp) 2184{ 2185 unsigned simm8_out_0; 2186 unsigned simm8_in_0; 2187 simm8_in_0 = *valp & 0xff; 2188 simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; 2189 *valp = simm8_out_0; 2190 return 0; 2191} 2192 2193static int 2194OperandSem_opnd_sem_simm8_encode (uint32 *valp) 2195{ 2196 unsigned simm8_in_0; 2197 unsigned simm8_out_0; 2198 simm8_out_0 = *valp; 2199 simm8_in_0 = (simm8_out_0 & 0xff); 2200 *valp = simm8_in_0; 2201 return 0; 2202} 2203 2204static int 2205OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) 2206{ 2207 unsigned simm8x256_out_0; 2208 unsigned simm8x256_in_0; 2209 simm8x256_in_0 = *valp & 0xff; 2210 simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; 2211 *valp = simm8x256_out_0; 2212 return 0; 2213} 2214 2215static int 2216OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) 2217{ 2218 unsigned simm8x256_in_0; 2219 unsigned simm8x256_out_0; 2220 simm8x256_out_0 = *valp; 2221 simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); 2222 *valp = simm8x256_in_0; 2223 return 0; 2224} 2225 2226static int 2227OperandSem_opnd_sem_simm12b_decode (uint32 *valp) 2228{ 2229 unsigned simm12b_out_0; 2230 unsigned simm12b_in_0; 2231 simm12b_in_0 = *valp & 0xfff; 2232 simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; 2233 *valp = simm12b_out_0; 2234 return 0; 2235} 2236 2237static int 2238OperandSem_opnd_sem_simm12b_encode (uint32 *valp) 2239{ 2240 unsigned simm12b_in_0; 2241 unsigned simm12b_out_0; 2242 simm12b_out_0 = *valp; 2243 simm12b_in_0 = (simm12b_out_0 & 0xfff); 2244 *valp = simm12b_in_0; 2245 return 0; 2246} 2247 2248static int 2249OperandSem_opnd_sem_msalp32_decode (uint32 *valp) 2250{ 2251 unsigned msalp32_out_0; 2252 unsigned msalp32_in_0; 2253 msalp32_in_0 = *valp & 0x1f; 2254 msalp32_out_0 = 0x20 - msalp32_in_0; 2255 *valp = msalp32_out_0; 2256 return 0; 2257} 2258 2259static int 2260OperandSem_opnd_sem_msalp32_encode (uint32 *valp) 2261{ 2262 unsigned msalp32_in_0; 2263 unsigned msalp32_out_0; 2264 msalp32_out_0 = *valp; 2265 msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; 2266 *valp = msalp32_in_0; 2267 return 0; 2268} 2269 2270static int 2271OperandSem_opnd_sem_op2p1_decode (uint32 *valp) 2272{ 2273 unsigned op2p1_out_0; 2274 unsigned op2p1_in_0; 2275 op2p1_in_0 = *valp & 0xf; 2276 op2p1_out_0 = op2p1_in_0 + 0x1; 2277 *valp = op2p1_out_0; 2278 return 0; 2279} 2280 2281static int 2282OperandSem_opnd_sem_op2p1_encode (uint32 *valp) 2283{ 2284 unsigned op2p1_in_0; 2285 unsigned op2p1_out_0; 2286 op2p1_out_0 = *valp; 2287 op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; 2288 *valp = op2p1_in_0; 2289 return 0; 2290} 2291 2292static int 2293OperandSem_opnd_sem_label8_decode (uint32 *valp) 2294{ 2295 unsigned label8_out_0; 2296 unsigned label8_in_0; 2297 label8_in_0 = *valp & 0xff; 2298 label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); 2299 *valp = label8_out_0; 2300 return 0; 2301} 2302 2303static int 2304OperandSem_opnd_sem_label8_encode (uint32 *valp) 2305{ 2306 unsigned label8_in_0; 2307 unsigned label8_out_0; 2308 label8_out_0 = *valp; 2309 label8_in_0 = (label8_out_0 - 0x4) & 0xff; 2310 *valp = label8_in_0; 2311 return 0; 2312} 2313 2314static int 2315OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) 2316{ 2317 unsigned ulabel8_out_0; 2318 unsigned ulabel8_in_0; 2319 ulabel8_in_0 = *valp & 0xff; 2320 ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); 2321 *valp = ulabel8_out_0; 2322 return 0; 2323} 2324 2325static int 2326OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) 2327{ 2328 unsigned ulabel8_in_0; 2329 unsigned ulabel8_out_0; 2330 ulabel8_out_0 = *valp; 2331 ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; 2332 *valp = ulabel8_in_0; 2333 return 0; 2334} 2335 2336static int 2337OperandSem_opnd_sem_label12_decode (uint32 *valp) 2338{ 2339 unsigned label12_out_0; 2340 unsigned label12_in_0; 2341 label12_in_0 = *valp & 0xfff; 2342 label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); 2343 *valp = label12_out_0; 2344 return 0; 2345} 2346 2347static int 2348OperandSem_opnd_sem_label12_encode (uint32 *valp) 2349{ 2350 unsigned label12_in_0; 2351 unsigned label12_out_0; 2352 label12_out_0 = *valp; 2353 label12_in_0 = (label12_out_0 - 0x4) & 0xfff; 2354 *valp = label12_in_0; 2355 return 0; 2356} 2357 2358static int 2359OperandSem_opnd_sem_soffset_decode (uint32 *valp) 2360{ 2361 unsigned soffset_out_0; 2362 unsigned soffset_in_0; 2363 soffset_in_0 = *valp & 0x3ffff; 2364 soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); 2365 *valp = soffset_out_0; 2366 return 0; 2367} 2368 2369static int 2370OperandSem_opnd_sem_soffset_encode (uint32 *valp) 2371{ 2372 unsigned soffset_in_0; 2373 unsigned soffset_out_0; 2374 soffset_out_0 = *valp; 2375 soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; 2376 *valp = soffset_in_0; 2377 return 0; 2378} 2379 2380static int 2381OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) 2382{ 2383 unsigned uimm16x4_out_0; 2384 unsigned uimm16x4_in_0; 2385 uimm16x4_in_0 = *valp & 0xffff; 2386 uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; 2387 *valp = uimm16x4_out_0; 2388 return 0; 2389} 2390 2391static int 2392OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) 2393{ 2394 unsigned uimm16x4_in_0; 2395 unsigned uimm16x4_out_0; 2396 uimm16x4_out_0 = *valp; 2397 uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; 2398 *valp = uimm16x4_in_0; 2399 return 0; 2400} 2401 2402static int 2403OperandSem_opnd_sem_bbi_decode (uint32 *valp) 2404{ 2405 unsigned bbi_out_0; 2406 unsigned bbi_in_0; 2407 bbi_in_0 = *valp & 0x1f; 2408 bbi_out_0 = (0 << 5) | bbi_in_0; 2409 *valp = bbi_out_0; 2410 return 0; 2411} 2412 2413static int 2414OperandSem_opnd_sem_bbi_encode (uint32 *valp) 2415{ 2416 unsigned bbi_in_0; 2417 unsigned bbi_out_0; 2418 bbi_out_0 = *valp; 2419 bbi_in_0 = (bbi_out_0 & 0x1f); 2420 *valp = bbi_in_0; 2421 return 0; 2422} 2423 2424static int 2425OperandSem_opnd_sem_s_decode (uint32 *valp) 2426{ 2427 unsigned s_out_0; 2428 unsigned s_in_0; 2429 s_in_0 = *valp & 0xf; 2430 s_out_0 = (0 << 4) | s_in_0; 2431 *valp = s_out_0; 2432 return 0; 2433} 2434 2435static int 2436OperandSem_opnd_sem_s_encode (uint32 *valp) 2437{ 2438 unsigned s_in_0; 2439 unsigned s_out_0; 2440 s_out_0 = *valp; 2441 s_in_0 = (s_out_0 & 0xf); 2442 *valp = s_in_0; 2443 return 0; 2444} 2445 2446static int 2447OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED) 2448{ 2449 return 0; 2450} 2451 2452static int 2453OperandSem_opnd_sem_MR_encode (uint32 *valp) 2454{ 2455 return (*valp >= 4); 2456} 2457 2458static int 2459OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) 2460{ 2461 return 0; 2462} 2463 2464static int 2465OperandSem_opnd_sem_MR_1_encode (uint32 *valp) 2466{ 2467 return (*valp >= 4); 2468} 2469 2470static int 2471OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) 2472{ 2473 return 0; 2474} 2475 2476static int 2477OperandSem_opnd_sem_MR_2_encode (uint32 *valp) 2478{ 2479 return (*valp >= 4); 2480} 2481 2482static int 2483OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) 2484{ 2485 return 0; 2486} 2487 2488static int 2489OperandSem_opnd_sem_MR_3_encode (uint32 *valp) 2490{ 2491 return (*valp >= 4); 2492} 2493 2494static int 2495OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) 2496{ 2497 return 0; 2498} 2499 2500static int 2501OperandSem_opnd_sem_MR_4_encode (uint32 *valp) 2502{ 2503 return (*valp >= 4); 2504} 2505 2506static int 2507OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED) 2508{ 2509 return 0; 2510} 2511 2512static int 2513OperandSem_opnd_sem_MR_5_encode (uint32 *valp) 2514{ 2515 return (*valp >= 4); 2516} 2517 2518static int 2519OperandSem_opnd_sem_immt_decode (uint32 *valp) 2520{ 2521 unsigned immt_out_0; 2522 unsigned immt_in_0; 2523 immt_in_0 = *valp & 0xf; 2524 immt_out_0 = immt_in_0; 2525 *valp = immt_out_0; 2526 return 0; 2527} 2528 2529static int 2530OperandSem_opnd_sem_immt_encode (uint32 *valp) 2531{ 2532 unsigned immt_in_0; 2533 unsigned immt_out_0; 2534 immt_out_0 = *valp; 2535 immt_in_0 = immt_out_0 & 0xf; 2536 *valp = immt_in_0; 2537 return 0; 2538} 2539 2540static int 2541OperandSem_opnd_sem_tp7_decode (uint32 *valp) 2542{ 2543 unsigned tp7_out_0; 2544 unsigned tp7_in_0; 2545 tp7_in_0 = *valp & 0xf; 2546 tp7_out_0 = tp7_in_0 + 0x7; 2547 *valp = tp7_out_0; 2548 return 0; 2549} 2550 2551static int 2552OperandSem_opnd_sem_tp7_encode (uint32 *valp) 2553{ 2554 unsigned tp7_in_0; 2555 unsigned tp7_out_0; 2556 tp7_out_0 = *valp; 2557 tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; 2558 *valp = tp7_in_0; 2559 return 0; 2560} 2561 2562static int 2563OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) 2564{ 2565 unsigned xt_wbr15_label_out_0; 2566 unsigned xt_wbr15_label_in_0; 2567 xt_wbr15_label_in_0 = *valp & 0x7fff; 2568 xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); 2569 *valp = xt_wbr15_label_out_0; 2570 return 0; 2571} 2572 2573static int 2574OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) 2575{ 2576 unsigned xt_wbr15_label_in_0; 2577 unsigned xt_wbr15_label_out_0; 2578 xt_wbr15_label_out_0 = *valp; 2579 xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; 2580 *valp = xt_wbr15_label_in_0; 2581 return 0; 2582} 2583 2584static int 2585OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp) 2586{ 2587 unsigned xt_wbr18_label_out_0; 2588 unsigned xt_wbr18_label_in_0; 2589 xt_wbr18_label_in_0 = *valp & 0x3ffff; 2590 xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14); 2591 *valp = xt_wbr18_label_out_0; 2592 return 0; 2593} 2594 2595static int 2596OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp) 2597{ 2598 unsigned xt_wbr18_label_in_0; 2599 unsigned xt_wbr18_label_out_0; 2600 xt_wbr18_label_out_0 = *valp; 2601 xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff; 2602 *valp = xt_wbr18_label_in_0; 2603 return 0; 2604} 2605 2606static int 2607OperandSem_opnd_sem_bitindex_decode (uint32 *valp) 2608{ 2609 unsigned bitindex_out_0; 2610 unsigned bitindex_in_0; 2611 bitindex_in_0 = *valp & 0x1f; 2612 bitindex_out_0 = (0 << 5) | bitindex_in_0; 2613 *valp = bitindex_out_0; 2614 return 0; 2615} 2616 2617static int 2618OperandSem_opnd_sem_bitindex_encode (uint32 *valp) 2619{ 2620 unsigned bitindex_in_0; 2621 unsigned bitindex_out_0; 2622 bitindex_out_0 = *valp; 2623 bitindex_in_0 = (bitindex_out_0 & 0x1f); 2624 *valp = bitindex_in_0; 2625 return 0; 2626} 2627 2628static int 2629Operand_soffsetx4_ator (uint32 *valp, uint32 pc) 2630{ 2631 *valp -= (pc & ~0x3); 2632 return 0; 2633} 2634 2635static int 2636Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) 2637{ 2638 *valp += (pc & ~0x3); 2639 return 0; 2640} 2641 2642static int 2643Operand_uimm6_ator (uint32 *valp, uint32 pc) 2644{ 2645 *valp -= pc; 2646 return 0; 2647} 2648 2649static int 2650Operand_uimm6_rtoa (uint32 *valp, uint32 pc) 2651{ 2652 *valp += pc; 2653 return 0; 2654} 2655 2656static int 2657Operand_label8_ator (uint32 *valp, uint32 pc) 2658{ 2659 *valp -= pc; 2660 return 0; 2661} 2662 2663static int 2664Operand_label8_rtoa (uint32 *valp, uint32 pc) 2665{ 2666 *valp += pc; 2667 return 0; 2668} 2669 2670static int 2671Operand_ulabel8_ator (uint32 *valp, uint32 pc) 2672{ 2673 *valp -= pc; 2674 return 0; 2675} 2676 2677static int 2678Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) 2679{ 2680 *valp += pc; 2681 return 0; 2682} 2683 2684static int 2685Operand_label12_ator (uint32 *valp, uint32 pc) 2686{ 2687 *valp -= pc; 2688 return 0; 2689} 2690 2691static int 2692Operand_label12_rtoa (uint32 *valp, uint32 pc) 2693{ 2694 *valp += pc; 2695 return 0; 2696} 2697 2698static int 2699Operand_soffset_ator (uint32 *valp, uint32 pc) 2700{ 2701 *valp -= pc; 2702 return 0; 2703} 2704 2705static int 2706Operand_soffset_rtoa (uint32 *valp, uint32 pc) 2707{ 2708 *valp += pc; 2709 return 0; 2710} 2711 2712static int 2713Operand_uimm16x4_ator (uint32 *valp, uint32 pc) 2714{ 2715 *valp -= ((pc + 3) & ~0x3); 2716 return 0; 2717} 2718 2719static int 2720Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) 2721{ 2722 *valp += ((pc + 3) & ~0x3); 2723 return 0; 2724} 2725 2726static int 2727Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) 2728{ 2729 *valp -= pc; 2730 return 0; 2731} 2732 2733static int 2734Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) 2735{ 2736 *valp += pc; 2737 return 0; 2738} 2739 2740static int 2741Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) 2742{ 2743 *valp -= pc; 2744 return 0; 2745} 2746 2747static int 2748Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) 2749{ 2750 *valp += pc; 2751 return 0; 2752} 2753 2754static xtensa_operand_internal operands[] = { 2755 { "soffsetx4", FIELD_offset, -1, 0, 2756 XTENSA_OPERAND_IS_PCRELATIVE, 2757 OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, 2758 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, 2759 { "uimm12x8", FIELD_imm12, -1, 0, 2760 0, 2761 OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, 2762 0, 0 }, 2763 { "simm4", FIELD_mn, -1, 0, 2764 0, 2765 OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, 2766 0, 0 }, 2767 { "arr", FIELD_r, REGFILE_AR, 1, 2768 XTENSA_OPERAND_IS_REGISTER, 2769 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 2770 0, 0 }, 2771 { "ars", FIELD_s, REGFILE_AR, 1, 2772 XTENSA_OPERAND_IS_REGISTER, 2773 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 2774 0, 0 }, 2775 { "*ars_invisible", FIELD_s, REGFILE_AR, 1, 2776 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2777 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 2778 0, 0 }, 2779 { "art", FIELD_t, REGFILE_AR, 1, 2780 XTENSA_OPERAND_IS_REGISTER, 2781 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 2782 0, 0 }, 2783 { "ar0", FIELD__ar0, REGFILE_AR, 1, 2784 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2785 OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, 2786 0, 0 }, 2787 { "ar4", FIELD__ar4, REGFILE_AR, 1, 2788 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2789 OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, 2790 0, 0 }, 2791 { "ar8", FIELD__ar8, REGFILE_AR, 1, 2792 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2793 OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, 2794 0, 0 }, 2795 { "ar12", FIELD__ar12, REGFILE_AR, 1, 2796 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2797 OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, 2798 0, 0 }, 2799 { "ars_entry", FIELD_s, REGFILE_AR, 1, 2800 XTENSA_OPERAND_IS_REGISTER, 2801 OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, 2802 0, 0 }, 2803 { "immrx4", FIELD_r, -1, 0, 2804 0, 2805 OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, 2806 0, 0 }, 2807 { "lsi4x4", FIELD_r, -1, 0, 2808 0, 2809 OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, 2810 0, 0 }, 2811 { "simm7", FIELD_imm7, -1, 0, 2812 0, 2813 OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, 2814 0, 0 }, 2815 { "uimm6", FIELD_imm6, -1, 0, 2816 XTENSA_OPERAND_IS_PCRELATIVE, 2817 OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, 2818 Operand_uimm6_ator, Operand_uimm6_rtoa }, 2819 { "ai4const", FIELD_t, -1, 0, 2820 0, 2821 OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, 2822 0, 0 }, 2823 { "b4const", FIELD_r, -1, 0, 2824 0, 2825 OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, 2826 0, 0 }, 2827 { "b4constu", FIELD_r, -1, 0, 2828 0, 2829 OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, 2830 0, 0 }, 2831 { "uimm8", FIELD_imm8, -1, 0, 2832 0, 2833 OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, 2834 0, 0 }, 2835 { "uimm8x2", FIELD_imm8, -1, 0, 2836 0, 2837 OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, 2838 0, 0 }, 2839 { "uimm8x4", FIELD_imm8, -1, 0, 2840 0, 2841 OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, 2842 0, 0 }, 2843 { "uimm4x16", FIELD_op2, -1, 0, 2844 0, 2845 OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, 2846 0, 0 }, 2847 { "uimmrx4", FIELD_r, -1, 0, 2848 0, 2849 OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode, 2850 0, 0 }, 2851 { "simm8", FIELD_imm8, -1, 0, 2852 0, 2853 OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, 2854 0, 0 }, 2855 { "simm8x256", FIELD_imm8, -1, 0, 2856 0, 2857 OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, 2858 0, 0 }, 2859 { "simm12b", FIELD_imm12b, -1, 0, 2860 0, 2861 OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, 2862 0, 0 }, 2863 { "msalp32", FIELD_sal, -1, 0, 2864 0, 2865 OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, 2866 0, 0 }, 2867 { "op2p1", FIELD_op2, -1, 0, 2868 0, 2869 OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, 2870 0, 0 }, 2871 { "label8", FIELD_imm8, -1, 0, 2872 XTENSA_OPERAND_IS_PCRELATIVE, 2873 OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, 2874 Operand_label8_ator, Operand_label8_rtoa }, 2875 { "ulabel8", FIELD_imm8, -1, 0, 2876 XTENSA_OPERAND_IS_PCRELATIVE, 2877 OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, 2878 Operand_ulabel8_ator, Operand_ulabel8_rtoa }, 2879 { "label12", FIELD_imm12, -1, 0, 2880 XTENSA_OPERAND_IS_PCRELATIVE, 2881 OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, 2882 Operand_label12_ator, Operand_label12_rtoa }, 2883 { "soffset", FIELD_offset, -1, 0, 2884 XTENSA_OPERAND_IS_PCRELATIVE, 2885 OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, 2886 Operand_soffset_ator, Operand_soffset_rtoa }, 2887 { "uimm16x4", FIELD_imm16, -1, 0, 2888 XTENSA_OPERAND_IS_PCRELATIVE, 2889 OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, 2890 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, 2891 { "bbi", FIELD_bbi, -1, 0, 2892 0, 2893 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, 2894 0, 0 }, 2895 { "sae", FIELD_sae, -1, 0, 2896 0, 2897 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, 2898 0, 0 }, 2899 { "sas", FIELD_sas, -1, 0, 2900 0, 2901 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, 2902 0, 0 }, 2903 { "sargt", FIELD_sargt, -1, 0, 2904 0, 2905 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, 2906 0, 0 }, 2907 { "s", FIELD_s, -1, 0, 2908 0, 2909 OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, 2910 0, 0 }, 2911 { "mx", FIELD_x, REGFILE_MR, 1, 2912 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, 2913 OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode, 2914 0, 0 }, 2915 { "my", FIELD_y, REGFILE_MR, 1, 2916 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, 2917 OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode, 2918 0, 0 }, 2919 { "mw", FIELD_w, REGFILE_MR, 1, 2920 XTENSA_OPERAND_IS_REGISTER, 2921 OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode, 2922 0, 0 }, 2923 { "mr0", FIELD__mr0, REGFILE_MR, 1, 2924 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2925 OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode, 2926 0, 0 }, 2927 { "mr1", FIELD__mr1, REGFILE_MR, 1, 2928 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2929 OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode, 2930 0, 0 }, 2931 { "mr2", FIELD__mr2, REGFILE_MR, 1, 2932 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2933 OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode, 2934 0, 0 }, 2935 { "mr3", FIELD__mr3, REGFILE_MR, 1, 2936 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 2937 OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode, 2938 0, 0 }, 2939 { "immt", FIELD_t, -1, 0, 2940 0, 2941 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, 2942 0, 0 }, 2943 { "imms", FIELD_s, -1, 0, 2944 0, 2945 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, 2946 0, 0 }, 2947 { "tp7", FIELD_t, -1, 0, 2948 0, 2949 OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, 2950 0, 0 }, 2951 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, 2952 XTENSA_OPERAND_IS_PCRELATIVE, 2953 OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, 2954 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, 2955 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, 2956 XTENSA_OPERAND_IS_PCRELATIVE, 2957 OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode, 2958 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, 2959 { "bitindex", FIELD_bitindex, -1, 0, 2960 0, 2961 OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode, 2962 0, 0 }, 2963 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, 2964 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, 2965 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, 2966 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, 2967 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, 2968 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, 2969 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, 2970 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, 2971 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, 2972 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, 2973 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, 2974 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, 2975 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, 2976 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, 2977 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, 2978 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, 2979 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, 2980 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, 2981 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, 2982 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, 2983 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, 2984 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, 2985 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, 2986 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, 2987 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, 2988 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, 2989 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, 2990 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, 2991 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, 2992 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, 2993 { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, 2994 { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, 2995 { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, 2996 { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, 2997 { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, 2998 { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, 2999 { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, 3000 { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, 3001 { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, 3002 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, 3003 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, 3004 { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } 3005}; 3006 3007enum xtensa_operand_id { 3008 OPERAND_soffsetx4, 3009 OPERAND_uimm12x8, 3010 OPERAND_simm4, 3011 OPERAND_arr, 3012 OPERAND_ars, 3013 OPERAND__ars_invisible, 3014 OPERAND_art, 3015 OPERAND_ar0, 3016 OPERAND_ar4, 3017 OPERAND_ar8, 3018 OPERAND_ar12, 3019 OPERAND_ars_entry, 3020 OPERAND_immrx4, 3021 OPERAND_lsi4x4, 3022 OPERAND_simm7, 3023 OPERAND_uimm6, 3024 OPERAND_ai4const, 3025 OPERAND_b4const, 3026 OPERAND_b4constu, 3027 OPERAND_uimm8, 3028 OPERAND_uimm8x2, 3029 OPERAND_uimm8x4, 3030 OPERAND_uimm4x16, 3031 OPERAND_uimmrx4, 3032 OPERAND_simm8, 3033 OPERAND_simm8x256, 3034 OPERAND_simm12b, 3035 OPERAND_msalp32, 3036 OPERAND_op2p1, 3037 OPERAND_label8, 3038 OPERAND_ulabel8, 3039 OPERAND_label12, 3040 OPERAND_soffset, 3041 OPERAND_uimm16x4, 3042 OPERAND_bbi, 3043 OPERAND_sae, 3044 OPERAND_sas, 3045 OPERAND_sargt, 3046 OPERAND_s, 3047 OPERAND_mx, 3048 OPERAND_my, 3049 OPERAND_mw, 3050 OPERAND_mr0, 3051 OPERAND_mr1, 3052 OPERAND_mr2, 3053 OPERAND_mr3, 3054 OPERAND_immt, 3055 OPERAND_imms, 3056 OPERAND_tp7, 3057 OPERAND_xt_wbr15_label, 3058 OPERAND_xt_wbr18_label, 3059 OPERAND_bitindex, 3060 OPERAND_t, 3061 OPERAND_bbi4, 3062 OPERAND_imm12, 3063 OPERAND_imm8, 3064 OPERAND_imm12b, 3065 OPERAND_imm16, 3066 OPERAND_m, 3067 OPERAND_n, 3068 OPERAND_offset, 3069 OPERAND_op0, 3070 OPERAND_op1, 3071 OPERAND_op2, 3072 OPERAND_r, 3073 OPERAND_sa4, 3074 OPERAND_sae4, 3075 OPERAND_sal, 3076 OPERAND_sas4, 3077 OPERAND_sr, 3078 OPERAND_st, 3079 OPERAND_thi3, 3080 OPERAND_imm4, 3081 OPERAND_mn, 3082 OPERAND_i, 3083 OPERAND_imm6lo, 3084 OPERAND_imm6hi, 3085 OPERAND_imm7lo, 3086 OPERAND_imm7hi, 3087 OPERAND_z, 3088 OPERAND_imm6, 3089 OPERAND_imm7, 3090 OPERAND_r3, 3091 OPERAND_rbit2, 3092 OPERAND_rhi, 3093 OPERAND_t3, 3094 OPERAND_tbit2, 3095 OPERAND_tlo, 3096 OPERAND_w, 3097 OPERAND_y, 3098 OPERAND_x, 3099 OPERAND_xt_wbr15_imm, 3100 OPERAND_xt_wbr18_imm, 3101 OPERAND_s3to1 3102}; 3103 3104 3105/* Iclass table. */ 3106 3107static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { 3108 { { STATE_PSEXCM }, 'o' }, 3109 { { STATE_EPC1 }, 'i' } 3110}; 3111 3112static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { 3113 { { STATE_DEPC }, 'i' } 3114}; 3115 3116static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { 3117 { { OPERAND_soffsetx4 }, 'i' }, 3118 { { OPERAND_ar12 }, 'o' } 3119}; 3120 3121static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { 3122 { { STATE_PSCALLINC }, 'o' } 3123}; 3124 3125static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { 3126 { { OPERAND_soffsetx4 }, 'i' }, 3127 { { OPERAND_ar8 }, 'o' } 3128}; 3129 3130static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { 3131 { { STATE_PSCALLINC }, 'o' } 3132}; 3133 3134static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { 3135 { { OPERAND_soffsetx4 }, 'i' }, 3136 { { OPERAND_ar4 }, 'o' } 3137}; 3138 3139static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { 3140 { { STATE_PSCALLINC }, 'o' } 3141}; 3142 3143static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { 3144 { { OPERAND_ars }, 'i' }, 3145 { { OPERAND_ar12 }, 'o' } 3146}; 3147 3148static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { 3149 { { STATE_PSCALLINC }, 'o' } 3150}; 3151 3152static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { 3153 { { OPERAND_ars }, 'i' }, 3154 { { OPERAND_ar8 }, 'o' } 3155}; 3156 3157static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { 3158 { { STATE_PSCALLINC }, 'o' } 3159}; 3160 3161static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { 3162 { { OPERAND_ars }, 'i' }, 3163 { { OPERAND_ar4 }, 'o' } 3164}; 3165 3166static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { 3167 { { STATE_PSCALLINC }, 'o' } 3168}; 3169 3170static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { 3171 { { OPERAND_ars_entry }, 's' }, 3172 { { OPERAND_ars }, 'i' }, 3173 { { OPERAND_uimm12x8 }, 'i' } 3174}; 3175 3176static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { 3177 { { STATE_PSCALLINC }, 'i' }, 3178 { { STATE_PSEXCM }, 'i' }, 3179 { { STATE_PSWOE }, 'i' }, 3180 { { STATE_WindowBase }, 'm' }, 3181 { { STATE_WindowStart }, 'm' } 3182}; 3183 3184static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { 3185 { { OPERAND_art }, 'o' }, 3186 { { OPERAND_ars }, 'i' } 3187}; 3188 3189static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { 3190 { { STATE_WindowBase }, 'i' }, 3191 { { STATE_WindowStart }, 'i' } 3192}; 3193 3194static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { 3195 { { OPERAND_simm4 }, 'i' } 3196}; 3197 3198static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { 3199 { { STATE_WindowBase }, 'm' } 3200}; 3201 3202static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { 3203 { { OPERAND__ars_invisible }, 'i' } 3204}; 3205 3206static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { 3207 { { STATE_WindowBase }, 'm' }, 3208 { { STATE_WindowStart }, 'm' }, 3209 { { STATE_PSCALLINC }, 'o' }, 3210 { { STATE_PSEXCM }, 'i' }, 3211 { { STATE_PSWOE }, 'i' } 3212}; 3213 3214static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { 3215 { { STATE_EPC1 }, 'i' }, 3216 { { STATE_PSEXCM }, 'o' }, 3217 { { STATE_WindowBase }, 'm' }, 3218 { { STATE_WindowStart }, 'm' }, 3219 { { STATE_PSOWB }, 'i' } 3220}; 3221 3222static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { 3223 { { OPERAND_art }, 'o' }, 3224 { { OPERAND_ars }, 'i' }, 3225 { { OPERAND_immrx4 }, 'i' } 3226}; 3227 3228static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { 3229 { { OPERAND_art }, 'i' }, 3230 { { OPERAND_ars }, 'i' }, 3231 { { OPERAND_immrx4 }, 'i' } 3232}; 3233 3234static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { 3235 { { OPERAND_art }, 'o' } 3236}; 3237 3238static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { 3239 { { STATE_WindowBase }, 'i' } 3240}; 3241 3242static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { 3243 { { OPERAND_art }, 'i' } 3244}; 3245 3246static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { 3247 { { STATE_WindowBase }, 'o' } 3248}; 3249 3250static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { 3251 { { OPERAND_art }, 'm' } 3252}; 3253 3254static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { 3255 { { STATE_WindowBase }, 'm' } 3256}; 3257 3258static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { 3259 { { OPERAND_art }, 'o' } 3260}; 3261 3262static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { 3263 { { STATE_WindowStart }, 'i' } 3264}; 3265 3266static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { 3267 { { OPERAND_art }, 'i' } 3268}; 3269 3270static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { 3271 { { STATE_WindowStart }, 'o' } 3272}; 3273 3274static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { 3275 { { OPERAND_art }, 'm' } 3276}; 3277 3278static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { 3279 { { STATE_WindowStart }, 'm' } 3280}; 3281 3282static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { 3283 { { OPERAND_arr }, 'o' }, 3284 { { OPERAND_ars }, 'i' }, 3285 { { OPERAND_art }, 'i' } 3286}; 3287 3288static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { 3289 { { OPERAND_arr }, 'o' }, 3290 { { OPERAND_ars }, 'i' }, 3291 { { OPERAND_ai4const }, 'i' } 3292}; 3293 3294static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { 3295 { { OPERAND_ars }, 'i' }, 3296 { { OPERAND_uimm6 }, 'i' } 3297}; 3298 3299static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { 3300 { { OPERAND_art }, 'o' }, 3301 { { OPERAND_ars }, 'i' }, 3302 { { OPERAND_lsi4x4 }, 'i' } 3303}; 3304 3305static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { 3306 { { OPERAND_art }, 'o' }, 3307 { { OPERAND_ars }, 'i' } 3308}; 3309 3310static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { 3311 { { OPERAND_ars }, 'o' }, 3312 { { OPERAND_simm7 }, 'i' } 3313}; 3314 3315static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { 3316 { { OPERAND__ars_invisible }, 'i' } 3317}; 3318 3319static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { 3320 { { OPERAND_art }, 'i' }, 3321 { { OPERAND_ars }, 'i' }, 3322 { { OPERAND_lsi4x4 }, 'i' } 3323}; 3324 3325static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { 3326 { { OPERAND_art }, 'o' }, 3327 { { OPERAND_ars }, 'i' }, 3328 { { OPERAND_simm8 }, 'i' } 3329}; 3330 3331static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { 3332 { { OPERAND_art }, 'o' }, 3333 { { OPERAND_ars }, 'i' }, 3334 { { OPERAND_simm8x256 }, 'i' } 3335}; 3336 3337static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { 3338 { { OPERAND_arr }, 'o' }, 3339 { { OPERAND_ars }, 'i' }, 3340 { { OPERAND_art }, 'i' } 3341}; 3342 3343static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { 3344 { { OPERAND_arr }, 'o' }, 3345 { { OPERAND_ars }, 'i' }, 3346 { { OPERAND_art }, 'i' } 3347}; 3348 3349static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { 3350 { { OPERAND_ars }, 'i' }, 3351 { { OPERAND_b4const }, 'i' }, 3352 { { OPERAND_label8 }, 'i' } 3353}; 3354 3355static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { 3356 { { OPERAND_ars }, 'i' }, 3357 { { OPERAND_bbi }, 'i' }, 3358 { { OPERAND_label8 }, 'i' } 3359}; 3360 3361static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { 3362 { { OPERAND_ars }, 'i' }, 3363 { { OPERAND_b4constu }, 'i' }, 3364 { { OPERAND_label8 }, 'i' } 3365}; 3366 3367static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { 3368 { { OPERAND_ars }, 'i' }, 3369 { { OPERAND_art }, 'i' }, 3370 { { OPERAND_label8 }, 'i' } 3371}; 3372 3373static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { 3374 { { OPERAND_ars }, 'i' }, 3375 { { OPERAND_label12 }, 'i' } 3376}; 3377 3378static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { 3379 { { OPERAND_soffsetx4 }, 'i' }, 3380 { { OPERAND_ar0 }, 'o' } 3381}; 3382 3383static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { 3384 { { OPERAND_ars }, 'i' }, 3385 { { OPERAND_ar0 }, 'o' } 3386}; 3387 3388static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { 3389 { { OPERAND_arr }, 'o' }, 3390 { { OPERAND_art }, 'i' }, 3391 { { OPERAND_sae }, 'i' }, 3392 { { OPERAND_op2p1 }, 'i' } 3393}; 3394 3395static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { 3396 { { OPERAND_soffset }, 'i' } 3397}; 3398 3399static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { 3400 { { OPERAND_ars }, 'i' } 3401}; 3402 3403static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { 3404 { { OPERAND_art }, 'o' }, 3405 { { OPERAND_ars }, 'i' }, 3406 { { OPERAND_uimm8x2 }, 'i' } 3407}; 3408 3409static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { 3410 { { OPERAND_art }, 'o' }, 3411 { { OPERAND_ars }, 'i' }, 3412 { { OPERAND_uimm8x2 }, 'i' } 3413}; 3414 3415static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { 3416 { { OPERAND_art }, 'o' }, 3417 { { OPERAND_ars }, 'i' }, 3418 { { OPERAND_uimm8x4 }, 'i' } 3419}; 3420 3421static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { 3422 { { OPERAND_art }, 'o' }, 3423 { { OPERAND_uimm16x4 }, 'i' } 3424}; 3425 3426static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { 3427 { { OPERAND_art }, 'o' }, 3428 { { OPERAND_ars }, 'i' }, 3429 { { OPERAND_uimm8 }, 'i' } 3430}; 3431 3432static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { 3433 { { OPERAND_ars }, 'i' }, 3434 { { OPERAND_ulabel8 }, 'i' } 3435}; 3436 3437static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { 3438 { { STATE_LBEG }, 'o' }, 3439 { { STATE_LEND }, 'o' }, 3440 { { STATE_LCOUNT }, 'o' } 3441}; 3442 3443static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { 3444 { { OPERAND_ars }, 'i' }, 3445 { { OPERAND_ulabel8 }, 'i' } 3446}; 3447 3448static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { 3449 { { STATE_LBEG }, 'o' }, 3450 { { STATE_LEND }, 'o' }, 3451 { { STATE_LCOUNT }, 'o' } 3452}; 3453 3454static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { 3455 { { OPERAND_art }, 'o' }, 3456 { { OPERAND_simm12b }, 'i' } 3457}; 3458 3459static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { 3460 { { OPERAND_arr }, 'm' }, 3461 { { OPERAND_ars }, 'i' }, 3462 { { OPERAND_art }, 'i' } 3463}; 3464 3465static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { 3466 { { OPERAND_arr }, 'o' }, 3467 { { OPERAND_art }, 'i' } 3468}; 3469 3470static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { 3471 { { OPERAND__ars_invisible }, 'i' } 3472}; 3473 3474static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { 3475 { { OPERAND_art }, 'i' }, 3476 { { OPERAND_ars }, 'i' }, 3477 { { OPERAND_uimm8x2 }, 'i' } 3478}; 3479 3480static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { 3481 { { OPERAND_art }, 'i' }, 3482 { { OPERAND_ars }, 'i' }, 3483 { { OPERAND_uimm8x4 }, 'i' } 3484}; 3485 3486static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { 3487 { { OPERAND_art }, 'i' }, 3488 { { OPERAND_ars }, 'i' }, 3489 { { OPERAND_uimmrx4 }, 'i' } 3490}; 3491 3492static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { 3493 { { OPERAND_art }, 'i' }, 3494 { { OPERAND_ars }, 'i' }, 3495 { { OPERAND_uimm8 }, 'i' } 3496}; 3497 3498static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { 3499 { { OPERAND_ars }, 'i' } 3500}; 3501 3502static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { 3503 { { STATE_SAR }, 'o' } 3504}; 3505 3506static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { 3507 { { OPERAND_sas }, 'i' } 3508}; 3509 3510static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { 3511 { { STATE_SAR }, 'o' } 3512}; 3513 3514static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { 3515 { { OPERAND_arr }, 'o' }, 3516 { { OPERAND_ars }, 'i' } 3517}; 3518 3519static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { 3520 { { STATE_SAR }, 'i' } 3521}; 3522 3523static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { 3524 { { OPERAND_arr }, 'o' }, 3525 { { OPERAND_ars }, 'i' }, 3526 { { OPERAND_art }, 'i' } 3527}; 3528 3529static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { 3530 { { STATE_SAR }, 'i' } 3531}; 3532 3533static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { 3534 { { OPERAND_arr }, 'o' }, 3535 { { OPERAND_art }, 'i' } 3536}; 3537 3538static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { 3539 { { STATE_SAR }, 'i' } 3540}; 3541 3542static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { 3543 { { OPERAND_arr }, 'o' }, 3544 { { OPERAND_ars }, 'i' }, 3545 { { OPERAND_msalp32 }, 'i' } 3546}; 3547 3548static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { 3549 { { OPERAND_arr }, 'o' }, 3550 { { OPERAND_art }, 'i' }, 3551 { { OPERAND_sargt }, 'i' } 3552}; 3553 3554static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { 3555 { { OPERAND_arr }, 'o' }, 3556 { { OPERAND_art }, 'i' }, 3557 { { OPERAND_s }, 'i' } 3558}; 3559 3560static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { 3561 { { STATE_XTSYNC }, 'i' } 3562}; 3563 3564static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { 3565 { { OPERAND_art }, 'o' }, 3566 { { OPERAND_s }, 'i' } 3567}; 3568 3569static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { 3570 { { STATE_PSWOE }, 'i' }, 3571 { { STATE_PSCALLINC }, 'i' }, 3572 { { STATE_PSOWB }, 'i' }, 3573 { { STATE_PSUM }, 'i' }, 3574 { { STATE_PSEXCM }, 'i' }, 3575 { { STATE_PSINTLEVEL }, 'm' } 3576}; 3577 3578static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { 3579 { { OPERAND_art }, 'o' } 3580}; 3581 3582static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { 3583 { { STATE_LEND }, 'i' } 3584}; 3585 3586static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { 3587 { { OPERAND_art }, 'i' } 3588}; 3589 3590static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { 3591 { { STATE_LEND }, 'o' } 3592}; 3593 3594static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { 3595 { { OPERAND_art }, 'm' } 3596}; 3597 3598static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { 3599 { { STATE_LEND }, 'm' } 3600}; 3601 3602static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { 3603 { { OPERAND_art }, 'o' } 3604}; 3605 3606static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { 3607 { { STATE_LCOUNT }, 'i' } 3608}; 3609 3610static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { 3611 { { OPERAND_art }, 'i' } 3612}; 3613 3614static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { 3615 { { STATE_XTSYNC }, 'o' }, 3616 { { STATE_LCOUNT }, 'o' } 3617}; 3618 3619static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { 3620 { { OPERAND_art }, 'm' } 3621}; 3622 3623static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { 3624 { { STATE_XTSYNC }, 'o' }, 3625 { { STATE_LCOUNT }, 'm' } 3626}; 3627 3628static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { 3629 { { OPERAND_art }, 'o' } 3630}; 3631 3632static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { 3633 { { STATE_LBEG }, 'i' } 3634}; 3635 3636static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { 3637 { { OPERAND_art }, 'i' } 3638}; 3639 3640static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { 3641 { { STATE_LBEG }, 'o' } 3642}; 3643 3644static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { 3645 { { OPERAND_art }, 'm' } 3646}; 3647 3648static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { 3649 { { STATE_LBEG }, 'm' } 3650}; 3651 3652static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { 3653 { { OPERAND_art }, 'o' } 3654}; 3655 3656static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { 3657 { { STATE_SAR }, 'i' } 3658}; 3659 3660static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { 3661 { { OPERAND_art }, 'i' } 3662}; 3663 3664static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { 3665 { { STATE_SAR }, 'o' }, 3666 { { STATE_XTSYNC }, 'o' } 3667}; 3668 3669static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { 3670 { { OPERAND_art }, 'm' } 3671}; 3672 3673static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { 3674 { { STATE_SAR }, 'm' } 3675}; 3676 3677static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { 3678 { { OPERAND_art }, 'o' } 3679}; 3680 3681static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { 3682 { { OPERAND_art }, 'i' } 3683}; 3684 3685static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { 3686 { { OPERAND_art }, 'm' } 3687}; 3688 3689static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { 3690 { { OPERAND_art }, 'o' } 3691}; 3692 3693static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { 3694 { { OPERAND_art }, 'i' } 3695}; 3696 3697static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { 3698 { { OPERAND_art }, 'm' } 3699}; 3700 3701static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { 3702 { { OPERAND_art }, 'o' } 3703}; 3704 3705static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { 3706 { { OPERAND_art }, 'i' } 3707}; 3708 3709static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { 3710 { { OPERAND_art }, 'o' } 3711}; 3712 3713static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { 3714 { { OPERAND_art }, 'o' } 3715}; 3716 3717static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { 3718 { { STATE_PSWOE }, 'i' }, 3719 { { STATE_PSCALLINC }, 'i' }, 3720 { { STATE_PSOWB }, 'i' }, 3721 { { STATE_PSUM }, 'i' }, 3722 { { STATE_PSEXCM }, 'i' }, 3723 { { STATE_PSINTLEVEL }, 'i' } 3724}; 3725 3726static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { 3727 { { OPERAND_art }, 'i' } 3728}; 3729 3730static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { 3731 { { STATE_PSWOE }, 'o' }, 3732 { { STATE_PSCALLINC }, 'o' }, 3733 { { STATE_PSOWB }, 'o' }, 3734 { { STATE_PSUM }, 'o' }, 3735 { { STATE_PSEXCM }, 'o' }, 3736 { { STATE_PSINTLEVEL }, 'o' } 3737}; 3738 3739static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { 3740 { { OPERAND_art }, 'm' } 3741}; 3742 3743static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { 3744 { { STATE_PSWOE }, 'm' }, 3745 { { STATE_PSCALLINC }, 'm' }, 3746 { { STATE_PSOWB }, 'm' }, 3747 { { STATE_PSUM }, 'm' }, 3748 { { STATE_PSEXCM }, 'm' }, 3749 { { STATE_PSINTLEVEL }, 'm' } 3750}; 3751 3752static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { 3753 { { OPERAND_art }, 'o' } 3754}; 3755 3756static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { 3757 { { STATE_EPC1 }, 'i' } 3758}; 3759 3760static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { 3761 { { OPERAND_art }, 'i' } 3762}; 3763 3764static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { 3765 { { STATE_EPC1 }, 'o' } 3766}; 3767 3768static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { 3769 { { OPERAND_art }, 'm' } 3770}; 3771 3772static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { 3773 { { STATE_EPC1 }, 'm' } 3774}; 3775 3776static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { 3777 { { OPERAND_art }, 'o' } 3778}; 3779 3780static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { 3781 { { STATE_EXCSAVE1 }, 'i' } 3782}; 3783 3784static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { 3785 { { OPERAND_art }, 'i' } 3786}; 3787 3788static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { 3789 { { STATE_EXCSAVE1 }, 'o' } 3790}; 3791 3792static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { 3793 { { OPERAND_art }, 'm' } 3794}; 3795 3796static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { 3797 { { STATE_EXCSAVE1 }, 'm' } 3798}; 3799 3800static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { 3801 { { OPERAND_art }, 'o' } 3802}; 3803 3804static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { 3805 { { STATE_EPC2 }, 'i' } 3806}; 3807 3808static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { 3809 { { OPERAND_art }, 'i' } 3810}; 3811 3812static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { 3813 { { STATE_EPC2 }, 'o' } 3814}; 3815 3816static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { 3817 { { OPERAND_art }, 'm' } 3818}; 3819 3820static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { 3821 { { STATE_EPC2 }, 'm' } 3822}; 3823 3824static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { 3825 { { OPERAND_art }, 'o' } 3826}; 3827 3828static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { 3829 { { STATE_EXCSAVE2 }, 'i' } 3830}; 3831 3832static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { 3833 { { OPERAND_art }, 'i' } 3834}; 3835 3836static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { 3837 { { STATE_EXCSAVE2 }, 'o' } 3838}; 3839 3840static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { 3841 { { OPERAND_art }, 'm' } 3842}; 3843 3844static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { 3845 { { STATE_EXCSAVE2 }, 'm' } 3846}; 3847 3848static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { 3849 { { OPERAND_art }, 'o' } 3850}; 3851 3852static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { 3853 { { STATE_EPC3 }, 'i' } 3854}; 3855 3856static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { 3857 { { OPERAND_art }, 'i' } 3858}; 3859 3860static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { 3861 { { STATE_EPC3 }, 'o' } 3862}; 3863 3864static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { 3865 { { OPERAND_art }, 'm' } 3866}; 3867 3868static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { 3869 { { STATE_EPC3 }, 'm' } 3870}; 3871 3872static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { 3873 { { OPERAND_art }, 'o' } 3874}; 3875 3876static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { 3877 { { STATE_EXCSAVE3 }, 'i' } 3878}; 3879 3880static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { 3881 { { OPERAND_art }, 'i' } 3882}; 3883 3884static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { 3885 { { STATE_EXCSAVE3 }, 'o' } 3886}; 3887 3888static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { 3889 { { OPERAND_art }, 'm' } 3890}; 3891 3892static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { 3893 { { STATE_EXCSAVE3 }, 'm' } 3894}; 3895 3896static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { 3897 { { OPERAND_art }, 'o' } 3898}; 3899 3900static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { 3901 { { STATE_EPC4 }, 'i' } 3902}; 3903 3904static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { 3905 { { OPERAND_art }, 'i' } 3906}; 3907 3908static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { 3909 { { STATE_EPC4 }, 'o' } 3910}; 3911 3912static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { 3913 { { OPERAND_art }, 'm' } 3914}; 3915 3916static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { 3917 { { STATE_EPC4 }, 'm' } 3918}; 3919 3920static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { 3921 { { OPERAND_art }, 'o' } 3922}; 3923 3924static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { 3925 { { STATE_EXCSAVE4 }, 'i' } 3926}; 3927 3928static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { 3929 { { OPERAND_art }, 'i' } 3930}; 3931 3932static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { 3933 { { STATE_EXCSAVE4 }, 'o' } 3934}; 3935 3936static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { 3937 { { OPERAND_art }, 'm' } 3938}; 3939 3940static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { 3941 { { STATE_EXCSAVE4 }, 'm' } 3942}; 3943 3944static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { 3945 { { OPERAND_art }, 'o' } 3946}; 3947 3948static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { 3949 { { STATE_EPC5 }, 'i' } 3950}; 3951 3952static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { 3953 { { OPERAND_art }, 'i' } 3954}; 3955 3956static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { 3957 { { STATE_EPC5 }, 'o' } 3958}; 3959 3960static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { 3961 { { OPERAND_art }, 'm' } 3962}; 3963 3964static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { 3965 { { STATE_EPC5 }, 'm' } 3966}; 3967 3968static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { 3969 { { OPERAND_art }, 'o' } 3970}; 3971 3972static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { 3973 { { STATE_EXCSAVE5 }, 'i' } 3974}; 3975 3976static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { 3977 { { OPERAND_art }, 'i' } 3978}; 3979 3980static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { 3981 { { STATE_EXCSAVE5 }, 'o' } 3982}; 3983 3984static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { 3985 { { OPERAND_art }, 'm' } 3986}; 3987 3988static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { 3989 { { STATE_EXCSAVE5 }, 'm' } 3990}; 3991 3992static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { 3993 { { OPERAND_art }, 'o' } 3994}; 3995 3996static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { 3997 { { STATE_EPC6 }, 'i' } 3998}; 3999 4000static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { 4001 { { OPERAND_art }, 'i' } 4002}; 4003 4004static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { 4005 { { STATE_EPC6 }, 'o' } 4006}; 4007 4008static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { 4009 { { OPERAND_art }, 'm' } 4010}; 4011 4012static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { 4013 { { STATE_EPC6 }, 'm' } 4014}; 4015 4016static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { 4017 { { OPERAND_art }, 'o' } 4018}; 4019 4020static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { 4021 { { STATE_EXCSAVE6 }, 'i' } 4022}; 4023 4024static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { 4025 { { OPERAND_art }, 'i' } 4026}; 4027 4028static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { 4029 { { STATE_EXCSAVE6 }, 'o' } 4030}; 4031 4032static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { 4033 { { OPERAND_art }, 'm' } 4034}; 4035 4036static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { 4037 { { STATE_EXCSAVE6 }, 'm' } 4038}; 4039 4040static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { 4041 { { OPERAND_art }, 'o' } 4042}; 4043 4044static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { 4045 { { STATE_EPC7 }, 'i' } 4046}; 4047 4048static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { 4049 { { OPERAND_art }, 'i' } 4050}; 4051 4052static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { 4053 { { STATE_EPC7 }, 'o' } 4054}; 4055 4056static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { 4057 { { OPERAND_art }, 'm' } 4058}; 4059 4060static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { 4061 { { STATE_EPC7 }, 'm' } 4062}; 4063 4064static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { 4065 { { OPERAND_art }, 'o' } 4066}; 4067 4068static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { 4069 { { STATE_EXCSAVE7 }, 'i' } 4070}; 4071 4072static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { 4073 { { OPERAND_art }, 'i' } 4074}; 4075 4076static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { 4077 { { STATE_EXCSAVE7 }, 'o' } 4078}; 4079 4080static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { 4081 { { OPERAND_art }, 'm' } 4082}; 4083 4084static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { 4085 { { STATE_EXCSAVE7 }, 'm' } 4086}; 4087 4088static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { 4089 { { OPERAND_art }, 'o' } 4090}; 4091 4092static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { 4093 { { STATE_EPS2 }, 'i' } 4094}; 4095 4096static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { 4097 { { OPERAND_art }, 'i' } 4098}; 4099 4100static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { 4101 { { STATE_EPS2 }, 'o' } 4102}; 4103 4104static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { 4105 { { OPERAND_art }, 'm' } 4106}; 4107 4108static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { 4109 { { STATE_EPS2 }, 'm' } 4110}; 4111 4112static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { 4113 { { OPERAND_art }, 'o' } 4114}; 4115 4116static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { 4117 { { STATE_EPS3 }, 'i' } 4118}; 4119 4120static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { 4121 { { OPERAND_art }, 'i' } 4122}; 4123 4124static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { 4125 { { STATE_EPS3 }, 'o' } 4126}; 4127 4128static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { 4129 { { OPERAND_art }, 'm' } 4130}; 4131 4132static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { 4133 { { STATE_EPS3 }, 'm' } 4134}; 4135 4136static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { 4137 { { OPERAND_art }, 'o' } 4138}; 4139 4140static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { 4141 { { STATE_EPS4 }, 'i' } 4142}; 4143 4144static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { 4145 { { OPERAND_art }, 'i' } 4146}; 4147 4148static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { 4149 { { STATE_EPS4 }, 'o' } 4150}; 4151 4152static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { 4153 { { OPERAND_art }, 'm' } 4154}; 4155 4156static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { 4157 { { STATE_EPS4 }, 'm' } 4158}; 4159 4160static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { 4161 { { OPERAND_art }, 'o' } 4162}; 4163 4164static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { 4165 { { STATE_EPS5 }, 'i' } 4166}; 4167 4168static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { 4169 { { OPERAND_art }, 'i' } 4170}; 4171 4172static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { 4173 { { STATE_EPS5 }, 'o' } 4174}; 4175 4176static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { 4177 { { OPERAND_art }, 'm' } 4178}; 4179 4180static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { 4181 { { STATE_EPS5 }, 'm' } 4182}; 4183 4184static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { 4185 { { OPERAND_art }, 'o' } 4186}; 4187 4188static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { 4189 { { STATE_EPS6 }, 'i' } 4190}; 4191 4192static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { 4193 { { OPERAND_art }, 'i' } 4194}; 4195 4196static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { 4197 { { STATE_EPS6 }, 'o' } 4198}; 4199 4200static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { 4201 { { OPERAND_art }, 'm' } 4202}; 4203 4204static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { 4205 { { STATE_EPS6 }, 'm' } 4206}; 4207 4208static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { 4209 { { OPERAND_art }, 'o' } 4210}; 4211 4212static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { 4213 { { STATE_EPS7 }, 'i' } 4214}; 4215 4216static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { 4217 { { OPERAND_art }, 'i' } 4218}; 4219 4220static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { 4221 { { STATE_EPS7 }, 'o' } 4222}; 4223 4224static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { 4225 { { OPERAND_art }, 'm' } 4226}; 4227 4228static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { 4229 { { STATE_EPS7 }, 'm' } 4230}; 4231 4232static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { 4233 { { OPERAND_art }, 'o' } 4234}; 4235 4236static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { 4237 { { STATE_EXCVADDR }, 'i' } 4238}; 4239 4240static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { 4241 { { OPERAND_art }, 'i' } 4242}; 4243 4244static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { 4245 { { STATE_EXCVADDR }, 'o' } 4246}; 4247 4248static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { 4249 { { OPERAND_art }, 'm' } 4250}; 4251 4252static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { 4253 { { STATE_EXCVADDR }, 'm' } 4254}; 4255 4256static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { 4257 { { OPERAND_art }, 'o' } 4258}; 4259 4260static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { 4261 { { STATE_DEPC }, 'i' } 4262}; 4263 4264static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { 4265 { { OPERAND_art }, 'i' } 4266}; 4267 4268static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { 4269 { { STATE_DEPC }, 'o' } 4270}; 4271 4272static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { 4273 { { OPERAND_art }, 'm' } 4274}; 4275 4276static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { 4277 { { STATE_DEPC }, 'm' } 4278}; 4279 4280static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { 4281 { { OPERAND_art }, 'o' } 4282}; 4283 4284static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { 4285 { { STATE_EXCCAUSE }, 'i' }, 4286 { { STATE_XTSYNC }, 'i' } 4287}; 4288 4289static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { 4290 { { OPERAND_art }, 'i' } 4291}; 4292 4293static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { 4294 { { STATE_EXCCAUSE }, 'o' } 4295}; 4296 4297static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { 4298 { { OPERAND_art }, 'm' } 4299}; 4300 4301static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { 4302 { { STATE_EXCCAUSE }, 'm' } 4303}; 4304 4305static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { 4306 { { OPERAND_art }, 'o' } 4307}; 4308 4309static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { 4310 { { STATE_MISC0 }, 'i' } 4311}; 4312 4313static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { 4314 { { OPERAND_art }, 'i' } 4315}; 4316 4317static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { 4318 { { STATE_MISC0 }, 'o' } 4319}; 4320 4321static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { 4322 { { OPERAND_art }, 'm' } 4323}; 4324 4325static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { 4326 { { STATE_MISC0 }, 'm' } 4327}; 4328 4329static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { 4330 { { OPERAND_art }, 'o' } 4331}; 4332 4333static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { 4334 { { STATE_MISC1 }, 'i' } 4335}; 4336 4337static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { 4338 { { OPERAND_art }, 'i' } 4339}; 4340 4341static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { 4342 { { STATE_MISC1 }, 'o' } 4343}; 4344 4345static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { 4346 { { OPERAND_art }, 'm' } 4347}; 4348 4349static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { 4350 { { STATE_MISC1 }, 'm' } 4351}; 4352 4353static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { 4354 { { OPERAND_art }, 'o' } 4355}; 4356 4357static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { 4358 { { OPERAND_art }, 'o' } 4359}; 4360 4361static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { 4362 { { STATE_VECBASE }, 'i' } 4363}; 4364 4365static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { 4366 { { OPERAND_art }, 'i' } 4367}; 4368 4369static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { 4370 { { STATE_VECBASE }, 'o' } 4371}; 4372 4373static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { 4374 { { OPERAND_art }, 'm' } 4375}; 4376 4377static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { 4378 { { STATE_VECBASE }, 'm' } 4379}; 4380 4381static xtensa_arg_internal Iclass_xt_mul16_args[] = { 4382 { { OPERAND_arr }, 'o' }, 4383 { { OPERAND_ars }, 'i' }, 4384 { { OPERAND_art }, 'i' } 4385}; 4386 4387static xtensa_arg_internal Iclass_xt_mul32_args[] = { 4388 { { OPERAND_arr }, 'o' }, 4389 { { OPERAND_ars }, 'i' }, 4390 { { OPERAND_art }, 'i' } 4391}; 4392 4393static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { 4394 { { OPERAND_ars }, 'i' }, 4395 { { OPERAND_art }, 'i' } 4396}; 4397 4398static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { 4399 { { STATE_ACC }, 'o' } 4400}; 4401 4402static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { 4403 { { OPERAND_ars }, 'i' }, 4404 { { OPERAND_my }, 'i' } 4405}; 4406 4407static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { 4408 { { STATE_ACC }, 'o' } 4409}; 4410 4411static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { 4412 { { OPERAND_mx }, 'i' }, 4413 { { OPERAND_art }, 'i' } 4414}; 4415 4416static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { 4417 { { STATE_ACC }, 'o' } 4418}; 4419 4420static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { 4421 { { OPERAND_mx }, 'i' }, 4422 { { OPERAND_my }, 'i' } 4423}; 4424 4425static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { 4426 { { STATE_ACC }, 'o' } 4427}; 4428 4429static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { 4430 { { OPERAND_ars }, 'i' }, 4431 { { OPERAND_art }, 'i' } 4432}; 4433 4434static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { 4435 { { STATE_ACC }, 'm' } 4436}; 4437 4438static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { 4439 { { OPERAND_ars }, 'i' }, 4440 { { OPERAND_my }, 'i' } 4441}; 4442 4443static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { 4444 { { STATE_ACC }, 'm' } 4445}; 4446 4447static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { 4448 { { OPERAND_mx }, 'i' }, 4449 { { OPERAND_art }, 'i' } 4450}; 4451 4452static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { 4453 { { STATE_ACC }, 'm' } 4454}; 4455 4456static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { 4457 { { OPERAND_mx }, 'i' }, 4458 { { OPERAND_my }, 'i' } 4459}; 4460 4461static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { 4462 { { STATE_ACC }, 'm' } 4463}; 4464 4465static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { 4466 { { OPERAND_mw }, 'o' }, 4467 { { OPERAND_ars }, 'm' }, 4468 { { OPERAND_mx }, 'i' }, 4469 { { OPERAND_art }, 'i' } 4470}; 4471 4472static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { 4473 { { STATE_ACC }, 'm' } 4474}; 4475 4476static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { 4477 { { OPERAND_mw }, 'o' }, 4478 { { OPERAND_ars }, 'm' }, 4479 { { OPERAND_mx }, 'i' }, 4480 { { OPERAND_my }, 'i' } 4481}; 4482 4483static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { 4484 { { STATE_ACC }, 'm' } 4485}; 4486 4487static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { 4488 { { OPERAND_mw }, 'o' }, 4489 { { OPERAND_ars }, 'm' } 4490}; 4491 4492static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { 4493 { { OPERAND_art }, 'o' }, 4494 { { OPERAND_mr0 }, 'i' } 4495}; 4496 4497static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { 4498 { { OPERAND_art }, 'i' }, 4499 { { OPERAND_mr0 }, 'o' } 4500}; 4501 4502static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { 4503 { { OPERAND_art }, 'm' }, 4504 { { OPERAND_mr0 }, 'm' } 4505}; 4506 4507static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { 4508 { { OPERAND_art }, 'o' }, 4509 { { OPERAND_mr1 }, 'i' } 4510}; 4511 4512static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { 4513 { { OPERAND_art }, 'i' }, 4514 { { OPERAND_mr1 }, 'o' } 4515}; 4516 4517static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { 4518 { { OPERAND_art }, 'm' }, 4519 { { OPERAND_mr1 }, 'm' } 4520}; 4521 4522static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { 4523 { { OPERAND_art }, 'o' }, 4524 { { OPERAND_mr2 }, 'i' } 4525}; 4526 4527static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { 4528 { { OPERAND_art }, 'i' }, 4529 { { OPERAND_mr2 }, 'o' } 4530}; 4531 4532static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { 4533 { { OPERAND_art }, 'm' }, 4534 { { OPERAND_mr2 }, 'm' } 4535}; 4536 4537static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { 4538 { { OPERAND_art }, 'o' }, 4539 { { OPERAND_mr3 }, 'i' } 4540}; 4541 4542static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { 4543 { { OPERAND_art }, 'i' }, 4544 { { OPERAND_mr3 }, 'o' } 4545}; 4546 4547static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { 4548 { { OPERAND_art }, 'm' }, 4549 { { OPERAND_mr3 }, 'm' } 4550}; 4551 4552static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { 4553 { { OPERAND_art }, 'o' } 4554}; 4555 4556static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { 4557 { { STATE_ACC }, 'i' } 4558}; 4559 4560static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { 4561 { { OPERAND_art }, 'i' } 4562}; 4563 4564static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { 4565 { { STATE_ACC }, 'm' } 4566}; 4567 4568static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { 4569 { { OPERAND_art }, 'm' } 4570}; 4571 4572static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { 4573 { { STATE_ACC }, 'm' } 4574}; 4575 4576static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { 4577 { { OPERAND_art }, 'o' } 4578}; 4579 4580static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { 4581 { { STATE_ACC }, 'i' } 4582}; 4583 4584static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { 4585 { { OPERAND_art }, 'i' } 4586}; 4587 4588static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { 4589 { { STATE_ACC }, 'm' } 4590}; 4591 4592static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { 4593 { { OPERAND_art }, 'm' } 4594}; 4595 4596static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { 4597 { { STATE_ACC }, 'm' } 4598}; 4599 4600static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { 4601 { { OPERAND_s }, 'i' } 4602}; 4603 4604static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { 4605 { { STATE_PSWOE }, 'o' }, 4606 { { STATE_PSCALLINC }, 'o' }, 4607 { { STATE_PSOWB }, 'o' }, 4608 { { STATE_PSUM }, 'o' }, 4609 { { STATE_PSEXCM }, 'o' }, 4610 { { STATE_PSINTLEVEL }, 'o' }, 4611 { { STATE_EPC1 }, 'i' }, 4612 { { STATE_EPC2 }, 'i' }, 4613 { { STATE_EPC3 }, 'i' }, 4614 { { STATE_EPC4 }, 'i' }, 4615 { { STATE_EPC5 }, 'i' }, 4616 { { STATE_EPC6 }, 'i' }, 4617 { { STATE_EPC7 }, 'i' }, 4618 { { STATE_EPS2 }, 'i' }, 4619 { { STATE_EPS3 }, 'i' }, 4620 { { STATE_EPS4 }, 'i' }, 4621 { { STATE_EPS5 }, 'i' }, 4622 { { STATE_EPS6 }, 'i' }, 4623 { { STATE_EPS7 }, 'i' }, 4624 { { STATE_InOCDMode }, 'm' } 4625}; 4626 4627static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { 4628 { { OPERAND_s }, 'i' } 4629}; 4630 4631static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { 4632 { { STATE_PSINTLEVEL }, 'o' } 4633}; 4634 4635static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { 4636 { { OPERAND_art }, 'o' } 4637}; 4638 4639static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { 4640 { { STATE_INTERRUPT }, 'i' } 4641}; 4642 4643static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { 4644 { { OPERAND_art }, 'i' } 4645}; 4646 4647static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { 4648 { { STATE_XTSYNC }, 'o' }, 4649 { { STATE_INTERRUPT }, 'm' } 4650}; 4651 4652static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { 4653 { { OPERAND_art }, 'i' } 4654}; 4655 4656static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { 4657 { { STATE_XTSYNC }, 'o' }, 4658 { { STATE_INTERRUPT }, 'm' } 4659}; 4660 4661static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { 4662 { { OPERAND_art }, 'o' } 4663}; 4664 4665static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { 4666 { { STATE_INTENABLE }, 'i' } 4667}; 4668 4669static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { 4670 { { OPERAND_art }, 'i' } 4671}; 4672 4673static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { 4674 { { STATE_INTENABLE }, 'o' } 4675}; 4676 4677static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { 4678 { { OPERAND_art }, 'm' } 4679}; 4680 4681static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { 4682 { { STATE_INTENABLE }, 'm' } 4683}; 4684 4685static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { 4686 { { OPERAND_imms }, 'i' }, 4687 { { OPERAND_immt }, 'i' } 4688}; 4689 4690static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { 4691 { { STATE_PSEXCM }, 'i' }, 4692 { { STATE_PSINTLEVEL }, 'i' } 4693}; 4694 4695static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { 4696 { { OPERAND_imms }, 'i' } 4697}; 4698 4699static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { 4700 { { STATE_PSEXCM }, 'i' }, 4701 { { STATE_PSINTLEVEL }, 'i' } 4702}; 4703 4704static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { 4705 { { OPERAND_art }, 'o' } 4706}; 4707 4708static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { 4709 { { STATE_DBREAKA0 }, 'i' } 4710}; 4711 4712static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { 4713 { { OPERAND_art }, 'i' } 4714}; 4715 4716static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { 4717 { { STATE_DBREAKA0 }, 'o' }, 4718 { { STATE_XTSYNC }, 'o' } 4719}; 4720 4721static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { 4722 { { OPERAND_art }, 'm' } 4723}; 4724 4725static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { 4726 { { STATE_DBREAKA0 }, 'm' }, 4727 { { STATE_XTSYNC }, 'o' } 4728}; 4729 4730static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { 4731 { { OPERAND_art }, 'o' } 4732}; 4733 4734static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { 4735 { { STATE_DBREAKC0 }, 'i' } 4736}; 4737 4738static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { 4739 { { OPERAND_art }, 'i' } 4740}; 4741 4742static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { 4743 { { STATE_DBREAKC0 }, 'o' }, 4744 { { STATE_XTSYNC }, 'o' } 4745}; 4746 4747static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { 4748 { { OPERAND_art }, 'm' } 4749}; 4750 4751static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { 4752 { { STATE_DBREAKC0 }, 'm' }, 4753 { { STATE_XTSYNC }, 'o' } 4754}; 4755 4756static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { 4757 { { OPERAND_art }, 'o' } 4758}; 4759 4760static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { 4761 { { STATE_DBREAKA1 }, 'i' } 4762}; 4763 4764static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { 4765 { { OPERAND_art }, 'i' } 4766}; 4767 4768static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { 4769 { { STATE_DBREAKA1 }, 'o' }, 4770 { { STATE_XTSYNC }, 'o' } 4771}; 4772 4773static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { 4774 { { OPERAND_art }, 'm' } 4775}; 4776 4777static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { 4778 { { STATE_DBREAKA1 }, 'm' }, 4779 { { STATE_XTSYNC }, 'o' } 4780}; 4781 4782static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { 4783 { { OPERAND_art }, 'o' } 4784}; 4785 4786static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { 4787 { { STATE_DBREAKC1 }, 'i' } 4788}; 4789 4790static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { 4791 { { OPERAND_art }, 'i' } 4792}; 4793 4794static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { 4795 { { STATE_DBREAKC1 }, 'o' }, 4796 { { STATE_XTSYNC }, 'o' } 4797}; 4798 4799static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { 4800 { { OPERAND_art }, 'm' } 4801}; 4802 4803static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { 4804 { { STATE_DBREAKC1 }, 'm' }, 4805 { { STATE_XTSYNC }, 'o' } 4806}; 4807 4808static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { 4809 { { OPERAND_art }, 'o' } 4810}; 4811 4812static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { 4813 { { STATE_IBREAKA0 }, 'i' } 4814}; 4815 4816static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { 4817 { { OPERAND_art }, 'i' } 4818}; 4819 4820static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { 4821 { { STATE_IBREAKA0 }, 'o' } 4822}; 4823 4824static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { 4825 { { OPERAND_art }, 'm' } 4826}; 4827 4828static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { 4829 { { STATE_IBREAKA0 }, 'm' } 4830}; 4831 4832static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { 4833 { { OPERAND_art }, 'o' } 4834}; 4835 4836static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { 4837 { { STATE_IBREAKA1 }, 'i' } 4838}; 4839 4840static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { 4841 { { OPERAND_art }, 'i' } 4842}; 4843 4844static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { 4845 { { STATE_IBREAKA1 }, 'o' } 4846}; 4847 4848static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { 4849 { { OPERAND_art }, 'm' } 4850}; 4851 4852static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { 4853 { { STATE_IBREAKA1 }, 'm' } 4854}; 4855 4856static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { 4857 { { OPERAND_art }, 'o' } 4858}; 4859 4860static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { 4861 { { STATE_IBREAKENABLE }, 'i' } 4862}; 4863 4864static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { 4865 { { OPERAND_art }, 'i' } 4866}; 4867 4868static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { 4869 { { STATE_IBREAKENABLE }, 'o' } 4870}; 4871 4872static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { 4873 { { OPERAND_art }, 'm' } 4874}; 4875 4876static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { 4877 { { STATE_IBREAKENABLE }, 'm' } 4878}; 4879 4880static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { 4881 { { OPERAND_art }, 'o' } 4882}; 4883 4884static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { 4885 { { STATE_DEBUGCAUSE }, 'i' }, 4886 { { STATE_DBNUM }, 'i' } 4887}; 4888 4889static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { 4890 { { OPERAND_art }, 'i' } 4891}; 4892 4893static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { 4894 { { STATE_DEBUGCAUSE }, 'o' }, 4895 { { STATE_DBNUM }, 'o' } 4896}; 4897 4898static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { 4899 { { OPERAND_art }, 'm' } 4900}; 4901 4902static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { 4903 { { STATE_DEBUGCAUSE }, 'm' }, 4904 { { STATE_DBNUM }, 'm' } 4905}; 4906 4907static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { 4908 { { OPERAND_art }, 'o' } 4909}; 4910 4911static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { 4912 { { STATE_ICOUNT }, 'i' } 4913}; 4914 4915static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { 4916 { { OPERAND_art }, 'i' } 4917}; 4918 4919static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { 4920 { { STATE_XTSYNC }, 'o' }, 4921 { { STATE_ICOUNT }, 'o' } 4922}; 4923 4924static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { 4925 { { OPERAND_art }, 'm' } 4926}; 4927 4928static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { 4929 { { STATE_XTSYNC }, 'o' }, 4930 { { STATE_ICOUNT }, 'm' } 4931}; 4932 4933static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { 4934 { { OPERAND_art }, 'o' } 4935}; 4936 4937static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { 4938 { { STATE_ICOUNTLEVEL }, 'i' } 4939}; 4940 4941static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { 4942 { { OPERAND_art }, 'i' } 4943}; 4944 4945static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { 4946 { { STATE_ICOUNTLEVEL }, 'o' } 4947}; 4948 4949static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { 4950 { { OPERAND_art }, 'm' } 4951}; 4952 4953static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { 4954 { { STATE_ICOUNTLEVEL }, 'm' } 4955}; 4956 4957static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { 4958 { { OPERAND_art }, 'o' } 4959}; 4960 4961static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { 4962 { { STATE_DDR }, 'i' } 4963}; 4964 4965static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { 4966 { { OPERAND_art }, 'i' } 4967}; 4968 4969static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { 4970 { { STATE_XTSYNC }, 'o' }, 4971 { { STATE_DDR }, 'o' } 4972}; 4973 4974static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { 4975 { { OPERAND_art }, 'm' } 4976}; 4977 4978static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { 4979 { { STATE_XTSYNC }, 'o' }, 4980 { { STATE_DDR }, 'm' } 4981}; 4982 4983static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { 4984 { { OPERAND_ars }, 'm' } 4985}; 4986 4987static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { 4988 { { STATE_XTSYNC }, 'o' }, 4989 { { STATE_InOCDMode }, 'i' }, 4990 { { STATE_DDR }, 'o' } 4991}; 4992 4993static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { 4994 { { OPERAND_ars }, 'm' } 4995}; 4996 4997static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { 4998 { { STATE_InOCDMode }, 'i' }, 4999 { { STATE_DDR }, 'i' } 5000}; 5001 5002static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { 5003 { { OPERAND_imms }, 'i' } 5004}; 5005 5006static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { 5007 { { STATE_InOCDMode }, 'm' }, 5008 { { STATE_EPC6 }, 'i' }, 5009 { { STATE_PSWOE }, 'o' }, 5010 { { STATE_PSCALLINC }, 'o' }, 5011 { { STATE_PSOWB }, 'o' }, 5012 { { STATE_PSUM }, 'o' }, 5013 { { STATE_PSEXCM }, 'o' }, 5014 { { STATE_PSINTLEVEL }, 'o' }, 5015 { { STATE_EPS6 }, 'i' } 5016}; 5017 5018static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { 5019 { { STATE_InOCDMode }, 'm' } 5020}; 5021 5022static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { 5023 { { OPERAND_art }, 'i' } 5024}; 5025 5026static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { 5027 { { STATE_XTSYNC }, 'o' } 5028}; 5029 5030static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { 5031 { { OPERAND_art }, 'o' } 5032}; 5033 5034static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { 5035 { { STATE_CCOUNT }, 'i' } 5036}; 5037 5038static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { 5039 { { OPERAND_art }, 'i' } 5040}; 5041 5042static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { 5043 { { STATE_XTSYNC }, 'o' }, 5044 { { STATE_CCOUNT }, 'o' } 5045}; 5046 5047static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { 5048 { { OPERAND_art }, 'm' } 5049}; 5050 5051static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { 5052 { { STATE_XTSYNC }, 'o' }, 5053 { { STATE_CCOUNT }, 'm' } 5054}; 5055 5056static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { 5057 { { OPERAND_art }, 'o' } 5058}; 5059 5060static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { 5061 { { STATE_CCOMPARE0 }, 'i' } 5062}; 5063 5064static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { 5065 { { OPERAND_art }, 'i' } 5066}; 5067 5068static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { 5069 { { STATE_CCOMPARE0 }, 'o' }, 5070 { { STATE_INTERRUPT }, 'm' } 5071}; 5072 5073static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { 5074 { { OPERAND_art }, 'm' } 5075}; 5076 5077static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { 5078 { { STATE_CCOMPARE0 }, 'm' }, 5079 { { STATE_INTERRUPT }, 'm' } 5080}; 5081 5082static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { 5083 { { OPERAND_art }, 'o' } 5084}; 5085 5086static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { 5087 { { STATE_CCOMPARE1 }, 'i' } 5088}; 5089 5090static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { 5091 { { OPERAND_art }, 'i' } 5092}; 5093 5094static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { 5095 { { STATE_CCOMPARE1 }, 'o' }, 5096 { { STATE_INTERRUPT }, 'm' } 5097}; 5098 5099static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { 5100 { { OPERAND_art }, 'm' } 5101}; 5102 5103static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { 5104 { { STATE_CCOMPARE1 }, 'm' }, 5105 { { STATE_INTERRUPT }, 'm' } 5106}; 5107 5108static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { 5109 { { OPERAND_art }, 'o' } 5110}; 5111 5112static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { 5113 { { STATE_CCOMPARE2 }, 'i' } 5114}; 5115 5116static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { 5117 { { OPERAND_art }, 'i' } 5118}; 5119 5120static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { 5121 { { STATE_CCOMPARE2 }, 'o' }, 5122 { { STATE_INTERRUPT }, 'm' } 5123}; 5124 5125static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { 5126 { { OPERAND_art }, 'm' } 5127}; 5128 5129static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { 5130 { { STATE_CCOMPARE2 }, 'm' }, 5131 { { STATE_INTERRUPT }, 'm' } 5132}; 5133 5134static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { 5135 { { OPERAND_ars }, 'i' }, 5136 { { OPERAND_uimm8x4 }, 'i' } 5137}; 5138 5139static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { 5140 { { OPERAND_ars }, 'i' }, 5141 { { OPERAND_uimm4x16 }, 'i' } 5142}; 5143 5144static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { 5145 { { OPERAND_ars }, 'i' }, 5146 { { OPERAND_uimm8x4 }, 'i' } 5147}; 5148 5149static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { 5150 { { OPERAND_art }, 'o' }, 5151 { { OPERAND_ars }, 'i' } 5152}; 5153 5154static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { 5155 { { OPERAND_art }, 'i' }, 5156 { { OPERAND_ars }, 'i' } 5157}; 5158 5159static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { 5160 { { OPERAND_ars }, 'i' }, 5161 { { OPERAND_uimm8x4 }, 'i' } 5162}; 5163 5164static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { 5165 { { OPERAND_ars }, 'm' } 5166}; 5167 5168static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { 5169 { { OPERAND_ars }, 'i' }, 5170 { { OPERAND_uimm4x16 }, 'i' } 5171}; 5172 5173static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { 5174 { { OPERAND_ars }, 'i' }, 5175 { { OPERAND_uimm8x4 }, 'i' } 5176}; 5177 5178static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { 5179 { { OPERAND_ars }, 'i' }, 5180 { { OPERAND_uimm8x4 }, 'i' } 5181}; 5182 5183static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { 5184 { { OPERAND_ars }, 'i' }, 5185 { { OPERAND_uimm4x16 }, 'i' } 5186}; 5187 5188static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { 5189 { { OPERAND_art }, 'i' }, 5190 { { OPERAND_ars }, 'i' } 5191}; 5192 5193static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { 5194 { { OPERAND_art }, 'o' }, 5195 { { OPERAND_ars }, 'i' } 5196}; 5197 5198static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { 5199 { { OPERAND_ars }, 'i' } 5200}; 5201 5202static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { 5203 { { STATE_XTSYNC }, 'o' } 5204}; 5205 5206static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { 5207 { { OPERAND_art }, 'o' }, 5208 { { OPERAND_ars }, 'i' } 5209}; 5210 5211static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { 5212 { { OPERAND_art }, 'i' }, 5213 { { OPERAND_ars }, 'i' } 5214}; 5215 5216static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { 5217 { { STATE_XTSYNC }, 'o' } 5218}; 5219 5220static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { 5221 { { OPERAND_ars }, 'i' } 5222}; 5223 5224static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { 5225 { { OPERAND_art }, 'o' }, 5226 { { OPERAND_ars }, 'i' } 5227}; 5228 5229static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { 5230 { { OPERAND_art }, 'i' }, 5231 { { OPERAND_ars }, 'i' } 5232}; 5233 5234static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { 5235 { { OPERAND_arr }, 'o' }, 5236 { { OPERAND_ars }, 'i' }, 5237 { { OPERAND_tp7 }, 'i' } 5238}; 5239 5240static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { 5241 { { OPERAND_arr }, 'o' }, 5242 { { OPERAND_ars }, 'i' }, 5243 { { OPERAND_art }, 'i' } 5244}; 5245 5246static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { 5247 { { OPERAND_art }, 'o' }, 5248 { { OPERAND_ars }, 'i' } 5249}; 5250 5251static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { 5252 { { OPERAND_arr }, 'o' }, 5253 { { OPERAND_ars }, 'i' }, 5254 { { OPERAND_tp7 }, 'i' } 5255}; 5256 5257static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { 5258 { { OPERAND_art }, 'o' }, 5259 { { OPERAND_ars }, 'i' }, 5260 { { OPERAND_uimm8x4 }, 'i' } 5261}; 5262 5263static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { 5264 { { OPERAND_art }, 'i' }, 5265 { { OPERAND_ars }, 'i' }, 5266 { { OPERAND_uimm8x4 }, 'i' } 5267}; 5268 5269static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { 5270 { { OPERAND_art }, 'm' }, 5271 { { OPERAND_ars }, 'i' }, 5272 { { OPERAND_uimm8x4 }, 'i' } 5273}; 5274 5275static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { 5276 { { STATE_SCOMPARE1 }, 'i' }, 5277 { { STATE_XTSYNC }, 'i' }, 5278 { { STATE_SCOMPARE1 }, 'i' } 5279}; 5280 5281static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { 5282 { { OPERAND_art }, 'o' } 5283}; 5284 5285static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { 5286 { { STATE_SCOMPARE1 }, 'i' } 5287}; 5288 5289static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { 5290 { { OPERAND_art }, 'i' } 5291}; 5292 5293static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { 5294 { { STATE_SCOMPARE1 }, 'o' } 5295}; 5296 5297static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { 5298 { { OPERAND_art }, 'm' } 5299}; 5300 5301static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { 5302 { { STATE_SCOMPARE1 }, 'm' } 5303}; 5304 5305static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { 5306 { { OPERAND_art }, 'o' } 5307}; 5308 5309static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { 5310 { { STATE_ATOMCTL }, 'i' } 5311}; 5312 5313static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { 5314 { { OPERAND_art }, 'i' } 5315}; 5316 5317static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { 5318 { { STATE_ATOMCTL }, 'o' }, 5319 { { STATE_XTSYNC }, 'o' } 5320}; 5321 5322static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { 5323 { { OPERAND_art }, 'm' } 5324}; 5325 5326static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { 5327 { { STATE_ATOMCTL }, 'm' }, 5328 { { STATE_XTSYNC }, 'o' } 5329}; 5330 5331static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { 5332 { { OPERAND_arr }, 'o' }, 5333 { { OPERAND_ars }, 'i' }, 5334 { { OPERAND_art }, 'i' } 5335}; 5336 5337static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { 5338 { { OPERAND_art }, 'o' }, 5339 { { OPERAND_ars }, 'i' } 5340}; 5341 5342static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { 5343 { { STATE_ERI_RAW_INTERLOCK }, 'i' } 5344}; 5345 5346static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { 5347 INTERFACE_ERI_RD_In, 5348 INTERFACE_ERI_RD_Out 5349}; 5350 5351static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { 5352 { { OPERAND_art }, 'i' }, 5353 { { OPERAND_ars }, 'i' } 5354}; 5355 5356static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { 5357 { { STATE_ERI_RAW_INTERLOCK }, 'o' } 5358}; 5359 5360static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { 5361 INTERFACE_ERI_WR_In, 5362 INTERFACE_ERI_WR_Out 5363}; 5364 5365static xtensa_arg_internal Iclass_rur_expstate_args[] = { 5366 { { OPERAND_arr }, 'o' } 5367}; 5368 5369static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { 5370 { { STATE_EXPSTATE }, 'i' } 5371}; 5372 5373static xtensa_arg_internal Iclass_wur_expstate_args[] = { 5374 { { OPERAND_art }, 'i' } 5375}; 5376 5377static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { 5378 { { STATE_EXPSTATE }, 'o' } 5379}; 5380 5381static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { 5382 { { OPERAND_art }, 'o' } 5383}; 5384 5385static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { 5386 INTERFACE_IMPWIRE 5387}; 5388 5389static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { 5390 { { OPERAND_bitindex }, 'i' } 5391}; 5392 5393static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { 5394 { { STATE_EXPSTATE }, 'm' } 5395}; 5396 5397static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { 5398 { { OPERAND_bitindex }, 'i' } 5399}; 5400 5401static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { 5402 { { STATE_EXPSTATE }, 'm' } 5403}; 5404 5405static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { 5406 { { OPERAND_art }, 'i' }, 5407 { { OPERAND_ars }, 'i' } 5408}; 5409 5410static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { 5411 { { STATE_EXPSTATE }, 'm' } 5412}; 5413 5414static xtensa_iclass_internal iclasses[] = { 5415 { 0, 0 /* xt_iclass_excw */, 5416 0, 0, 0, 0 }, 5417 { 0, 0 /* xt_iclass_rfe */, 5418 2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, 5419 { 0, 0 /* xt_iclass_rfde */, 5420 1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, 5421 { 0, 0 /* xt_iclass_syscall */, 5422 0, 0, 0, 0 }, 5423 { 2, Iclass_xt_iclass_call12_args, 5424 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, 5425 { 2, Iclass_xt_iclass_call8_args, 5426 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, 5427 { 2, Iclass_xt_iclass_call4_args, 5428 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, 5429 { 2, Iclass_xt_iclass_callx12_args, 5430 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, 5431 { 2, Iclass_xt_iclass_callx8_args, 5432 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, 5433 { 2, Iclass_xt_iclass_callx4_args, 5434 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, 5435 { 3, Iclass_xt_iclass_entry_args, 5436 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, 5437 { 2, Iclass_xt_iclass_movsp_args, 5438 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, 5439 { 1, Iclass_xt_iclass_rotw_args, 5440 1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, 5441 { 1, Iclass_xt_iclass_retw_args, 5442 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, 5443 { 0, 0 /* xt_iclass_rfwou */, 5444 5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, 5445 { 3, Iclass_xt_iclass_l32e_args, 5446 0, 0, 0, 0 }, 5447 { 3, Iclass_xt_iclass_s32e_args, 5448 0, 0, 0, 0 }, 5449 { 1, Iclass_xt_iclass_rsr_windowbase_args, 5450 1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, 5451 { 1, Iclass_xt_iclass_wsr_windowbase_args, 5452 1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, 5453 { 1, Iclass_xt_iclass_xsr_windowbase_args, 5454 1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, 5455 { 1, Iclass_xt_iclass_rsr_windowstart_args, 5456 1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, 5457 { 1, Iclass_xt_iclass_wsr_windowstart_args, 5458 1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, 5459 { 1, Iclass_xt_iclass_xsr_windowstart_args, 5460 1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, 5461 { 3, Iclass_xt_iclass_add_n_args, 5462 0, 0, 0, 0 }, 5463 { 3, Iclass_xt_iclass_addi_n_args, 5464 0, 0, 0, 0 }, 5465 { 2, Iclass_xt_iclass_bz6_args, 5466 0, 0, 0, 0 }, 5467 { 0, 0 /* xt_iclass_ill_n */, 5468 0, 0, 0, 0 }, 5469 { 3, Iclass_xt_iclass_loadi4_args, 5470 0, 0, 0, 0 }, 5471 { 2, Iclass_xt_iclass_mov_n_args, 5472 0, 0, 0, 0 }, 5473 { 2, Iclass_xt_iclass_movi_n_args, 5474 0, 0, 0, 0 }, 5475 { 0, 0 /* xt_iclass_nopn */, 5476 0, 0, 0, 0 }, 5477 { 1, Iclass_xt_iclass_retn_args, 5478 0, 0, 0, 0 }, 5479 { 3, Iclass_xt_iclass_storei4_args, 5480 0, 0, 0, 0 }, 5481 { 3, Iclass_xt_iclass_addi_args, 5482 0, 0, 0, 0 }, 5483 { 3, Iclass_xt_iclass_addmi_args, 5484 0, 0, 0, 0 }, 5485 { 3, Iclass_xt_iclass_addsub_args, 5486 0, 0, 0, 0 }, 5487 { 3, Iclass_xt_iclass_bit_args, 5488 0, 0, 0, 0 }, 5489 { 3, Iclass_xt_iclass_bsi8_args, 5490 0, 0, 0, 0 }, 5491 { 3, Iclass_xt_iclass_bsi8b_args, 5492 0, 0, 0, 0 }, 5493 { 3, Iclass_xt_iclass_bsi8u_args, 5494 0, 0, 0, 0 }, 5495 { 3, Iclass_xt_iclass_bst8_args, 5496 0, 0, 0, 0 }, 5497 { 2, Iclass_xt_iclass_bsz12_args, 5498 0, 0, 0, 0 }, 5499 { 2, Iclass_xt_iclass_call0_args, 5500 0, 0, 0, 0 }, 5501 { 2, Iclass_xt_iclass_callx0_args, 5502 0, 0, 0, 0 }, 5503 { 4, Iclass_xt_iclass_exti_args, 5504 0, 0, 0, 0 }, 5505 { 0, 0 /* xt_iclass_ill */, 5506 0, 0, 0, 0 }, 5507 { 1, Iclass_xt_iclass_jump_args, 5508 0, 0, 0, 0 }, 5509 { 1, Iclass_xt_iclass_jumpx_args, 5510 0, 0, 0, 0 }, 5511 { 3, Iclass_xt_iclass_l16ui_args, 5512 0, 0, 0, 0 }, 5513 { 3, Iclass_xt_iclass_l16si_args, 5514 0, 0, 0, 0 }, 5515 { 3, Iclass_xt_iclass_l32i_args, 5516 0, 0, 0, 0 }, 5517 { 2, Iclass_xt_iclass_l32r_args, 5518 0, 0, 0, 0 }, 5519 { 3, Iclass_xt_iclass_l8i_args, 5520 0, 0, 0, 0 }, 5521 { 2, Iclass_xt_iclass_loop_args, 5522 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, 5523 { 2, Iclass_xt_iclass_loopz_args, 5524 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, 5525 { 2, Iclass_xt_iclass_movi_args, 5526 0, 0, 0, 0 }, 5527 { 3, Iclass_xt_iclass_movz_args, 5528 0, 0, 0, 0 }, 5529 { 2, Iclass_xt_iclass_neg_args, 5530 0, 0, 0, 0 }, 5531 { 0, 0 /* xt_iclass_nop */, 5532 0, 0, 0, 0 }, 5533 { 1, Iclass_xt_iclass_return_args, 5534 0, 0, 0, 0 }, 5535 { 0, 0 /* xt_iclass_simcall */, 5536 0, 0, 0, 0 }, 5537 { 3, Iclass_xt_iclass_s16i_args, 5538 0, 0, 0, 0 }, 5539 { 3, Iclass_xt_iclass_s32i_args, 5540 0, 0, 0, 0 }, 5541 { 3, Iclass_xt_iclass_s32nb_args, 5542 0, 0, 0, 0 }, 5543 { 3, Iclass_xt_iclass_s8i_args, 5544 0, 0, 0, 0 }, 5545 { 1, Iclass_xt_iclass_sar_args, 5546 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, 5547 { 1, Iclass_xt_iclass_sari_args, 5548 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, 5549 { 2, Iclass_xt_iclass_shifts_args, 5550 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, 5551 { 3, Iclass_xt_iclass_shiftst_args, 5552 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, 5553 { 2, Iclass_xt_iclass_shiftt_args, 5554 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, 5555 { 3, Iclass_xt_iclass_slli_args, 5556 0, 0, 0, 0 }, 5557 { 3, Iclass_xt_iclass_srai_args, 5558 0, 0, 0, 0 }, 5559 { 3, Iclass_xt_iclass_srli_args, 5560 0, 0, 0, 0 }, 5561 { 0, 0 /* xt_iclass_memw */, 5562 0, 0, 0, 0 }, 5563 { 0, 0 /* xt_iclass_extw */, 5564 0, 0, 0, 0 }, 5565 { 0, 0 /* xt_iclass_isync */, 5566 0, 0, 0, 0 }, 5567 { 0, 0 /* xt_iclass_sync */, 5568 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, 5569 { 2, Iclass_xt_iclass_rsil_args, 5570 6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, 5571 { 1, Iclass_xt_iclass_rsr_lend_args, 5572 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, 5573 { 1, Iclass_xt_iclass_wsr_lend_args, 5574 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, 5575 { 1, Iclass_xt_iclass_xsr_lend_args, 5576 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, 5577 { 1, Iclass_xt_iclass_rsr_lcount_args, 5578 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, 5579 { 1, Iclass_xt_iclass_wsr_lcount_args, 5580 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, 5581 { 1, Iclass_xt_iclass_xsr_lcount_args, 5582 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, 5583 { 1, Iclass_xt_iclass_rsr_lbeg_args, 5584 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, 5585 { 1, Iclass_xt_iclass_wsr_lbeg_args, 5586 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, 5587 { 1, Iclass_xt_iclass_xsr_lbeg_args, 5588 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, 5589 { 1, Iclass_xt_iclass_rsr_sar_args, 5590 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, 5591 { 1, Iclass_xt_iclass_wsr_sar_args, 5592 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, 5593 { 1, Iclass_xt_iclass_xsr_sar_args, 5594 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, 5595 { 1, Iclass_xt_iclass_rsr_memctl_args, 5596 0, 0, 0, 0 }, 5597 { 1, Iclass_xt_iclass_wsr_memctl_args, 5598 0, 0, 0, 0 }, 5599 { 1, Iclass_xt_iclass_xsr_memctl_args, 5600 0, 0, 0, 0 }, 5601 { 1, Iclass_xt_iclass_rsr_litbase_args, 5602 0, 0, 0, 0 }, 5603 { 1, Iclass_xt_iclass_wsr_litbase_args, 5604 0, 0, 0, 0 }, 5605 { 1, Iclass_xt_iclass_xsr_litbase_args, 5606 0, 0, 0, 0 }, 5607 { 1, Iclass_xt_iclass_rsr_configid0_args, 5608 0, 0, 0, 0 }, 5609 { 1, Iclass_xt_iclass_wsr_configid0_args, 5610 0, 0, 0, 0 }, 5611 { 1, Iclass_xt_iclass_rsr_configid1_args, 5612 0, 0, 0, 0 }, 5613 { 1, Iclass_xt_iclass_rsr_ps_args, 5614 6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, 5615 { 1, Iclass_xt_iclass_wsr_ps_args, 5616 6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, 5617 { 1, Iclass_xt_iclass_xsr_ps_args, 5618 6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, 5619 { 1, Iclass_xt_iclass_rsr_epc1_args, 5620 1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, 5621 { 1, Iclass_xt_iclass_wsr_epc1_args, 5622 1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, 5623 { 1, Iclass_xt_iclass_xsr_epc1_args, 5624 1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, 5625 { 1, Iclass_xt_iclass_rsr_excsave1_args, 5626 1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, 5627 { 1, Iclass_xt_iclass_wsr_excsave1_args, 5628 1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, 5629 { 1, Iclass_xt_iclass_xsr_excsave1_args, 5630 1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, 5631 { 1, Iclass_xt_iclass_rsr_epc2_args, 5632 1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, 5633 { 1, Iclass_xt_iclass_wsr_epc2_args, 5634 1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, 5635 { 1, Iclass_xt_iclass_xsr_epc2_args, 5636 1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, 5637 { 1, Iclass_xt_iclass_rsr_excsave2_args, 5638 1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, 5639 { 1, Iclass_xt_iclass_wsr_excsave2_args, 5640 1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, 5641 { 1, Iclass_xt_iclass_xsr_excsave2_args, 5642 1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, 5643 { 1, Iclass_xt_iclass_rsr_epc3_args, 5644 1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, 5645 { 1, Iclass_xt_iclass_wsr_epc3_args, 5646 1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, 5647 { 1, Iclass_xt_iclass_xsr_epc3_args, 5648 1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, 5649 { 1, Iclass_xt_iclass_rsr_excsave3_args, 5650 1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, 5651 { 1, Iclass_xt_iclass_wsr_excsave3_args, 5652 1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, 5653 { 1, Iclass_xt_iclass_xsr_excsave3_args, 5654 1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, 5655 { 1, Iclass_xt_iclass_rsr_epc4_args, 5656 1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, 5657 { 1, Iclass_xt_iclass_wsr_epc4_args, 5658 1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, 5659 { 1, Iclass_xt_iclass_xsr_epc4_args, 5660 1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, 5661 { 1, Iclass_xt_iclass_rsr_excsave4_args, 5662 1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, 5663 { 1, Iclass_xt_iclass_wsr_excsave4_args, 5664 1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, 5665 { 1, Iclass_xt_iclass_xsr_excsave4_args, 5666 1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, 5667 { 1, Iclass_xt_iclass_rsr_epc5_args, 5668 1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, 5669 { 1, Iclass_xt_iclass_wsr_epc5_args, 5670 1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, 5671 { 1, Iclass_xt_iclass_xsr_epc5_args, 5672 1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, 5673 { 1, Iclass_xt_iclass_rsr_excsave5_args, 5674 1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, 5675 { 1, Iclass_xt_iclass_wsr_excsave5_args, 5676 1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, 5677 { 1, Iclass_xt_iclass_xsr_excsave5_args, 5678 1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, 5679 { 1, Iclass_xt_iclass_rsr_epc6_args, 5680 1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, 5681 { 1, Iclass_xt_iclass_wsr_epc6_args, 5682 1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, 5683 { 1, Iclass_xt_iclass_xsr_epc6_args, 5684 1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, 5685 { 1, Iclass_xt_iclass_rsr_excsave6_args, 5686 1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, 5687 { 1, Iclass_xt_iclass_wsr_excsave6_args, 5688 1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, 5689 { 1, Iclass_xt_iclass_xsr_excsave6_args, 5690 1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, 5691 { 1, Iclass_xt_iclass_rsr_epc7_args, 5692 1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, 5693 { 1, Iclass_xt_iclass_wsr_epc7_args, 5694 1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, 5695 { 1, Iclass_xt_iclass_xsr_epc7_args, 5696 1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, 5697 { 1, Iclass_xt_iclass_rsr_excsave7_args, 5698 1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, 5699 { 1, Iclass_xt_iclass_wsr_excsave7_args, 5700 1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, 5701 { 1, Iclass_xt_iclass_xsr_excsave7_args, 5702 1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, 5703 { 1, Iclass_xt_iclass_rsr_eps2_args, 5704 1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, 5705 { 1, Iclass_xt_iclass_wsr_eps2_args, 5706 1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, 5707 { 1, Iclass_xt_iclass_xsr_eps2_args, 5708 1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, 5709 { 1, Iclass_xt_iclass_rsr_eps3_args, 5710 1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, 5711 { 1, Iclass_xt_iclass_wsr_eps3_args, 5712 1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, 5713 { 1, Iclass_xt_iclass_xsr_eps3_args, 5714 1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, 5715 { 1, Iclass_xt_iclass_rsr_eps4_args, 5716 1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, 5717 { 1, Iclass_xt_iclass_wsr_eps4_args, 5718 1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, 5719 { 1, Iclass_xt_iclass_xsr_eps4_args, 5720 1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, 5721 { 1, Iclass_xt_iclass_rsr_eps5_args, 5722 1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, 5723 { 1, Iclass_xt_iclass_wsr_eps5_args, 5724 1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, 5725 { 1, Iclass_xt_iclass_xsr_eps5_args, 5726 1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, 5727 { 1, Iclass_xt_iclass_rsr_eps6_args, 5728 1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, 5729 { 1, Iclass_xt_iclass_wsr_eps6_args, 5730 1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, 5731 { 1, Iclass_xt_iclass_xsr_eps6_args, 5732 1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, 5733 { 1, Iclass_xt_iclass_rsr_eps7_args, 5734 1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, 5735 { 1, Iclass_xt_iclass_wsr_eps7_args, 5736 1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, 5737 { 1, Iclass_xt_iclass_xsr_eps7_args, 5738 1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, 5739 { 1, Iclass_xt_iclass_rsr_excvaddr_args, 5740 1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, 5741 { 1, Iclass_xt_iclass_wsr_excvaddr_args, 5742 1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, 5743 { 1, Iclass_xt_iclass_xsr_excvaddr_args, 5744 1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, 5745 { 1, Iclass_xt_iclass_rsr_depc_args, 5746 1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, 5747 { 1, Iclass_xt_iclass_wsr_depc_args, 5748 1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, 5749 { 1, Iclass_xt_iclass_xsr_depc_args, 5750 1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, 5751 { 1, Iclass_xt_iclass_rsr_exccause_args, 5752 2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, 5753 { 1, Iclass_xt_iclass_wsr_exccause_args, 5754 1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, 5755 { 1, Iclass_xt_iclass_xsr_exccause_args, 5756 1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, 5757 { 1, Iclass_xt_iclass_rsr_misc0_args, 5758 1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, 5759 { 1, Iclass_xt_iclass_wsr_misc0_args, 5760 1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, 5761 { 1, Iclass_xt_iclass_xsr_misc0_args, 5762 1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, 5763 { 1, Iclass_xt_iclass_rsr_misc1_args, 5764 1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, 5765 { 1, Iclass_xt_iclass_wsr_misc1_args, 5766 1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, 5767 { 1, Iclass_xt_iclass_xsr_misc1_args, 5768 1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, 5769 { 1, Iclass_xt_iclass_rsr_prid_args, 5770 0, 0, 0, 0 }, 5771 { 1, Iclass_xt_iclass_rsr_vecbase_args, 5772 1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, 5773 { 1, Iclass_xt_iclass_wsr_vecbase_args, 5774 1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, 5775 { 1, Iclass_xt_iclass_xsr_vecbase_args, 5776 1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, 5777 { 3, Iclass_xt_mul16_args, 5778 0, 0, 0, 0 }, 5779 { 3, Iclass_xt_mul32_args, 5780 0, 0, 0, 0 }, 5781 { 2, Iclass_xt_iclass_mac16_aa_args, 5782 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, 5783 { 2, Iclass_xt_iclass_mac16_ad_args, 5784 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, 5785 { 2, Iclass_xt_iclass_mac16_da_args, 5786 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, 5787 { 2, Iclass_xt_iclass_mac16_dd_args, 5788 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, 5789 { 2, Iclass_xt_iclass_mac16a_aa_args, 5790 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, 5791 { 2, Iclass_xt_iclass_mac16a_ad_args, 5792 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, 5793 { 2, Iclass_xt_iclass_mac16a_da_args, 5794 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, 5795 { 2, Iclass_xt_iclass_mac16a_dd_args, 5796 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, 5797 { 4, Iclass_xt_iclass_mac16al_da_args, 5798 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, 5799 { 4, Iclass_xt_iclass_mac16al_dd_args, 5800 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, 5801 { 2, Iclass_xt_iclass_mac16_l_args, 5802 0, 0, 0, 0 }, 5803 { 2, Iclass_xt_iclass_rsr_m0_args, 5804 0, 0, 0, 0 }, 5805 { 2, Iclass_xt_iclass_wsr_m0_args, 5806 0, 0, 0, 0 }, 5807 { 2, Iclass_xt_iclass_xsr_m0_args, 5808 0, 0, 0, 0 }, 5809 { 2, Iclass_xt_iclass_rsr_m1_args, 5810 0, 0, 0, 0 }, 5811 { 2, Iclass_xt_iclass_wsr_m1_args, 5812 0, 0, 0, 0 }, 5813 { 2, Iclass_xt_iclass_xsr_m1_args, 5814 0, 0, 0, 0 }, 5815 { 2, Iclass_xt_iclass_rsr_m2_args, 5816 0, 0, 0, 0 }, 5817 { 2, Iclass_xt_iclass_wsr_m2_args, 5818 0, 0, 0, 0 }, 5819 { 2, Iclass_xt_iclass_xsr_m2_args, 5820 0, 0, 0, 0 }, 5821 { 2, Iclass_xt_iclass_rsr_m3_args, 5822 0, 0, 0, 0 }, 5823 { 2, Iclass_xt_iclass_wsr_m3_args, 5824 0, 0, 0, 0 }, 5825 { 2, Iclass_xt_iclass_xsr_m3_args, 5826 0, 0, 0, 0 }, 5827 { 1, Iclass_xt_iclass_rsr_acclo_args, 5828 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, 5829 { 1, Iclass_xt_iclass_wsr_acclo_args, 5830 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, 5831 { 1, Iclass_xt_iclass_xsr_acclo_args, 5832 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, 5833 { 1, Iclass_xt_iclass_rsr_acchi_args, 5834 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, 5835 { 1, Iclass_xt_iclass_wsr_acchi_args, 5836 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, 5837 { 1, Iclass_xt_iclass_xsr_acchi_args, 5838 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, 5839 { 1, Iclass_xt_iclass_rfi_args, 5840 20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, 5841 { 1, Iclass_xt_iclass_wait_args, 5842 1, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, 5843 { 1, Iclass_xt_iclass_rsr_interrupt_args, 5844 1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, 5845 { 1, Iclass_xt_iclass_wsr_intset_args, 5846 2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, 5847 { 1, Iclass_xt_iclass_wsr_intclear_args, 5848 2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, 5849 { 1, Iclass_xt_iclass_rsr_intenable_args, 5850 1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, 5851 { 1, Iclass_xt_iclass_wsr_intenable_args, 5852 1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, 5853 { 1, Iclass_xt_iclass_xsr_intenable_args, 5854 1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, 5855 { 2, Iclass_xt_iclass_break_args, 5856 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, 5857 { 1, Iclass_xt_iclass_break_n_args, 5858 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, 5859 { 1, Iclass_xt_iclass_rsr_dbreaka0_args, 5860 1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, 5861 { 1, Iclass_xt_iclass_wsr_dbreaka0_args, 5862 2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, 5863 { 1, Iclass_xt_iclass_xsr_dbreaka0_args, 5864 2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, 5865 { 1, Iclass_xt_iclass_rsr_dbreakc0_args, 5866 1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, 5867 { 1, Iclass_xt_iclass_wsr_dbreakc0_args, 5868 2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, 5869 { 1, Iclass_xt_iclass_xsr_dbreakc0_args, 5870 2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, 5871 { 1, Iclass_xt_iclass_rsr_dbreaka1_args, 5872 1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, 5873 { 1, Iclass_xt_iclass_wsr_dbreaka1_args, 5874 2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, 5875 { 1, Iclass_xt_iclass_xsr_dbreaka1_args, 5876 2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, 5877 { 1, Iclass_xt_iclass_rsr_dbreakc1_args, 5878 1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, 5879 { 1, Iclass_xt_iclass_wsr_dbreakc1_args, 5880 2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, 5881 { 1, Iclass_xt_iclass_xsr_dbreakc1_args, 5882 2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, 5883 { 1, Iclass_xt_iclass_rsr_ibreaka0_args, 5884 1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, 5885 { 1, Iclass_xt_iclass_wsr_ibreaka0_args, 5886 1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, 5887 { 1, Iclass_xt_iclass_xsr_ibreaka0_args, 5888 1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, 5889 { 1, Iclass_xt_iclass_rsr_ibreaka1_args, 5890 1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, 5891 { 1, Iclass_xt_iclass_wsr_ibreaka1_args, 5892 1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, 5893 { 1, Iclass_xt_iclass_xsr_ibreaka1_args, 5894 1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, 5895 { 1, Iclass_xt_iclass_rsr_ibreakenable_args, 5896 1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, 5897 { 1, Iclass_xt_iclass_wsr_ibreakenable_args, 5898 1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, 5899 { 1, Iclass_xt_iclass_xsr_ibreakenable_args, 5900 1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, 5901 { 1, Iclass_xt_iclass_rsr_debugcause_args, 5902 2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, 5903 { 1, Iclass_xt_iclass_wsr_debugcause_args, 5904 2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, 5905 { 1, Iclass_xt_iclass_xsr_debugcause_args, 5906 2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, 5907 { 1, Iclass_xt_iclass_rsr_icount_args, 5908 1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, 5909 { 1, Iclass_xt_iclass_wsr_icount_args, 5910 2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, 5911 { 1, Iclass_xt_iclass_xsr_icount_args, 5912 2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, 5913 { 1, Iclass_xt_iclass_rsr_icountlevel_args, 5914 1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, 5915 { 1, Iclass_xt_iclass_wsr_icountlevel_args, 5916 1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, 5917 { 1, Iclass_xt_iclass_xsr_icountlevel_args, 5918 1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, 5919 { 1, Iclass_xt_iclass_rsr_ddr_args, 5920 1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, 5921 { 1, Iclass_xt_iclass_wsr_ddr_args, 5922 2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, 5923 { 1, Iclass_xt_iclass_xsr_ddr_args, 5924 2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, 5925 { 1, Iclass_xt_iclass_lddr32_p_args, 5926 3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, 5927 { 1, Iclass_xt_iclass_sddr32_p_args, 5928 2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, 5929 { 1, Iclass_xt_iclass_rfdo_args, 5930 9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, 5931 { 0, 0 /* xt_iclass_rfdd */, 5932 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, 5933 { 1, Iclass_xt_iclass_wsr_mmid_args, 5934 1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, 5935 { 1, Iclass_xt_iclass_rsr_ccount_args, 5936 1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, 5937 { 1, Iclass_xt_iclass_wsr_ccount_args, 5938 2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, 5939 { 1, Iclass_xt_iclass_xsr_ccount_args, 5940 2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, 5941 { 1, Iclass_xt_iclass_rsr_ccompare0_args, 5942 1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, 5943 { 1, Iclass_xt_iclass_wsr_ccompare0_args, 5944 2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, 5945 { 1, Iclass_xt_iclass_xsr_ccompare0_args, 5946 2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, 5947 { 1, Iclass_xt_iclass_rsr_ccompare1_args, 5948 1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, 5949 { 1, Iclass_xt_iclass_wsr_ccompare1_args, 5950 2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, 5951 { 1, Iclass_xt_iclass_xsr_ccompare1_args, 5952 2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, 5953 { 1, Iclass_xt_iclass_rsr_ccompare2_args, 5954 1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, 5955 { 1, Iclass_xt_iclass_wsr_ccompare2_args, 5956 2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, 5957 { 1, Iclass_xt_iclass_xsr_ccompare2_args, 5958 2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, 5959 { 2, Iclass_xt_iclass_icache_args, 5960 0, 0, 0, 0 }, 5961 { 2, Iclass_xt_iclass_icache_lock_args, 5962 0, 0, 0, 0 }, 5963 { 2, Iclass_xt_iclass_icache_inv_args, 5964 0, 0, 0, 0 }, 5965 { 2, Iclass_xt_iclass_licx_args, 5966 0, 0, 0, 0 }, 5967 { 2, Iclass_xt_iclass_sicx_args, 5968 0, 0, 0, 0 }, 5969 { 2, Iclass_xt_iclass_dcache_args, 5970 0, 0, 0, 0 }, 5971 { 1, Iclass_xt_iclass_dcache_dyn_args, 5972 0, 0, 0, 0 }, 5973 { 2, Iclass_xt_iclass_dcache_ind_args, 5974 0, 0, 0, 0 }, 5975 { 2, Iclass_xt_iclass_dcache_inv_args, 5976 0, 0, 0, 0 }, 5977 { 2, Iclass_xt_iclass_dpf_args, 5978 0, 0, 0, 0 }, 5979 { 2, Iclass_xt_iclass_dcache_lock_args, 5980 0, 0, 0, 0 }, 5981 { 2, Iclass_xt_iclass_sdct_args, 5982 0, 0, 0, 0 }, 5983 { 2, Iclass_xt_iclass_ldct_args, 5984 0, 0, 0, 0 }, 5985 { 1, Iclass_xt_iclass_idtlb_args, 5986 1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, 5987 { 2, Iclass_xt_iclass_rdtlb_args, 5988 0, 0, 0, 0 }, 5989 { 2, Iclass_xt_iclass_wdtlb_args, 5990 1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, 5991 { 1, Iclass_xt_iclass_iitlb_args, 5992 0, 0, 0, 0 }, 5993 { 2, Iclass_xt_iclass_ritlb_args, 5994 0, 0, 0, 0 }, 5995 { 2, Iclass_xt_iclass_witlb_args, 5996 0, 0, 0, 0 }, 5997 { 3, Iclass_xt_iclass_clamp_args, 5998 0, 0, 0, 0 }, 5999 { 3, Iclass_xt_iclass_minmax_args, 6000 0, 0, 0, 0 }, 6001 { 2, Iclass_xt_iclass_nsa_args, 6002 0, 0, 0, 0 }, 6003 { 3, Iclass_xt_iclass_sx_args, 6004 0, 0, 0, 0 }, 6005 { 3, Iclass_xt_iclass_l32ai_args, 6006 0, 0, 0, 0 }, 6007 { 3, Iclass_xt_iclass_s32ri_args, 6008 0, 0, 0, 0 }, 6009 { 3, Iclass_xt_iclass_s32c1i_args, 6010 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, 6011 { 1, Iclass_xt_iclass_rsr_scompare1_args, 6012 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, 6013 { 1, Iclass_xt_iclass_wsr_scompare1_args, 6014 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, 6015 { 1, Iclass_xt_iclass_xsr_scompare1_args, 6016 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, 6017 { 1, Iclass_xt_iclass_rsr_atomctl_args, 6018 1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, 6019 { 1, Iclass_xt_iclass_wsr_atomctl_args, 6020 2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, 6021 { 1, Iclass_xt_iclass_xsr_atomctl_args, 6022 2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, 6023 { 3, Iclass_xt_iclass_div_args, 6024 0, 0, 0, 0 }, 6025 { 2, Iclass_xt_iclass_rer_args, 6026 1, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, 6027 { 2, Iclass_xt_iclass_wer_args, 6028 1, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, 6029 { 1, Iclass_rur_expstate_args, 6030 1, Iclass_rur_expstate_stateArgs, 0, 0 }, 6031 { 1, Iclass_wur_expstate_args, 6032 1, Iclass_wur_expstate_stateArgs, 0, 0 }, 6033 { 1, Iclass_iclass_READ_IMPWIRE_args, 6034 0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, 6035 { 1, Iclass_iclass_SETB_EXPSTATE_args, 6036 1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, 6037 { 1, Iclass_iclass_CLRB_EXPSTATE_args, 6038 1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, 6039 { 2, Iclass_iclass_WRMSK_EXPSTATE_args, 6040 1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } 6041}; 6042 6043enum xtensa_iclass_id { 6044 ICLASS_xt_iclass_excw, 6045 ICLASS_xt_iclass_rfe, 6046 ICLASS_xt_iclass_rfde, 6047 ICLASS_xt_iclass_syscall, 6048 ICLASS_xt_iclass_call12, 6049 ICLASS_xt_iclass_call8, 6050 ICLASS_xt_iclass_call4, 6051 ICLASS_xt_iclass_callx12, 6052 ICLASS_xt_iclass_callx8, 6053 ICLASS_xt_iclass_callx4, 6054 ICLASS_xt_iclass_entry, 6055 ICLASS_xt_iclass_movsp, 6056 ICLASS_xt_iclass_rotw, 6057 ICLASS_xt_iclass_retw, 6058 ICLASS_xt_iclass_rfwou, 6059 ICLASS_xt_iclass_l32e, 6060 ICLASS_xt_iclass_s32e, 6061 ICLASS_xt_iclass_rsr_windowbase, 6062 ICLASS_xt_iclass_wsr_windowbase, 6063 ICLASS_xt_iclass_xsr_windowbase, 6064 ICLASS_xt_iclass_rsr_windowstart, 6065 ICLASS_xt_iclass_wsr_windowstart, 6066 ICLASS_xt_iclass_xsr_windowstart, 6067 ICLASS_xt_iclass_add_n, 6068 ICLASS_xt_iclass_addi_n, 6069 ICLASS_xt_iclass_bz6, 6070 ICLASS_xt_iclass_ill_n, 6071 ICLASS_xt_iclass_loadi4, 6072 ICLASS_xt_iclass_mov_n, 6073 ICLASS_xt_iclass_movi_n, 6074 ICLASS_xt_iclass_nopn, 6075 ICLASS_xt_iclass_retn, 6076 ICLASS_xt_iclass_storei4, 6077 ICLASS_xt_iclass_addi, 6078 ICLASS_xt_iclass_addmi, 6079 ICLASS_xt_iclass_addsub, 6080 ICLASS_xt_iclass_bit, 6081 ICLASS_xt_iclass_bsi8, 6082 ICLASS_xt_iclass_bsi8b, 6083 ICLASS_xt_iclass_bsi8u, 6084 ICLASS_xt_iclass_bst8, 6085 ICLASS_xt_iclass_bsz12, 6086 ICLASS_xt_iclass_call0, 6087 ICLASS_xt_iclass_callx0, 6088 ICLASS_xt_iclass_exti, 6089 ICLASS_xt_iclass_ill, 6090 ICLASS_xt_iclass_jump, 6091 ICLASS_xt_iclass_jumpx, 6092 ICLASS_xt_iclass_l16ui, 6093 ICLASS_xt_iclass_l16si, 6094 ICLASS_xt_iclass_l32i, 6095 ICLASS_xt_iclass_l32r, 6096 ICLASS_xt_iclass_l8i, 6097 ICLASS_xt_iclass_loop, 6098 ICLASS_xt_iclass_loopz, 6099 ICLASS_xt_iclass_movi, 6100 ICLASS_xt_iclass_movz, 6101 ICLASS_xt_iclass_neg, 6102 ICLASS_xt_iclass_nop, 6103 ICLASS_xt_iclass_return, 6104 ICLASS_xt_iclass_simcall, 6105 ICLASS_xt_iclass_s16i, 6106 ICLASS_xt_iclass_s32i, 6107 ICLASS_xt_iclass_s32nb, 6108 ICLASS_xt_iclass_s8i, 6109 ICLASS_xt_iclass_sar, 6110 ICLASS_xt_iclass_sari, 6111 ICLASS_xt_iclass_shifts, 6112 ICLASS_xt_iclass_shiftst, 6113 ICLASS_xt_iclass_shiftt, 6114 ICLASS_xt_iclass_slli, 6115 ICLASS_xt_iclass_srai, 6116 ICLASS_xt_iclass_srli, 6117 ICLASS_xt_iclass_memw, 6118 ICLASS_xt_iclass_extw, 6119 ICLASS_xt_iclass_isync, 6120 ICLASS_xt_iclass_sync, 6121 ICLASS_xt_iclass_rsil, 6122 ICLASS_xt_iclass_rsr_lend, 6123 ICLASS_xt_iclass_wsr_lend, 6124 ICLASS_xt_iclass_xsr_lend, 6125 ICLASS_xt_iclass_rsr_lcount, 6126 ICLASS_xt_iclass_wsr_lcount, 6127 ICLASS_xt_iclass_xsr_lcount, 6128 ICLASS_xt_iclass_rsr_lbeg, 6129 ICLASS_xt_iclass_wsr_lbeg, 6130 ICLASS_xt_iclass_xsr_lbeg, 6131 ICLASS_xt_iclass_rsr_sar, 6132 ICLASS_xt_iclass_wsr_sar, 6133 ICLASS_xt_iclass_xsr_sar, 6134 ICLASS_xt_iclass_rsr_memctl, 6135 ICLASS_xt_iclass_wsr_memctl, 6136 ICLASS_xt_iclass_xsr_memctl, 6137 ICLASS_xt_iclass_rsr_litbase, 6138 ICLASS_xt_iclass_wsr_litbase, 6139 ICLASS_xt_iclass_xsr_litbase, 6140 ICLASS_xt_iclass_rsr_configid0, 6141 ICLASS_xt_iclass_wsr_configid0, 6142 ICLASS_xt_iclass_rsr_configid1, 6143 ICLASS_xt_iclass_rsr_ps, 6144 ICLASS_xt_iclass_wsr_ps, 6145 ICLASS_xt_iclass_xsr_ps, 6146 ICLASS_xt_iclass_rsr_epc1, 6147 ICLASS_xt_iclass_wsr_epc1, 6148 ICLASS_xt_iclass_xsr_epc1, 6149 ICLASS_xt_iclass_rsr_excsave1, 6150 ICLASS_xt_iclass_wsr_excsave1, 6151 ICLASS_xt_iclass_xsr_excsave1, 6152 ICLASS_xt_iclass_rsr_epc2, 6153 ICLASS_xt_iclass_wsr_epc2, 6154 ICLASS_xt_iclass_xsr_epc2, 6155 ICLASS_xt_iclass_rsr_excsave2, 6156 ICLASS_xt_iclass_wsr_excsave2, 6157 ICLASS_xt_iclass_xsr_excsave2, 6158 ICLASS_xt_iclass_rsr_epc3, 6159 ICLASS_xt_iclass_wsr_epc3, 6160 ICLASS_xt_iclass_xsr_epc3, 6161 ICLASS_xt_iclass_rsr_excsave3, 6162 ICLASS_xt_iclass_wsr_excsave3, 6163 ICLASS_xt_iclass_xsr_excsave3, 6164 ICLASS_xt_iclass_rsr_epc4, 6165 ICLASS_xt_iclass_wsr_epc4, 6166 ICLASS_xt_iclass_xsr_epc4, 6167 ICLASS_xt_iclass_rsr_excsave4, 6168 ICLASS_xt_iclass_wsr_excsave4, 6169 ICLASS_xt_iclass_xsr_excsave4, 6170 ICLASS_xt_iclass_rsr_epc5, 6171 ICLASS_xt_iclass_wsr_epc5, 6172 ICLASS_xt_iclass_xsr_epc5, 6173 ICLASS_xt_iclass_rsr_excsave5, 6174 ICLASS_xt_iclass_wsr_excsave5, 6175 ICLASS_xt_iclass_xsr_excsave5, 6176 ICLASS_xt_iclass_rsr_epc6, 6177 ICLASS_xt_iclass_wsr_epc6, 6178 ICLASS_xt_iclass_xsr_epc6, 6179 ICLASS_xt_iclass_rsr_excsave6, 6180 ICLASS_xt_iclass_wsr_excsave6, 6181 ICLASS_xt_iclass_xsr_excsave6, 6182 ICLASS_xt_iclass_rsr_epc7, 6183 ICLASS_xt_iclass_wsr_epc7, 6184 ICLASS_xt_iclass_xsr_epc7, 6185 ICLASS_xt_iclass_rsr_excsave7, 6186 ICLASS_xt_iclass_wsr_excsave7, 6187 ICLASS_xt_iclass_xsr_excsave7, 6188 ICLASS_xt_iclass_rsr_eps2, 6189 ICLASS_xt_iclass_wsr_eps2, 6190 ICLASS_xt_iclass_xsr_eps2, 6191 ICLASS_xt_iclass_rsr_eps3, 6192 ICLASS_xt_iclass_wsr_eps3, 6193 ICLASS_xt_iclass_xsr_eps3, 6194 ICLASS_xt_iclass_rsr_eps4, 6195 ICLASS_xt_iclass_wsr_eps4, 6196 ICLASS_xt_iclass_xsr_eps4, 6197 ICLASS_xt_iclass_rsr_eps5, 6198 ICLASS_xt_iclass_wsr_eps5, 6199 ICLASS_xt_iclass_xsr_eps5, 6200 ICLASS_xt_iclass_rsr_eps6, 6201 ICLASS_xt_iclass_wsr_eps6, 6202 ICLASS_xt_iclass_xsr_eps6, 6203 ICLASS_xt_iclass_rsr_eps7, 6204 ICLASS_xt_iclass_wsr_eps7, 6205 ICLASS_xt_iclass_xsr_eps7, 6206 ICLASS_xt_iclass_rsr_excvaddr, 6207 ICLASS_xt_iclass_wsr_excvaddr, 6208 ICLASS_xt_iclass_xsr_excvaddr, 6209 ICLASS_xt_iclass_rsr_depc, 6210 ICLASS_xt_iclass_wsr_depc, 6211 ICLASS_xt_iclass_xsr_depc, 6212 ICLASS_xt_iclass_rsr_exccause, 6213 ICLASS_xt_iclass_wsr_exccause, 6214 ICLASS_xt_iclass_xsr_exccause, 6215 ICLASS_xt_iclass_rsr_misc0, 6216 ICLASS_xt_iclass_wsr_misc0, 6217 ICLASS_xt_iclass_xsr_misc0, 6218 ICLASS_xt_iclass_rsr_misc1, 6219 ICLASS_xt_iclass_wsr_misc1, 6220 ICLASS_xt_iclass_xsr_misc1, 6221 ICLASS_xt_iclass_rsr_prid, 6222 ICLASS_xt_iclass_rsr_vecbase, 6223 ICLASS_xt_iclass_wsr_vecbase, 6224 ICLASS_xt_iclass_xsr_vecbase, 6225 ICLASS_xt_mul16, 6226 ICLASS_xt_mul32, 6227 ICLASS_xt_iclass_mac16_aa, 6228 ICLASS_xt_iclass_mac16_ad, 6229 ICLASS_xt_iclass_mac16_da, 6230 ICLASS_xt_iclass_mac16_dd, 6231 ICLASS_xt_iclass_mac16a_aa, 6232 ICLASS_xt_iclass_mac16a_ad, 6233 ICLASS_xt_iclass_mac16a_da, 6234 ICLASS_xt_iclass_mac16a_dd, 6235 ICLASS_xt_iclass_mac16al_da, 6236 ICLASS_xt_iclass_mac16al_dd, 6237 ICLASS_xt_iclass_mac16_l, 6238 ICLASS_xt_iclass_rsr_m0, 6239 ICLASS_xt_iclass_wsr_m0, 6240 ICLASS_xt_iclass_xsr_m0, 6241 ICLASS_xt_iclass_rsr_m1, 6242 ICLASS_xt_iclass_wsr_m1, 6243 ICLASS_xt_iclass_xsr_m1, 6244 ICLASS_xt_iclass_rsr_m2, 6245 ICLASS_xt_iclass_wsr_m2, 6246 ICLASS_xt_iclass_xsr_m2, 6247 ICLASS_xt_iclass_rsr_m3, 6248 ICLASS_xt_iclass_wsr_m3, 6249 ICLASS_xt_iclass_xsr_m3, 6250 ICLASS_xt_iclass_rsr_acclo, 6251 ICLASS_xt_iclass_wsr_acclo, 6252 ICLASS_xt_iclass_xsr_acclo, 6253 ICLASS_xt_iclass_rsr_acchi, 6254 ICLASS_xt_iclass_wsr_acchi, 6255 ICLASS_xt_iclass_xsr_acchi, 6256 ICLASS_xt_iclass_rfi, 6257 ICLASS_xt_iclass_wait, 6258 ICLASS_xt_iclass_rsr_interrupt, 6259 ICLASS_xt_iclass_wsr_intset, 6260 ICLASS_xt_iclass_wsr_intclear, 6261 ICLASS_xt_iclass_rsr_intenable, 6262 ICLASS_xt_iclass_wsr_intenable, 6263 ICLASS_xt_iclass_xsr_intenable, 6264 ICLASS_xt_iclass_break, 6265 ICLASS_xt_iclass_break_n, 6266 ICLASS_xt_iclass_rsr_dbreaka0, 6267 ICLASS_xt_iclass_wsr_dbreaka0, 6268 ICLASS_xt_iclass_xsr_dbreaka0, 6269 ICLASS_xt_iclass_rsr_dbreakc0, 6270 ICLASS_xt_iclass_wsr_dbreakc0, 6271 ICLASS_xt_iclass_xsr_dbreakc0, 6272 ICLASS_xt_iclass_rsr_dbreaka1, 6273 ICLASS_xt_iclass_wsr_dbreaka1, 6274 ICLASS_xt_iclass_xsr_dbreaka1, 6275 ICLASS_xt_iclass_rsr_dbreakc1, 6276 ICLASS_xt_iclass_wsr_dbreakc1, 6277 ICLASS_xt_iclass_xsr_dbreakc1, 6278 ICLASS_xt_iclass_rsr_ibreaka0, 6279 ICLASS_xt_iclass_wsr_ibreaka0, 6280 ICLASS_xt_iclass_xsr_ibreaka0, 6281 ICLASS_xt_iclass_rsr_ibreaka1, 6282 ICLASS_xt_iclass_wsr_ibreaka1, 6283 ICLASS_xt_iclass_xsr_ibreaka1, 6284 ICLASS_xt_iclass_rsr_ibreakenable, 6285 ICLASS_xt_iclass_wsr_ibreakenable, 6286 ICLASS_xt_iclass_xsr_ibreakenable, 6287 ICLASS_xt_iclass_rsr_debugcause, 6288 ICLASS_xt_iclass_wsr_debugcause, 6289 ICLASS_xt_iclass_xsr_debugcause, 6290 ICLASS_xt_iclass_rsr_icount, 6291 ICLASS_xt_iclass_wsr_icount, 6292 ICLASS_xt_iclass_xsr_icount, 6293 ICLASS_xt_iclass_rsr_icountlevel, 6294 ICLASS_xt_iclass_wsr_icountlevel, 6295 ICLASS_xt_iclass_xsr_icountlevel, 6296 ICLASS_xt_iclass_rsr_ddr, 6297 ICLASS_xt_iclass_wsr_ddr, 6298 ICLASS_xt_iclass_xsr_ddr, 6299 ICLASS_xt_iclass_lddr32_p, 6300 ICLASS_xt_iclass_sddr32_p, 6301 ICLASS_xt_iclass_rfdo, 6302 ICLASS_xt_iclass_rfdd, 6303 ICLASS_xt_iclass_wsr_mmid, 6304 ICLASS_xt_iclass_rsr_ccount, 6305 ICLASS_xt_iclass_wsr_ccount, 6306 ICLASS_xt_iclass_xsr_ccount, 6307 ICLASS_xt_iclass_rsr_ccompare0, 6308 ICLASS_xt_iclass_wsr_ccompare0, 6309 ICLASS_xt_iclass_xsr_ccompare0, 6310 ICLASS_xt_iclass_rsr_ccompare1, 6311 ICLASS_xt_iclass_wsr_ccompare1, 6312 ICLASS_xt_iclass_xsr_ccompare1, 6313 ICLASS_xt_iclass_rsr_ccompare2, 6314 ICLASS_xt_iclass_wsr_ccompare2, 6315 ICLASS_xt_iclass_xsr_ccompare2, 6316 ICLASS_xt_iclass_icache, 6317 ICLASS_xt_iclass_icache_lock, 6318 ICLASS_xt_iclass_icache_inv, 6319 ICLASS_xt_iclass_licx, 6320 ICLASS_xt_iclass_sicx, 6321 ICLASS_xt_iclass_dcache, 6322 ICLASS_xt_iclass_dcache_dyn, 6323 ICLASS_xt_iclass_dcache_ind, 6324 ICLASS_xt_iclass_dcache_inv, 6325 ICLASS_xt_iclass_dpf, 6326 ICLASS_xt_iclass_dcache_lock, 6327 ICLASS_xt_iclass_sdct, 6328 ICLASS_xt_iclass_ldct, 6329 ICLASS_xt_iclass_idtlb, 6330 ICLASS_xt_iclass_rdtlb, 6331 ICLASS_xt_iclass_wdtlb, 6332 ICLASS_xt_iclass_iitlb, 6333 ICLASS_xt_iclass_ritlb, 6334 ICLASS_xt_iclass_witlb, 6335 ICLASS_xt_iclass_clamp, 6336 ICLASS_xt_iclass_minmax, 6337 ICLASS_xt_iclass_nsa, 6338 ICLASS_xt_iclass_sx, 6339 ICLASS_xt_iclass_l32ai, 6340 ICLASS_xt_iclass_s32ri, 6341 ICLASS_xt_iclass_s32c1i, 6342 ICLASS_xt_iclass_rsr_scompare1, 6343 ICLASS_xt_iclass_wsr_scompare1, 6344 ICLASS_xt_iclass_xsr_scompare1, 6345 ICLASS_xt_iclass_rsr_atomctl, 6346 ICLASS_xt_iclass_wsr_atomctl, 6347 ICLASS_xt_iclass_xsr_atomctl, 6348 ICLASS_xt_iclass_div, 6349 ICLASS_xt_iclass_rer, 6350 ICLASS_xt_iclass_wer, 6351 ICLASS_rur_expstate, 6352 ICLASS_wur_expstate, 6353 ICLASS_iclass_READ_IMPWIRE, 6354 ICLASS_iclass_SETB_EXPSTATE, 6355 ICLASS_iclass_CLRB_EXPSTATE, 6356 ICLASS_iclass_WRMSK_EXPSTATE 6357}; 6358 6359 6360/* Opcode encodings. */ 6361 6362static void 6363Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6364{ 6365 slotbuf[0] = 0x2080; 6366} 6367 6368static void 6369Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) 6370{ 6371 slotbuf[0] = 0x3000; 6372} 6373 6374static void 6375Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) 6376{ 6377 slotbuf[0] = 0x3200; 6378} 6379 6380static void 6381Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) 6382{ 6383 slotbuf[0] = 0x5000; 6384} 6385 6386static void 6387Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) 6388{ 6389 slotbuf[0] = 0x35; 6390} 6391 6392static void 6393Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6394{ 6395 slotbuf[0] = 0x25; 6396} 6397 6398static void 6399Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6400{ 6401 slotbuf[0] = 0x15; 6402} 6403 6404static void 6405Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) 6406{ 6407 slotbuf[0] = 0xf0; 6408} 6409 6410static void 6411Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6412{ 6413 slotbuf[0] = 0xe0; 6414} 6415 6416static void 6417Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6418{ 6419 slotbuf[0] = 0xd0; 6420} 6421 6422static void 6423Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) 6424{ 6425 slotbuf[0] = 0x36; 6426} 6427 6428static void 6429Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) 6430{ 6431 slotbuf[0] = 0x1000; 6432} 6433 6434static void 6435Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6436{ 6437 slotbuf[0] = 0x408000; 6438} 6439 6440static void 6441Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) 6442{ 6443 slotbuf[0] = 0x90; 6444} 6445 6446static void 6447Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6448{ 6449 slotbuf[0] = 0xf01d; 6450} 6451 6452static void 6453Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 6454{ 6455 slotbuf[0] = 0x3400; 6456} 6457 6458static void 6459Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) 6460{ 6461 slotbuf[0] = 0x3500; 6462} 6463 6464static void 6465Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 6466{ 6467 slotbuf[0] = 0x90000; 6468} 6469 6470static void 6471Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 6472{ 6473 slotbuf[0] = 0x490000; 6474} 6475 6476static void 6477Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 6478{ 6479 slotbuf[0] = 0x34800; 6480} 6481 6482static void 6483Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 6484{ 6485 slotbuf[0] = 0x134800; 6486} 6487 6488static void 6489Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 6490{ 6491 slotbuf[0] = 0x614800; 6492} 6493 6494static void 6495Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 6496{ 6497 slotbuf[0] = 0x34900; 6498} 6499 6500static void 6501Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 6502{ 6503 slotbuf[0] = 0x134900; 6504} 6505 6506static void 6507Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 6508{ 6509 slotbuf[0] = 0x614900; 6510} 6511 6512static void 6513Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6514{ 6515 slotbuf[0] = 0xa; 6516} 6517 6518static void 6519Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6520{ 6521 slotbuf[0] = 0xb; 6522} 6523 6524static void 6525Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6526{ 6527 slotbuf[0] = 0x8c; 6528} 6529 6530static void 6531Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6532{ 6533 slotbuf[0] = 0xcc; 6534} 6535 6536static void 6537Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6538{ 6539 slotbuf[0] = 0xf06d; 6540} 6541 6542static void 6543Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6544{ 6545 slotbuf[0] = 0x8; 6546} 6547 6548static void 6549Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6550{ 6551 slotbuf[0] = 0xd; 6552} 6553 6554static void 6555Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6556{ 6557 slotbuf[0] = 0xc; 6558} 6559 6560static void 6561Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6562{ 6563 slotbuf[0] = 0xf03d; 6564} 6565 6566static void 6567Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 6568{ 6569 slotbuf[0] = 0xf00d; 6570} 6571 6572static void 6573Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 6574{ 6575 slotbuf[0] = 0x9; 6576} 6577 6578static void 6579Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6580{ 6581 slotbuf[0] = 0xc002; 6582} 6583 6584static void 6585Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6586{ 6587 slotbuf[0] = 0xd002; 6588} 6589 6590static void 6591Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) 6592{ 6593 slotbuf[0] = 0x800000; 6594} 6595 6596static void 6597Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) 6598{ 6599 slotbuf[0] = 0xc00000; 6600} 6601 6602static void 6603Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6604{ 6605 slotbuf[0] = 0x900000; 6606} 6607 6608static void 6609Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6610{ 6611 slotbuf[0] = 0xa00000; 6612} 6613 6614static void 6615Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6616{ 6617 slotbuf[0] = 0xb00000; 6618} 6619 6620static void 6621Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 6622{ 6623 slotbuf[0] = 0xd00000; 6624} 6625 6626static void 6627Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 6628{ 6629 slotbuf[0] = 0xe00000; 6630} 6631 6632static void 6633Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 6634{ 6635 slotbuf[0] = 0xf00000; 6636} 6637 6638static void 6639Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) 6640{ 6641 slotbuf[0] = 0x100000; 6642} 6643 6644static void 6645Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) 6646{ 6647 slotbuf[0] = 0x200000; 6648} 6649 6650static void 6651Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) 6652{ 6653 slotbuf[0] = 0x300000; 6654} 6655 6656static void 6657Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6658{ 6659 slotbuf[0] = 0x26; 6660} 6661 6662static void 6663Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) 6664{ 6665 slotbuf[0] = 0x66; 6666} 6667 6668static void 6669Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) 6670{ 6671 slotbuf[0] = 0xe6; 6672} 6673 6674static void 6675Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) 6676{ 6677 slotbuf[0] = 0xa6; 6678} 6679 6680static void 6681Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) 6682{ 6683 slotbuf[0] = 0x6007; 6684} 6685 6686static void 6687Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6688{ 6689 slotbuf[0] = 0xe007; 6690} 6691 6692static void 6693Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6694{ 6695 slotbuf[0] = 0xf6; 6696} 6697 6698static void 6699Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6700{ 6701 slotbuf[0] = 0xb6; 6702} 6703 6704static void 6705Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) 6706{ 6707 slotbuf[0] = 0x1007; 6708} 6709 6710static void 6711Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) 6712{ 6713 slotbuf[0] = 0x9007; 6714} 6715 6716static void 6717Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) 6718{ 6719 slotbuf[0] = 0xa007; 6720} 6721 6722static void 6723Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) 6724{ 6725 slotbuf[0] = 0x2007; 6726} 6727 6728static void 6729Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) 6730{ 6731 slotbuf[0] = 0xb007; 6732} 6733 6734static void 6735Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) 6736{ 6737 slotbuf[0] = 0x3007; 6738} 6739 6740static void 6741Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) 6742{ 6743 slotbuf[0] = 0x8007; 6744} 6745 6746static void 6747Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) 6748{ 6749 slotbuf[0] = 0x7; 6750} 6751 6752static void 6753Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) 6754{ 6755 slotbuf[0] = 0x4007; 6756} 6757 6758static void 6759Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) 6760{ 6761 slotbuf[0] = 0xc007; 6762} 6763 6764static void 6765Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) 6766{ 6767 slotbuf[0] = 0x5007; 6768} 6769 6770static void 6771Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) 6772{ 6773 slotbuf[0] = 0xd007; 6774} 6775 6776static void 6777Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6778{ 6779 slotbuf[0] = 0x16; 6780} 6781 6782static void 6783Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6784{ 6785 slotbuf[0] = 0x56; 6786} 6787 6788static void 6789Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6790{ 6791 slotbuf[0] = 0xd6; 6792} 6793 6794static void 6795Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6796{ 6797 slotbuf[0] = 0x96; 6798} 6799 6800static void 6801Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6802{ 6803 slotbuf[0] = 0x5; 6804} 6805 6806static void 6807Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) 6808{ 6809 slotbuf[0] = 0xc0; 6810} 6811 6812static void 6813Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6814{ 6815 slotbuf[0] = 0x40000; 6816} 6817 6818static void 6819Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) 6820{ 6821 slotbuf[0] = 0; 6822} 6823 6824static void 6825Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) 6826{ 6827 slotbuf[0] = 0x6; 6828} 6829 6830static void 6831Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) 6832{ 6833 slotbuf[0] = 0xa0; 6834} 6835 6836static void 6837Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6838{ 6839 slotbuf[0] = 0x1002; 6840} 6841 6842static void 6843Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) 6844{ 6845 slotbuf[0] = 0x9002; 6846} 6847 6848static void 6849Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6850{ 6851 slotbuf[0] = 0x2002; 6852} 6853 6854static void 6855Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) 6856{ 6857 slotbuf[0] = 0x1; 6858} 6859 6860static void 6861Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 6862{ 6863 slotbuf[0] = 0x2; 6864} 6865 6866static void 6867Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) 6868{ 6869 slotbuf[0] = 0x8076; 6870} 6871 6872static void 6873Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6874{ 6875 slotbuf[0] = 0x9076; 6876} 6877 6878static void 6879Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6880{ 6881 slotbuf[0] = 0xa076; 6882} 6883 6884static void 6885Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) 6886{ 6887 slotbuf[0] = 0xa002; 6888} 6889 6890static void 6891Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6892{ 6893 slotbuf[0] = 0x830000; 6894} 6895 6896static void 6897Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6898{ 6899 slotbuf[0] = 0x930000; 6900} 6901 6902static void 6903Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 6904{ 6905 slotbuf[0] = 0xa30000; 6906} 6907 6908static void 6909Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 6910{ 6911 slotbuf[0] = 0xb30000; 6912} 6913 6914static void 6915Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) 6916{ 6917 slotbuf[0] = 0x600000; 6918} 6919 6920static void 6921Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) 6922{ 6923 slotbuf[0] = 0x600100; 6924} 6925 6926static void 6927Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) 6928{ 6929 slotbuf[0] = 0x20f0; 6930} 6931 6932static void 6933Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) 6934{ 6935 slotbuf[0] = 0x80; 6936} 6937 6938static void 6939Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) 6940{ 6941 slotbuf[0] = 0x5100; 6942} 6943 6944static void 6945Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6946{ 6947 slotbuf[0] = 0x5002; 6948} 6949 6950static void 6951Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6952{ 6953 slotbuf[0] = 0x6002; 6954} 6955 6956static void 6957Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) 6958{ 6959 slotbuf[0] = 0x590000; 6960} 6961 6962static void 6963Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) 6964{ 6965 slotbuf[0] = 0x4002; 6966} 6967 6968static void 6969Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) 6970{ 6971 slotbuf[0] = 0x400000; 6972} 6973 6974static void 6975Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) 6976{ 6977 slotbuf[0] = 0x401000; 6978} 6979 6980static void 6981Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) 6982{ 6983 slotbuf[0] = 0x402000; 6984} 6985 6986static void 6987Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) 6988{ 6989 slotbuf[0] = 0x403000; 6990} 6991 6992static void 6993Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) 6994{ 6995 slotbuf[0] = 0x404000; 6996} 6997 6998static void 6999Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7000{ 7001 slotbuf[0] = 0xa10000; 7002} 7003 7004static void 7005Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) 7006{ 7007 slotbuf[0] = 0x810000; 7008} 7009 7010static void 7011Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7012{ 7013 slotbuf[0] = 0x910000; 7014} 7015 7016static void 7017Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) 7018{ 7019 slotbuf[0] = 0xb10000; 7020} 7021 7022static void 7023Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) 7024{ 7025 slotbuf[0] = 0x10000; 7026} 7027 7028static void 7029Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) 7030{ 7031 slotbuf[0] = 0x210000; 7032} 7033 7034static void 7035Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) 7036{ 7037 slotbuf[0] = 0x410000; 7038} 7039 7040static void 7041Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) 7042{ 7043 slotbuf[0] = 0x20c0; 7044} 7045 7046static void 7047Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) 7048{ 7049 slotbuf[0] = 0x20d0; 7050} 7051 7052static void 7053Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) 7054{ 7055 slotbuf[0] = 0x2000; 7056} 7057 7058static void 7059Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 7060{ 7061 slotbuf[0] = 0x2010; 7062} 7063 7064static void 7065Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) 7066{ 7067 slotbuf[0] = 0x2020; 7068} 7069 7070static void 7071Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 7072{ 7073 slotbuf[0] = 0x2030; 7074} 7075 7076static void 7077Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) 7078{ 7079 slotbuf[0] = 0x6000; 7080} 7081 7082static void 7083Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 7084{ 7085 slotbuf[0] = 0x30100; 7086} 7087 7088static void 7089Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 7090{ 7091 slotbuf[0] = 0x130100; 7092} 7093 7094static void 7095Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 7096{ 7097 slotbuf[0] = 0x610100; 7098} 7099 7100static void 7101Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 7102{ 7103 slotbuf[0] = 0x30200; 7104} 7105 7106static void 7107Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 7108{ 7109 slotbuf[0] = 0x130200; 7110} 7111 7112static void 7113Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 7114{ 7115 slotbuf[0] = 0x610200; 7116} 7117 7118static void 7119Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 7120{ 7121 slotbuf[0] = 0x30000; 7122} 7123 7124static void 7125Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 7126{ 7127 slotbuf[0] = 0x130000; 7128} 7129 7130static void 7131Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 7132{ 7133 slotbuf[0] = 0x610000; 7134} 7135 7136static void 7137Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 7138{ 7139 slotbuf[0] = 0x30300; 7140} 7141 7142static void 7143Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 7144{ 7145 slotbuf[0] = 0x130300; 7146} 7147 7148static void 7149Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 7150{ 7151 slotbuf[0] = 0x610300; 7152} 7153 7154static void 7155Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7156{ 7157 slotbuf[0] = 0x36100; 7158} 7159 7160static void 7161Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7162{ 7163 slotbuf[0] = 0x136100; 7164} 7165 7166static void 7167Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7168{ 7169 slotbuf[0] = 0x616100; 7170} 7171 7172static void 7173Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7174{ 7175 slotbuf[0] = 0x30500; 7176} 7177 7178static void 7179Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7180{ 7181 slotbuf[0] = 0x130500; 7182} 7183 7184static void 7185Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7186{ 7187 slotbuf[0] = 0x610500; 7188} 7189 7190static void 7191Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7192{ 7193 slotbuf[0] = 0x3b000; 7194} 7195 7196static void 7197Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7198{ 7199 slotbuf[0] = 0x13b000; 7200} 7201 7202static void 7203Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7204{ 7205 slotbuf[0] = 0x3d000; 7206} 7207 7208static void 7209Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 7210{ 7211 slotbuf[0] = 0x3e600; 7212} 7213 7214static void 7215Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 7216{ 7217 slotbuf[0] = 0x13e600; 7218} 7219 7220static void 7221Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 7222{ 7223 slotbuf[0] = 0x61e600; 7224} 7225 7226static void 7227Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7228{ 7229 slotbuf[0] = 0x3b100; 7230} 7231 7232static void 7233Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7234{ 7235 slotbuf[0] = 0x13b100; 7236} 7237 7238static void 7239Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7240{ 7241 slotbuf[0] = 0x61b100; 7242} 7243 7244static void 7245Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7246{ 7247 slotbuf[0] = 0x3d100; 7248} 7249 7250static void 7251Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7252{ 7253 slotbuf[0] = 0x13d100; 7254} 7255 7256static void 7257Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7258{ 7259 slotbuf[0] = 0x61d100; 7260} 7261 7262static void 7263Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7264{ 7265 slotbuf[0] = 0x3b200; 7266} 7267 7268static void 7269Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7270{ 7271 slotbuf[0] = 0x13b200; 7272} 7273 7274static void 7275Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7276{ 7277 slotbuf[0] = 0x61b200; 7278} 7279 7280static void 7281Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7282{ 7283 slotbuf[0] = 0x3d200; 7284} 7285 7286static void 7287Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7288{ 7289 slotbuf[0] = 0x13d200; 7290} 7291 7292static void 7293Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7294{ 7295 slotbuf[0] = 0x61d200; 7296} 7297 7298static void 7299Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7300{ 7301 slotbuf[0] = 0x3b300; 7302} 7303 7304static void 7305Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7306{ 7307 slotbuf[0] = 0x13b300; 7308} 7309 7310static void 7311Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7312{ 7313 slotbuf[0] = 0x61b300; 7314} 7315 7316static void 7317Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7318{ 7319 slotbuf[0] = 0x3d300; 7320} 7321 7322static void 7323Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7324{ 7325 slotbuf[0] = 0x13d300; 7326} 7327 7328static void 7329Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7330{ 7331 slotbuf[0] = 0x61d300; 7332} 7333 7334static void 7335Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7336{ 7337 slotbuf[0] = 0x3b400; 7338} 7339 7340static void 7341Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7342{ 7343 slotbuf[0] = 0x13b400; 7344} 7345 7346static void 7347Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7348{ 7349 slotbuf[0] = 0x61b400; 7350} 7351 7352static void 7353Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7354{ 7355 slotbuf[0] = 0x3d400; 7356} 7357 7358static void 7359Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7360{ 7361 slotbuf[0] = 0x13d400; 7362} 7363 7364static void 7365Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7366{ 7367 slotbuf[0] = 0x61d400; 7368} 7369 7370static void 7371Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7372{ 7373 slotbuf[0] = 0x3b500; 7374} 7375 7376static void 7377Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7378{ 7379 slotbuf[0] = 0x13b500; 7380} 7381 7382static void 7383Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7384{ 7385 slotbuf[0] = 0x61b500; 7386} 7387 7388static void 7389Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7390{ 7391 slotbuf[0] = 0x3d500; 7392} 7393 7394static void 7395Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7396{ 7397 slotbuf[0] = 0x13d500; 7398} 7399 7400static void 7401Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7402{ 7403 slotbuf[0] = 0x61d500; 7404} 7405 7406static void 7407Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7408{ 7409 slotbuf[0] = 0x3b600; 7410} 7411 7412static void 7413Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7414{ 7415 slotbuf[0] = 0x13b600; 7416} 7417 7418static void 7419Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7420{ 7421 slotbuf[0] = 0x61b600; 7422} 7423 7424static void 7425Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7426{ 7427 slotbuf[0] = 0x3d600; 7428} 7429 7430static void 7431Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7432{ 7433 slotbuf[0] = 0x13d600; 7434} 7435 7436static void 7437Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7438{ 7439 slotbuf[0] = 0x61d600; 7440} 7441 7442static void 7443Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7444{ 7445 slotbuf[0] = 0x3b700; 7446} 7447 7448static void 7449Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7450{ 7451 slotbuf[0] = 0x13b700; 7452} 7453 7454static void 7455Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7456{ 7457 slotbuf[0] = 0x61b700; 7458} 7459 7460static void 7461Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7462{ 7463 slotbuf[0] = 0x3d700; 7464} 7465 7466static void 7467Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7468{ 7469 slotbuf[0] = 0x13d700; 7470} 7471 7472static void 7473Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7474{ 7475 slotbuf[0] = 0x61d700; 7476} 7477 7478static void 7479Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7480{ 7481 slotbuf[0] = 0x3c200; 7482} 7483 7484static void 7485Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7486{ 7487 slotbuf[0] = 0x13c200; 7488} 7489 7490static void 7491Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 7492{ 7493 slotbuf[0] = 0x61c200; 7494} 7495 7496static void 7497Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7498{ 7499 slotbuf[0] = 0x3c300; 7500} 7501 7502static void 7503Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7504{ 7505 slotbuf[0] = 0x13c300; 7506} 7507 7508static void 7509Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 7510{ 7511 slotbuf[0] = 0x61c300; 7512} 7513 7514static void 7515Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7516{ 7517 slotbuf[0] = 0x3c400; 7518} 7519 7520static void 7521Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7522{ 7523 slotbuf[0] = 0x13c400; 7524} 7525 7526static void 7527Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 7528{ 7529 slotbuf[0] = 0x61c400; 7530} 7531 7532static void 7533Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7534{ 7535 slotbuf[0] = 0x3c500; 7536} 7537 7538static void 7539Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7540{ 7541 slotbuf[0] = 0x13c500; 7542} 7543 7544static void 7545Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 7546{ 7547 slotbuf[0] = 0x61c500; 7548} 7549 7550static void 7551Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7552{ 7553 slotbuf[0] = 0x3c600; 7554} 7555 7556static void 7557Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7558{ 7559 slotbuf[0] = 0x13c600; 7560} 7561 7562static void 7563Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 7564{ 7565 slotbuf[0] = 0x61c600; 7566} 7567 7568static void 7569Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7570{ 7571 slotbuf[0] = 0x3c700; 7572} 7573 7574static void 7575Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7576{ 7577 slotbuf[0] = 0x13c700; 7578} 7579 7580static void 7581Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 7582{ 7583 slotbuf[0] = 0x61c700; 7584} 7585 7586static void 7587Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 7588{ 7589 slotbuf[0] = 0x3ee00; 7590} 7591 7592static void 7593Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 7594{ 7595 slotbuf[0] = 0x13ee00; 7596} 7597 7598static void 7599Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 7600{ 7601 slotbuf[0] = 0x61ee00; 7602} 7603 7604static void 7605Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7606{ 7607 slotbuf[0] = 0x3c000; 7608} 7609 7610static void 7611Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7612{ 7613 slotbuf[0] = 0x13c000; 7614} 7615 7616static void 7617Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 7618{ 7619 slotbuf[0] = 0x61c000; 7620} 7621 7622static void 7623Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 7624{ 7625 slotbuf[0] = 0x3e800; 7626} 7627 7628static void 7629Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 7630{ 7631 slotbuf[0] = 0x13e800; 7632} 7633 7634static void 7635Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 7636{ 7637 slotbuf[0] = 0x61e800; 7638} 7639 7640static void 7641Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7642{ 7643 slotbuf[0] = 0x3f400; 7644} 7645 7646static void 7647Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7648{ 7649 slotbuf[0] = 0x13f400; 7650} 7651 7652static void 7653Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 7654{ 7655 slotbuf[0] = 0x61f400; 7656} 7657 7658static void 7659Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7660{ 7661 slotbuf[0] = 0x3f500; 7662} 7663 7664static void 7665Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7666{ 7667 slotbuf[0] = 0x13f500; 7668} 7669 7670static void 7671Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 7672{ 7673 slotbuf[0] = 0x61f500; 7674} 7675 7676static void 7677Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) 7678{ 7679 slotbuf[0] = 0x3eb00; 7680} 7681 7682static void 7683Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7684{ 7685 slotbuf[0] = 0x3e700; 7686} 7687 7688static void 7689Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7690{ 7691 slotbuf[0] = 0x13e700; 7692} 7693 7694static void 7695Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 7696{ 7697 slotbuf[0] = 0x61e700; 7698} 7699 7700static void 7701Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) 7702{ 7703 slotbuf[0] = 0xc10000; 7704} 7705 7706static void 7707Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) 7708{ 7709 slotbuf[0] = 0xd10000; 7710} 7711 7712static void 7713Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) 7714{ 7715 slotbuf[0] = 0x820000; 7716} 7717 7718static void 7719Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7720{ 7721 slotbuf[0] = 0x740004; 7722} 7723 7724static void 7725Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7726{ 7727 slotbuf[0] = 0x750004; 7728} 7729 7730static void 7731Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7732{ 7733 slotbuf[0] = 0x760004; 7734} 7735 7736static void 7737Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7738{ 7739 slotbuf[0] = 0x770004; 7740} 7741 7742static void 7743Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7744{ 7745 slotbuf[0] = 0x700004; 7746} 7747 7748static void 7749Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7750{ 7751 slotbuf[0] = 0x710004; 7752} 7753 7754static void 7755Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7756{ 7757 slotbuf[0] = 0x720004; 7758} 7759 7760static void 7761Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7762{ 7763 slotbuf[0] = 0x730004; 7764} 7765 7766static void 7767Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7768{ 7769 slotbuf[0] = 0x340004; 7770} 7771 7772static void 7773Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7774{ 7775 slotbuf[0] = 0x350004; 7776} 7777 7778static void 7779Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7780{ 7781 slotbuf[0] = 0x360004; 7782} 7783 7784static void 7785Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7786{ 7787 slotbuf[0] = 0x370004; 7788} 7789 7790static void 7791Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7792{ 7793 slotbuf[0] = 0x640004; 7794} 7795 7796static void 7797Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7798{ 7799 slotbuf[0] = 0x650004; 7800} 7801 7802static void 7803Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7804{ 7805 slotbuf[0] = 0x660004; 7806} 7807 7808static void 7809Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7810{ 7811 slotbuf[0] = 0x670004; 7812} 7813 7814static void 7815Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7816{ 7817 slotbuf[0] = 0x240004; 7818} 7819 7820static void 7821Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7822{ 7823 slotbuf[0] = 0x250004; 7824} 7825 7826static void 7827Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7828{ 7829 slotbuf[0] = 0x260004; 7830} 7831 7832static void 7833Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7834{ 7835 slotbuf[0] = 0x270004; 7836} 7837 7838static void 7839Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7840{ 7841 slotbuf[0] = 0x780004; 7842} 7843 7844static void 7845Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7846{ 7847 slotbuf[0] = 0x790004; 7848} 7849 7850static void 7851Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7852{ 7853 slotbuf[0] = 0x7a0004; 7854} 7855 7856static void 7857Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7858{ 7859 slotbuf[0] = 0x7b0004; 7860} 7861 7862static void 7863Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7864{ 7865 slotbuf[0] = 0x7c0004; 7866} 7867 7868static void 7869Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7870{ 7871 slotbuf[0] = 0x7d0004; 7872} 7873 7874static void 7875Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7876{ 7877 slotbuf[0] = 0x7e0004; 7878} 7879 7880static void 7881Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7882{ 7883 slotbuf[0] = 0x7f0004; 7884} 7885 7886static void 7887Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7888{ 7889 slotbuf[0] = 0x380004; 7890} 7891 7892static void 7893Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7894{ 7895 slotbuf[0] = 0x390004; 7896} 7897 7898static void 7899Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7900{ 7901 slotbuf[0] = 0x3a0004; 7902} 7903 7904static void 7905Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7906{ 7907 slotbuf[0] = 0x3b0004; 7908} 7909 7910static void 7911Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7912{ 7913 slotbuf[0] = 0x3c0004; 7914} 7915 7916static void 7917Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7918{ 7919 slotbuf[0] = 0x3d0004; 7920} 7921 7922static void 7923Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7924{ 7925 slotbuf[0] = 0x3e0004; 7926} 7927 7928static void 7929Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7930{ 7931 slotbuf[0] = 0x3f0004; 7932} 7933 7934static void 7935Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7936{ 7937 slotbuf[0] = 0x680004; 7938} 7939 7940static void 7941Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7942{ 7943 slotbuf[0] = 0x690004; 7944} 7945 7946static void 7947Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7948{ 7949 slotbuf[0] = 0x6a0004; 7950} 7951 7952static void 7953Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7954{ 7955 slotbuf[0] = 0x6b0004; 7956} 7957 7958static void 7959Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7960{ 7961 slotbuf[0] = 0x6c0004; 7962} 7963 7964static void 7965Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7966{ 7967 slotbuf[0] = 0x6d0004; 7968} 7969 7970static void 7971Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7972{ 7973 slotbuf[0] = 0x6e0004; 7974} 7975 7976static void 7977Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7978{ 7979 slotbuf[0] = 0x6f0004; 7980} 7981 7982static void 7983Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 7984{ 7985 slotbuf[0] = 0x280004; 7986} 7987 7988static void 7989Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 7990{ 7991 slotbuf[0] = 0x290004; 7992} 7993 7994static void 7995Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 7996{ 7997 slotbuf[0] = 0x2a0004; 7998} 7999 8000static void 8001Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 8002{ 8003 slotbuf[0] = 0x2b0004; 8004} 8005 8006static void 8007Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 8008{ 8009 slotbuf[0] = 0x2c0004; 8010} 8011 8012static void 8013Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 8014{ 8015 slotbuf[0] = 0x2d0004; 8016} 8017 8018static void 8019Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 8020{ 8021 slotbuf[0] = 0x2e0004; 8022} 8023 8024static void 8025Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 8026{ 8027 slotbuf[0] = 0x2f0004; 8028} 8029 8030static void 8031Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8032{ 8033 slotbuf[0] = 0x580004; 8034} 8035 8036static void 8037Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8038{ 8039 slotbuf[0] = 0x480004; 8040} 8041 8042static void 8043Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8044{ 8045 slotbuf[0] = 0x590004; 8046} 8047 8048static void 8049Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8050{ 8051 slotbuf[0] = 0x490004; 8052} 8053 8054static void 8055Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8056{ 8057 slotbuf[0] = 0x5a0004; 8058} 8059 8060static void 8061Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8062{ 8063 slotbuf[0] = 0x4a0004; 8064} 8065 8066static void 8067Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8068{ 8069 slotbuf[0] = 0x5b0004; 8070} 8071 8072static void 8073Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8074{ 8075 slotbuf[0] = 0x4b0004; 8076} 8077 8078static void 8079Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8080{ 8081 slotbuf[0] = 0x180004; 8082} 8083 8084static void 8085Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8086{ 8087 slotbuf[0] = 0x80004; 8088} 8089 8090static void 8091Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8092{ 8093 slotbuf[0] = 0x190004; 8094} 8095 8096static void 8097Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8098{ 8099 slotbuf[0] = 0x90004; 8100} 8101 8102static void 8103Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8104{ 8105 slotbuf[0] = 0x1a0004; 8106} 8107 8108static void 8109Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8110{ 8111 slotbuf[0] = 0xa0004; 8112} 8113 8114static void 8115Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8116{ 8117 slotbuf[0] = 0x1b0004; 8118} 8119 8120static void 8121Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8122{ 8123 slotbuf[0] = 0xb0004; 8124} 8125 8126static void 8127Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 8128{ 8129 slotbuf[0] = 0x900004; 8130} 8131 8132static void 8133Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 8134{ 8135 slotbuf[0] = 0x800004; 8136} 8137 8138static void 8139Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8140{ 8141 slotbuf[0] = 0x32000; 8142} 8143 8144static void 8145Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8146{ 8147 slotbuf[0] = 0x132000; 8148} 8149 8150static void 8151Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8152{ 8153 slotbuf[0] = 0x612000; 8154} 8155 8156static void 8157Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8158{ 8159 slotbuf[0] = 0x32100; 8160} 8161 8162static void 8163Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8164{ 8165 slotbuf[0] = 0x132100; 8166} 8167 8168static void 8169Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8170{ 8171 slotbuf[0] = 0x612100; 8172} 8173 8174static void 8175Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8176{ 8177 slotbuf[0] = 0x32200; 8178} 8179 8180static void 8181Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8182{ 8183 slotbuf[0] = 0x132200; 8184} 8185 8186static void 8187Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8188{ 8189 slotbuf[0] = 0x612200; 8190} 8191 8192static void 8193Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 8194{ 8195 slotbuf[0] = 0x32300; 8196} 8197 8198static void 8199Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 8200{ 8201 slotbuf[0] = 0x132300; 8202} 8203 8204static void 8205Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 8206{ 8207 slotbuf[0] = 0x612300; 8208} 8209 8210static void 8211Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8212{ 8213 slotbuf[0] = 0x31000; 8214} 8215 8216static void 8217Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8218{ 8219 slotbuf[0] = 0x131000; 8220} 8221 8222static void 8223Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8224{ 8225 slotbuf[0] = 0x611000; 8226} 8227 8228static void 8229Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8230{ 8231 slotbuf[0] = 0x31100; 8232} 8233 8234static void 8235Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8236{ 8237 slotbuf[0] = 0x131100; 8238} 8239 8240static void 8241Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8242{ 8243 slotbuf[0] = 0x611100; 8244} 8245 8246static void 8247Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8248{ 8249 slotbuf[0] = 0x3010; 8250} 8251 8252static void 8253Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) 8254{ 8255 slotbuf[0] = 0x7000; 8256} 8257 8258static void 8259Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) 8260{ 8261 slotbuf[0] = 0x3e200; 8262} 8263 8264static void 8265Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) 8266{ 8267 slotbuf[0] = 0x13e200; 8268} 8269 8270static void 8271Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) 8272{ 8273 slotbuf[0] = 0x13e300; 8274} 8275 8276static void 8277Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8278{ 8279 slotbuf[0] = 0x3e400; 8280} 8281 8282static void 8283Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8284{ 8285 slotbuf[0] = 0x13e400; 8286} 8287 8288static void 8289Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8290{ 8291 slotbuf[0] = 0x61e400; 8292} 8293 8294static void 8295Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) 8296{ 8297 slotbuf[0] = 0x4000; 8298} 8299 8300static void 8301Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 8302{ 8303 slotbuf[0] = 0xf02d; 8304} 8305 8306static void 8307Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8308{ 8309 slotbuf[0] = 0x39000; 8310} 8311 8312static void 8313Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8314{ 8315 slotbuf[0] = 0x139000; 8316} 8317 8318static void 8319Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8320{ 8321 slotbuf[0] = 0x619000; 8322} 8323 8324static void 8325Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8326{ 8327 slotbuf[0] = 0x3a000; 8328} 8329 8330static void 8331Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8332{ 8333 slotbuf[0] = 0x13a000; 8334} 8335 8336static void 8337Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8338{ 8339 slotbuf[0] = 0x61a000; 8340} 8341 8342static void 8343Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8344{ 8345 slotbuf[0] = 0x39100; 8346} 8347 8348static void 8349Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8350{ 8351 slotbuf[0] = 0x139100; 8352} 8353 8354static void 8355Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8356{ 8357 slotbuf[0] = 0x619100; 8358} 8359 8360static void 8361Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8362{ 8363 slotbuf[0] = 0x3a100; 8364} 8365 8366static void 8367Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8368{ 8369 slotbuf[0] = 0x13a100; 8370} 8371 8372static void 8373Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8374{ 8375 slotbuf[0] = 0x61a100; 8376} 8377 8378static void 8379Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8380{ 8381 slotbuf[0] = 0x38000; 8382} 8383 8384static void 8385Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8386{ 8387 slotbuf[0] = 0x138000; 8388} 8389 8390static void 8391Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8392{ 8393 slotbuf[0] = 0x618000; 8394} 8395 8396static void 8397Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8398{ 8399 slotbuf[0] = 0x38100; 8400} 8401 8402static void 8403Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8404{ 8405 slotbuf[0] = 0x138100; 8406} 8407 8408static void 8409Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8410{ 8411 slotbuf[0] = 0x618100; 8412} 8413 8414static void 8415Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8416{ 8417 slotbuf[0] = 0x36000; 8418} 8419 8420static void 8421Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8422{ 8423 slotbuf[0] = 0x136000; 8424} 8425 8426static void 8427Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 8428{ 8429 slotbuf[0] = 0x616000; 8430} 8431 8432static void 8433Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 8434{ 8435 slotbuf[0] = 0x3e900; 8436} 8437 8438static void 8439Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 8440{ 8441 slotbuf[0] = 0x13e900; 8442} 8443 8444static void 8445Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 8446{ 8447 slotbuf[0] = 0x61e900; 8448} 8449 8450static void 8451Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8452{ 8453 slotbuf[0] = 0x3ec00; 8454} 8455 8456static void 8457Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8458{ 8459 slotbuf[0] = 0x13ec00; 8460} 8461 8462static void 8463Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8464{ 8465 slotbuf[0] = 0x61ec00; 8466} 8467 8468static void 8469Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 8470{ 8471 slotbuf[0] = 0x3ed00; 8472} 8473 8474static void 8475Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 8476{ 8477 slotbuf[0] = 0x13ed00; 8478} 8479 8480static void 8481Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 8482{ 8483 slotbuf[0] = 0x61ed00; 8484} 8485 8486static void 8487Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8488{ 8489 slotbuf[0] = 0x36800; 8490} 8491 8492static void 8493Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8494{ 8495 slotbuf[0] = 0x136800; 8496} 8497 8498static void 8499Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8500{ 8501 slotbuf[0] = 0x616800; 8502} 8503 8504static void 8505Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) 8506{ 8507 slotbuf[0] = 0x70e0; 8508} 8509 8510static void 8511Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) 8512{ 8513 slotbuf[0] = 0x70f0; 8514} 8515 8516static void 8517Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8518{ 8519 slotbuf[0] = 0xf1e000; 8520} 8521 8522static void 8523Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) 8524{ 8525 slotbuf[0] = 0xf1e010; 8526} 8527 8528static void 8529Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) 8530{ 8531 slotbuf[0] = 0x135900; 8532} 8533 8534static void 8535Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8536{ 8537 slotbuf[0] = 0x3ea00; 8538} 8539 8540static void 8541Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8542{ 8543 slotbuf[0] = 0x13ea00; 8544} 8545 8546static void 8547Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 8548{ 8549 slotbuf[0] = 0x61ea00; 8550} 8551 8552static void 8553Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8554{ 8555 slotbuf[0] = 0x3f000; 8556} 8557 8558static void 8559Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8560{ 8561 slotbuf[0] = 0x13f000; 8562} 8563 8564static void 8565Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8566{ 8567 slotbuf[0] = 0x61f000; 8568} 8569 8570static void 8571Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8572{ 8573 slotbuf[0] = 0x3f100; 8574} 8575 8576static void 8577Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8578{ 8579 slotbuf[0] = 0x13f100; 8580} 8581 8582static void 8583Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8584{ 8585 slotbuf[0] = 0x61f100; 8586} 8587 8588static void 8589Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8590{ 8591 slotbuf[0] = 0x3f200; 8592} 8593 8594static void 8595Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8596{ 8597 slotbuf[0] = 0x13f200; 8598} 8599 8600static void 8601Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 8602{ 8603 slotbuf[0] = 0x61f200; 8604} 8605 8606static void 8607Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) 8608{ 8609 slotbuf[0] = 0x70c2; 8610} 8611 8612static void 8613Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8614{ 8615 slotbuf[0] = 0x70e2; 8616} 8617 8618static void 8619Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) 8620{ 8621 slotbuf[0] = 0x70d2; 8622} 8623 8624static void 8625Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8626{ 8627 slotbuf[0] = 0x270d2; 8628} 8629 8630static void 8631Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8632{ 8633 slotbuf[0] = 0x370d2; 8634} 8635 8636static void 8637Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) 8638{ 8639 slotbuf[0] = 0x70f2; 8640} 8641 8642static void 8643Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) 8644{ 8645 slotbuf[0] = 0xf10000; 8646} 8647 8648static void 8649Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) 8650{ 8651 slotbuf[0] = 0xf12000; 8652} 8653 8654static void 8655Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) 8656{ 8657 slotbuf[0] = 0xf11000; 8658} 8659 8660static void 8661Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) 8662{ 8663 slotbuf[0] = 0xf13000; 8664} 8665 8666static void 8667Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8668{ 8669 slotbuf[0] = 0x7042; 8670} 8671 8672static void 8673Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8674{ 8675 slotbuf[0] = 0x7052; 8676} 8677 8678static void 8679Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) 8680{ 8681 slotbuf[0] = 0xf7082; 8682} 8683 8684static void 8685Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8686{ 8687 slotbuf[0] = 0x47082; 8688} 8689 8690static void 8691Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8692{ 8693 slotbuf[0] = 0x57082; 8694} 8695 8696static void 8697Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) 8698{ 8699 slotbuf[0] = 0x7062; 8700} 8701 8702static void 8703Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) 8704{ 8705 slotbuf[0] = 0x7072; 8706} 8707 8708static void 8709Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) 8710{ 8711 slotbuf[0] = 0x7002; 8712} 8713 8714static void 8715Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) 8716{ 8717 slotbuf[0] = 0x7012; 8718} 8719 8720static void 8721Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) 8722{ 8723 slotbuf[0] = 0x7022; 8724} 8725 8726static void 8727Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 8728{ 8729 slotbuf[0] = 0x7032; 8730} 8731 8732static void 8733Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) 8734{ 8735 slotbuf[0] = 0x7082; 8736} 8737 8738static void 8739Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8740{ 8741 slotbuf[0] = 0x27082; 8742} 8743 8744static void 8745Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8746{ 8747 slotbuf[0] = 0x37082; 8748} 8749 8750static void 8751Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) 8752{ 8753 slotbuf[0] = 0xf19000; 8754} 8755 8756static void 8757Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) 8758{ 8759 slotbuf[0] = 0xf18000; 8760} 8761 8762static void 8763Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8764{ 8765 slotbuf[0] = 0x50c000; 8766} 8767 8768static void 8769Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8770{ 8771 slotbuf[0] = 0x50d000; 8772} 8773 8774static void 8775Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8776{ 8777 slotbuf[0] = 0x50b000; 8778} 8779 8780static void 8781Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8782{ 8783 slotbuf[0] = 0x50f000; 8784} 8785 8786static void 8787Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8788{ 8789 slotbuf[0] = 0x50e000; 8790} 8791 8792static void 8793Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8794{ 8795 slotbuf[0] = 0x504000; 8796} 8797 8798static void 8799Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8800{ 8801 slotbuf[0] = 0x505000; 8802} 8803 8804static void 8805Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 8806{ 8807 slotbuf[0] = 0x503000; 8808} 8809 8810static void 8811Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8812{ 8813 slotbuf[0] = 0x507000; 8814} 8815 8816static void 8817Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 8818{ 8819 slotbuf[0] = 0x506000; 8820} 8821 8822static void 8823Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) 8824{ 8825 slotbuf[0] = 0x330000; 8826} 8827 8828static void 8829Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) 8830{ 8831 slotbuf[0] = 0x430000; 8832} 8833 8834static void 8835Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) 8836{ 8837 slotbuf[0] = 0x530000; 8838} 8839 8840static void 8841Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8842{ 8843 slotbuf[0] = 0x630000; 8844} 8845 8846static void 8847Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8848{ 8849 slotbuf[0] = 0x730000; 8850} 8851 8852static void 8853Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) 8854{ 8855 slotbuf[0] = 0x40e000; 8856} 8857 8858static void 8859Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) 8860{ 8861 slotbuf[0] = 0x40f000; 8862} 8863 8864static void 8865Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) 8866{ 8867 slotbuf[0] = 0x230000; 8868} 8869 8870static void 8871Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) 8872{ 8873 slotbuf[0] = 0xb002; 8874} 8875 8876static void 8877Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) 8878{ 8879 slotbuf[0] = 0xf002; 8880} 8881 8882static void 8883Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) 8884{ 8885 slotbuf[0] = 0xe002; 8886} 8887 8888static void 8889Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8890{ 8891 slotbuf[0] = 0x30c00; 8892} 8893 8894static void 8895Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8896{ 8897 slotbuf[0] = 0x130c00; 8898} 8899 8900static void 8901Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 8902{ 8903 slotbuf[0] = 0x610c00; 8904} 8905 8906static void 8907Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 8908{ 8909 slotbuf[0] = 0x36300; 8910} 8911 8912static void 8913Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 8914{ 8915 slotbuf[0] = 0x136300; 8916} 8917 8918static void 8919Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 8920{ 8921 slotbuf[0] = 0x616300; 8922} 8923 8924static void 8925Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) 8926{ 8927 slotbuf[0] = 0xc20000; 8928} 8929 8930static void 8931Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) 8932{ 8933 slotbuf[0] = 0xd20000; 8934} 8935 8936static void 8937Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) 8938{ 8939 slotbuf[0] = 0xe20000; 8940} 8941 8942static void 8943Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) 8944{ 8945 slotbuf[0] = 0xf20000; 8946} 8947 8948static void 8949Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) 8950{ 8951 slotbuf[0] = 0x406000; 8952} 8953 8954static void 8955Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) 8956{ 8957 slotbuf[0] = 0x407000; 8958} 8959 8960static void 8961Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8962{ 8963 slotbuf[0] = 0xe30e60; 8964} 8965 8966static void 8967Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8968{ 8969 slotbuf[0] = 0xf3e600; 8970} 8971 8972static void 8973Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) 8974{ 8975 slotbuf[0] = 0xe0000; 8976} 8977 8978static void 8979Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8980{ 8981 slotbuf[0] = 0xe1000; 8982} 8983 8984static void 8985Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8986{ 8987 slotbuf[0] = 0xe1200; 8988} 8989 8990static void 8991Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 8992{ 8993 slotbuf[0] = 0xe2000; 8994} 8995 8996static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { 8997 Opcode_excw_Slot_inst_encode, 0, 0 8998}; 8999 9000static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { 9001 Opcode_rfe_Slot_inst_encode, 0, 0 9002}; 9003 9004static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { 9005 Opcode_rfde_Slot_inst_encode, 0, 0 9006}; 9007 9008static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { 9009 Opcode_syscall_Slot_inst_encode, 0, 0 9010}; 9011 9012static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { 9013 Opcode_call12_Slot_inst_encode, 0, 0 9014}; 9015 9016static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { 9017 Opcode_call8_Slot_inst_encode, 0, 0 9018}; 9019 9020static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { 9021 Opcode_call4_Slot_inst_encode, 0, 0 9022}; 9023 9024static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { 9025 Opcode_callx12_Slot_inst_encode, 0, 0 9026}; 9027 9028static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { 9029 Opcode_callx8_Slot_inst_encode, 0, 0 9030}; 9031 9032static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { 9033 Opcode_callx4_Slot_inst_encode, 0, 0 9034}; 9035 9036static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { 9037 Opcode_entry_Slot_inst_encode, 0, 0 9038}; 9039 9040static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { 9041 Opcode_movsp_Slot_inst_encode, 0, 0 9042}; 9043 9044static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { 9045 Opcode_rotw_Slot_inst_encode, 0, 0 9046}; 9047 9048static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { 9049 Opcode_retw_Slot_inst_encode, 0, 0 9050}; 9051 9052static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { 9053 0, 0, Opcode_retw_n_Slot_inst16b_encode 9054}; 9055 9056static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { 9057 Opcode_rfwo_Slot_inst_encode, 0, 0 9058}; 9059 9060static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { 9061 Opcode_rfwu_Slot_inst_encode, 0, 0 9062}; 9063 9064static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { 9065 Opcode_l32e_Slot_inst_encode, 0, 0 9066}; 9067 9068static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { 9069 Opcode_s32e_Slot_inst_encode, 0, 0 9070}; 9071 9072static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { 9073 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0 9074}; 9075 9076static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { 9077 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0 9078}; 9079 9080static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { 9081 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0 9082}; 9083 9084static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { 9085 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0 9086}; 9087 9088static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { 9089 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0 9090}; 9091 9092static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { 9093 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0 9094}; 9095 9096static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { 9097 0, Opcode_add_n_Slot_inst16a_encode, 0 9098}; 9099 9100static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { 9101 0, Opcode_addi_n_Slot_inst16a_encode, 0 9102}; 9103 9104static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { 9105 0, 0, Opcode_beqz_n_Slot_inst16b_encode 9106}; 9107 9108static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { 9109 0, 0, Opcode_bnez_n_Slot_inst16b_encode 9110}; 9111 9112static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { 9113 0, 0, Opcode_ill_n_Slot_inst16b_encode 9114}; 9115 9116static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { 9117 0, Opcode_l32i_n_Slot_inst16a_encode, 0 9118}; 9119 9120static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { 9121 0, 0, Opcode_mov_n_Slot_inst16b_encode 9122}; 9123 9124static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { 9125 0, 0, Opcode_movi_n_Slot_inst16b_encode 9126}; 9127 9128static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { 9129 0, 0, Opcode_nop_n_Slot_inst16b_encode 9130}; 9131 9132static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { 9133 0, 0, Opcode_ret_n_Slot_inst16b_encode 9134}; 9135 9136static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { 9137 0, Opcode_s32i_n_Slot_inst16a_encode, 0 9138}; 9139 9140static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { 9141 Opcode_addi_Slot_inst_encode, 0, 0 9142}; 9143 9144static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { 9145 Opcode_addmi_Slot_inst_encode, 0, 0 9146}; 9147 9148static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { 9149 Opcode_add_Slot_inst_encode, 0, 0 9150}; 9151 9152static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { 9153 Opcode_sub_Slot_inst_encode, 0, 0 9154}; 9155 9156static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { 9157 Opcode_addx2_Slot_inst_encode, 0, 0 9158}; 9159 9160static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { 9161 Opcode_addx4_Slot_inst_encode, 0, 0 9162}; 9163 9164static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { 9165 Opcode_addx8_Slot_inst_encode, 0, 0 9166}; 9167 9168static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { 9169 Opcode_subx2_Slot_inst_encode, 0, 0 9170}; 9171 9172static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { 9173 Opcode_subx4_Slot_inst_encode, 0, 0 9174}; 9175 9176static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { 9177 Opcode_subx8_Slot_inst_encode, 0, 0 9178}; 9179 9180static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { 9181 Opcode_and_Slot_inst_encode, 0, 0 9182}; 9183 9184static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { 9185 Opcode_or_Slot_inst_encode, 0, 0 9186}; 9187 9188static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { 9189 Opcode_xor_Slot_inst_encode, 0, 0 9190}; 9191 9192static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { 9193 Opcode_beqi_Slot_inst_encode, 0, 0 9194}; 9195 9196static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { 9197 Opcode_bnei_Slot_inst_encode, 0, 0 9198}; 9199 9200static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { 9201 Opcode_bgei_Slot_inst_encode, 0, 0 9202}; 9203 9204static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { 9205 Opcode_blti_Slot_inst_encode, 0, 0 9206}; 9207 9208static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { 9209 Opcode_bbci_Slot_inst_encode, 0, 0 9210}; 9211 9212static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { 9213 Opcode_bbsi_Slot_inst_encode, 0, 0 9214}; 9215 9216static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { 9217 Opcode_bgeui_Slot_inst_encode, 0, 0 9218}; 9219 9220static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { 9221 Opcode_bltui_Slot_inst_encode, 0, 0 9222}; 9223 9224static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { 9225 Opcode_beq_Slot_inst_encode, 0, 0 9226}; 9227 9228static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { 9229 Opcode_bne_Slot_inst_encode, 0, 0 9230}; 9231 9232static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { 9233 Opcode_bge_Slot_inst_encode, 0, 0 9234}; 9235 9236static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { 9237 Opcode_blt_Slot_inst_encode, 0, 0 9238}; 9239 9240static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { 9241 Opcode_bgeu_Slot_inst_encode, 0, 0 9242}; 9243 9244static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { 9245 Opcode_bltu_Slot_inst_encode, 0, 0 9246}; 9247 9248static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { 9249 Opcode_bany_Slot_inst_encode, 0, 0 9250}; 9251 9252static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { 9253 Opcode_bnone_Slot_inst_encode, 0, 0 9254}; 9255 9256static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { 9257 Opcode_ball_Slot_inst_encode, 0, 0 9258}; 9259 9260static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { 9261 Opcode_bnall_Slot_inst_encode, 0, 0 9262}; 9263 9264static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { 9265 Opcode_bbc_Slot_inst_encode, 0, 0 9266}; 9267 9268static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { 9269 Opcode_bbs_Slot_inst_encode, 0, 0 9270}; 9271 9272static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { 9273 Opcode_beqz_Slot_inst_encode, 0, 0 9274}; 9275 9276static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { 9277 Opcode_bnez_Slot_inst_encode, 0, 0 9278}; 9279 9280static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { 9281 Opcode_bgez_Slot_inst_encode, 0, 0 9282}; 9283 9284static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { 9285 Opcode_bltz_Slot_inst_encode, 0, 0 9286}; 9287 9288static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { 9289 Opcode_call0_Slot_inst_encode, 0, 0 9290}; 9291 9292static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { 9293 Opcode_callx0_Slot_inst_encode, 0, 0 9294}; 9295 9296static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { 9297 Opcode_extui_Slot_inst_encode, 0, 0 9298}; 9299 9300static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { 9301 Opcode_ill_Slot_inst_encode, 0, 0 9302}; 9303 9304static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { 9305 Opcode_j_Slot_inst_encode, 0, 0 9306}; 9307 9308static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { 9309 Opcode_jx_Slot_inst_encode, 0, 0 9310}; 9311 9312static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { 9313 Opcode_l16ui_Slot_inst_encode, 0, 0 9314}; 9315 9316static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { 9317 Opcode_l16si_Slot_inst_encode, 0, 0 9318}; 9319 9320static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { 9321 Opcode_l32i_Slot_inst_encode, 0, 0 9322}; 9323 9324static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { 9325 Opcode_l32r_Slot_inst_encode, 0, 0 9326}; 9327 9328static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { 9329 Opcode_l8ui_Slot_inst_encode, 0, 0 9330}; 9331 9332static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { 9333 Opcode_loop_Slot_inst_encode, 0, 0 9334}; 9335 9336static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { 9337 Opcode_loopnez_Slot_inst_encode, 0, 0 9338}; 9339 9340static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { 9341 Opcode_loopgtz_Slot_inst_encode, 0, 0 9342}; 9343 9344static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { 9345 Opcode_movi_Slot_inst_encode, 0, 0 9346}; 9347 9348static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { 9349 Opcode_moveqz_Slot_inst_encode, 0, 0 9350}; 9351 9352static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { 9353 Opcode_movnez_Slot_inst_encode, 0, 0 9354}; 9355 9356static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { 9357 Opcode_movltz_Slot_inst_encode, 0, 0 9358}; 9359 9360static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { 9361 Opcode_movgez_Slot_inst_encode, 0, 0 9362}; 9363 9364static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { 9365 Opcode_neg_Slot_inst_encode, 0, 0 9366}; 9367 9368static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { 9369 Opcode_abs_Slot_inst_encode, 0, 0 9370}; 9371 9372static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { 9373 Opcode_nop_Slot_inst_encode, 0, 0 9374}; 9375 9376static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { 9377 Opcode_ret_Slot_inst_encode, 0, 0 9378}; 9379 9380static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { 9381 Opcode_simcall_Slot_inst_encode, 0, 0 9382}; 9383 9384static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { 9385 Opcode_s16i_Slot_inst_encode, 0, 0 9386}; 9387 9388static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { 9389 Opcode_s32i_Slot_inst_encode, 0, 0 9390}; 9391 9392static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { 9393 Opcode_s32nb_Slot_inst_encode, 0, 0 9394}; 9395 9396static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { 9397 Opcode_s8i_Slot_inst_encode, 0, 0 9398}; 9399 9400static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { 9401 Opcode_ssr_Slot_inst_encode, 0, 0 9402}; 9403 9404static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { 9405 Opcode_ssl_Slot_inst_encode, 0, 0 9406}; 9407 9408static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { 9409 Opcode_ssa8l_Slot_inst_encode, 0, 0 9410}; 9411 9412static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { 9413 Opcode_ssa8b_Slot_inst_encode, 0, 0 9414}; 9415 9416static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { 9417 Opcode_ssai_Slot_inst_encode, 0, 0 9418}; 9419 9420static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { 9421 Opcode_sll_Slot_inst_encode, 0, 0 9422}; 9423 9424static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { 9425 Opcode_src_Slot_inst_encode, 0, 0 9426}; 9427 9428static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { 9429 Opcode_srl_Slot_inst_encode, 0, 0 9430}; 9431 9432static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { 9433 Opcode_sra_Slot_inst_encode, 0, 0 9434}; 9435 9436static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { 9437 Opcode_slli_Slot_inst_encode, 0, 0 9438}; 9439 9440static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { 9441 Opcode_srai_Slot_inst_encode, 0, 0 9442}; 9443 9444static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { 9445 Opcode_srli_Slot_inst_encode, 0, 0 9446}; 9447 9448static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { 9449 Opcode_memw_Slot_inst_encode, 0, 0 9450}; 9451 9452static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { 9453 Opcode_extw_Slot_inst_encode, 0, 0 9454}; 9455 9456static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { 9457 Opcode_isync_Slot_inst_encode, 0, 0 9458}; 9459 9460static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { 9461 Opcode_rsync_Slot_inst_encode, 0, 0 9462}; 9463 9464static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { 9465 Opcode_esync_Slot_inst_encode, 0, 0 9466}; 9467 9468static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { 9469 Opcode_dsync_Slot_inst_encode, 0, 0 9470}; 9471 9472static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { 9473 Opcode_rsil_Slot_inst_encode, 0, 0 9474}; 9475 9476static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { 9477 Opcode_rsr_lend_Slot_inst_encode, 0, 0 9478}; 9479 9480static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { 9481 Opcode_wsr_lend_Slot_inst_encode, 0, 0 9482}; 9483 9484static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { 9485 Opcode_xsr_lend_Slot_inst_encode, 0, 0 9486}; 9487 9488static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { 9489 Opcode_rsr_lcount_Slot_inst_encode, 0, 0 9490}; 9491 9492static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { 9493 Opcode_wsr_lcount_Slot_inst_encode, 0, 0 9494}; 9495 9496static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { 9497 Opcode_xsr_lcount_Slot_inst_encode, 0, 0 9498}; 9499 9500static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { 9501 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0 9502}; 9503 9504static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { 9505 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0 9506}; 9507 9508static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { 9509 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0 9510}; 9511 9512static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { 9513 Opcode_rsr_sar_Slot_inst_encode, 0, 0 9514}; 9515 9516static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { 9517 Opcode_wsr_sar_Slot_inst_encode, 0, 0 9518}; 9519 9520static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { 9521 Opcode_xsr_sar_Slot_inst_encode, 0, 0 9522}; 9523 9524static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { 9525 Opcode_rsr_memctl_Slot_inst_encode, 0, 0 9526}; 9527 9528static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { 9529 Opcode_wsr_memctl_Slot_inst_encode, 0, 0 9530}; 9531 9532static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { 9533 Opcode_xsr_memctl_Slot_inst_encode, 0, 0 9534}; 9535 9536static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { 9537 Opcode_rsr_litbase_Slot_inst_encode, 0, 0 9538}; 9539 9540static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { 9541 Opcode_wsr_litbase_Slot_inst_encode, 0, 0 9542}; 9543 9544static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { 9545 Opcode_xsr_litbase_Slot_inst_encode, 0, 0 9546}; 9547 9548static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { 9549 Opcode_rsr_configid0_Slot_inst_encode, 0, 0 9550}; 9551 9552static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { 9553 Opcode_wsr_configid0_Slot_inst_encode, 0, 0 9554}; 9555 9556static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { 9557 Opcode_rsr_configid1_Slot_inst_encode, 0, 0 9558}; 9559 9560static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { 9561 Opcode_rsr_ps_Slot_inst_encode, 0, 0 9562}; 9563 9564static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { 9565 Opcode_wsr_ps_Slot_inst_encode, 0, 0 9566}; 9567 9568static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { 9569 Opcode_xsr_ps_Slot_inst_encode, 0, 0 9570}; 9571 9572static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { 9573 Opcode_rsr_epc1_Slot_inst_encode, 0, 0 9574}; 9575 9576static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { 9577 Opcode_wsr_epc1_Slot_inst_encode, 0, 0 9578}; 9579 9580static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { 9581 Opcode_xsr_epc1_Slot_inst_encode, 0, 0 9582}; 9583 9584static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { 9585 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0 9586}; 9587 9588static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { 9589 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0 9590}; 9591 9592static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { 9593 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0 9594}; 9595 9596static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { 9597 Opcode_rsr_epc2_Slot_inst_encode, 0, 0 9598}; 9599 9600static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { 9601 Opcode_wsr_epc2_Slot_inst_encode, 0, 0 9602}; 9603 9604static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { 9605 Opcode_xsr_epc2_Slot_inst_encode, 0, 0 9606}; 9607 9608static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { 9609 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0 9610}; 9611 9612static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { 9613 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0 9614}; 9615 9616static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { 9617 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0 9618}; 9619 9620static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { 9621 Opcode_rsr_epc3_Slot_inst_encode, 0, 0 9622}; 9623 9624static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { 9625 Opcode_wsr_epc3_Slot_inst_encode, 0, 0 9626}; 9627 9628static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { 9629 Opcode_xsr_epc3_Slot_inst_encode, 0, 0 9630}; 9631 9632static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { 9633 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0 9634}; 9635 9636static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { 9637 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0 9638}; 9639 9640static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { 9641 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0 9642}; 9643 9644static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { 9645 Opcode_rsr_epc4_Slot_inst_encode, 0, 0 9646}; 9647 9648static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { 9649 Opcode_wsr_epc4_Slot_inst_encode, 0, 0 9650}; 9651 9652static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { 9653 Opcode_xsr_epc4_Slot_inst_encode, 0, 0 9654}; 9655 9656static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { 9657 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0 9658}; 9659 9660static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { 9661 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0 9662}; 9663 9664static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { 9665 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0 9666}; 9667 9668static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { 9669 Opcode_rsr_epc5_Slot_inst_encode, 0, 0 9670}; 9671 9672static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { 9673 Opcode_wsr_epc5_Slot_inst_encode, 0, 0 9674}; 9675 9676static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { 9677 Opcode_xsr_epc5_Slot_inst_encode, 0, 0 9678}; 9679 9680static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { 9681 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0 9682}; 9683 9684static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { 9685 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0 9686}; 9687 9688static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { 9689 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0 9690}; 9691 9692static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { 9693 Opcode_rsr_epc6_Slot_inst_encode, 0, 0 9694}; 9695 9696static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { 9697 Opcode_wsr_epc6_Slot_inst_encode, 0, 0 9698}; 9699 9700static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { 9701 Opcode_xsr_epc6_Slot_inst_encode, 0, 0 9702}; 9703 9704static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { 9705 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0 9706}; 9707 9708static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { 9709 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0 9710}; 9711 9712static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { 9713 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0 9714}; 9715 9716static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { 9717 Opcode_rsr_epc7_Slot_inst_encode, 0, 0 9718}; 9719 9720static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { 9721 Opcode_wsr_epc7_Slot_inst_encode, 0, 0 9722}; 9723 9724static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { 9725 Opcode_xsr_epc7_Slot_inst_encode, 0, 0 9726}; 9727 9728static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { 9729 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0 9730}; 9731 9732static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { 9733 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0 9734}; 9735 9736static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { 9737 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0 9738}; 9739 9740static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { 9741 Opcode_rsr_eps2_Slot_inst_encode, 0, 0 9742}; 9743 9744static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { 9745 Opcode_wsr_eps2_Slot_inst_encode, 0, 0 9746}; 9747 9748static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { 9749 Opcode_xsr_eps2_Slot_inst_encode, 0, 0 9750}; 9751 9752static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { 9753 Opcode_rsr_eps3_Slot_inst_encode, 0, 0 9754}; 9755 9756static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { 9757 Opcode_wsr_eps3_Slot_inst_encode, 0, 0 9758}; 9759 9760static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { 9761 Opcode_xsr_eps3_Slot_inst_encode, 0, 0 9762}; 9763 9764static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { 9765 Opcode_rsr_eps4_Slot_inst_encode, 0, 0 9766}; 9767 9768static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { 9769 Opcode_wsr_eps4_Slot_inst_encode, 0, 0 9770}; 9771 9772static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { 9773 Opcode_xsr_eps4_Slot_inst_encode, 0, 0 9774}; 9775 9776static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { 9777 Opcode_rsr_eps5_Slot_inst_encode, 0, 0 9778}; 9779 9780static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { 9781 Opcode_wsr_eps5_Slot_inst_encode, 0, 0 9782}; 9783 9784static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { 9785 Opcode_xsr_eps5_Slot_inst_encode, 0, 0 9786}; 9787 9788static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { 9789 Opcode_rsr_eps6_Slot_inst_encode, 0, 0 9790}; 9791 9792static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { 9793 Opcode_wsr_eps6_Slot_inst_encode, 0, 0 9794}; 9795 9796static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { 9797 Opcode_xsr_eps6_Slot_inst_encode, 0, 0 9798}; 9799 9800static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { 9801 Opcode_rsr_eps7_Slot_inst_encode, 0, 0 9802}; 9803 9804static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { 9805 Opcode_wsr_eps7_Slot_inst_encode, 0, 0 9806}; 9807 9808static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { 9809 Opcode_xsr_eps7_Slot_inst_encode, 0, 0 9810}; 9811 9812static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { 9813 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0 9814}; 9815 9816static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { 9817 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0 9818}; 9819 9820static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { 9821 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0 9822}; 9823 9824static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { 9825 Opcode_rsr_depc_Slot_inst_encode, 0, 0 9826}; 9827 9828static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { 9829 Opcode_wsr_depc_Slot_inst_encode, 0, 0 9830}; 9831 9832static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { 9833 Opcode_xsr_depc_Slot_inst_encode, 0, 0 9834}; 9835 9836static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { 9837 Opcode_rsr_exccause_Slot_inst_encode, 0, 0 9838}; 9839 9840static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { 9841 Opcode_wsr_exccause_Slot_inst_encode, 0, 0 9842}; 9843 9844static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { 9845 Opcode_xsr_exccause_Slot_inst_encode, 0, 0 9846}; 9847 9848static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { 9849 Opcode_rsr_misc0_Slot_inst_encode, 0, 0 9850}; 9851 9852static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { 9853 Opcode_wsr_misc0_Slot_inst_encode, 0, 0 9854}; 9855 9856static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { 9857 Opcode_xsr_misc0_Slot_inst_encode, 0, 0 9858}; 9859 9860static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { 9861 Opcode_rsr_misc1_Slot_inst_encode, 0, 0 9862}; 9863 9864static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { 9865 Opcode_wsr_misc1_Slot_inst_encode, 0, 0 9866}; 9867 9868static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { 9869 Opcode_xsr_misc1_Slot_inst_encode, 0, 0 9870}; 9871 9872static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { 9873 Opcode_rsr_prid_Slot_inst_encode, 0, 0 9874}; 9875 9876static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { 9877 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0 9878}; 9879 9880static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { 9881 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0 9882}; 9883 9884static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { 9885 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0 9886}; 9887 9888static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { 9889 Opcode_mul16u_Slot_inst_encode, 0, 0 9890}; 9891 9892static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { 9893 Opcode_mul16s_Slot_inst_encode, 0, 0 9894}; 9895 9896static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { 9897 Opcode_mull_Slot_inst_encode, 0, 0 9898}; 9899 9900static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { 9901 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0 9902}; 9903 9904static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { 9905 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0 9906}; 9907 9908static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { 9909 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0 9910}; 9911 9912static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { 9913 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0 9914}; 9915 9916static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { 9917 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0 9918}; 9919 9920static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { 9921 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0 9922}; 9923 9924static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { 9925 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0 9926}; 9927 9928static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { 9929 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0 9930}; 9931 9932static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { 9933 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0 9934}; 9935 9936static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { 9937 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0 9938}; 9939 9940static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { 9941 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0 9942}; 9943 9944static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { 9945 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0 9946}; 9947 9948static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { 9949 Opcode_mul_da_ll_Slot_inst_encode, 0, 0 9950}; 9951 9952static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { 9953 Opcode_mul_da_hl_Slot_inst_encode, 0, 0 9954}; 9955 9956static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { 9957 Opcode_mul_da_lh_Slot_inst_encode, 0, 0 9958}; 9959 9960static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { 9961 Opcode_mul_da_hh_Slot_inst_encode, 0, 0 9962}; 9963 9964static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { 9965 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0 9966}; 9967 9968static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { 9969 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0 9970}; 9971 9972static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { 9973 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0 9974}; 9975 9976static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { 9977 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0 9978}; 9979 9980static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { 9981 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0 9982}; 9983 9984static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { 9985 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0 9986}; 9987 9988static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { 9989 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0 9990}; 9991 9992static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { 9993 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0 9994}; 9995 9996static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { 9997 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0 9998}; 9999 10000static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { 10001 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0 10002}; 10003 10004static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { 10005 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0 10006}; 10007 10008static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { 10009 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0 10010}; 10011 10012static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { 10013 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0 10014}; 10015 10016static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { 10017 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0 10018}; 10019 10020static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { 10021 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0 10022}; 10023 10024static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { 10025 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0 10026}; 10027 10028static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { 10029 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0 10030}; 10031 10032static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { 10033 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0 10034}; 10035 10036static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { 10037 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0 10038}; 10039 10040static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { 10041 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0 10042}; 10043 10044static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { 10045 Opcode_mula_da_ll_Slot_inst_encode, 0, 0 10046}; 10047 10048static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { 10049 Opcode_mula_da_hl_Slot_inst_encode, 0, 0 10050}; 10051 10052static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { 10053 Opcode_mula_da_lh_Slot_inst_encode, 0, 0 10054}; 10055 10056static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { 10057 Opcode_mula_da_hh_Slot_inst_encode, 0, 0 10058}; 10059 10060static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { 10061 Opcode_muls_da_ll_Slot_inst_encode, 0, 0 10062}; 10063 10064static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { 10065 Opcode_muls_da_hl_Slot_inst_encode, 0, 0 10066}; 10067 10068static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { 10069 Opcode_muls_da_lh_Slot_inst_encode, 0, 0 10070}; 10071 10072static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { 10073 Opcode_muls_da_hh_Slot_inst_encode, 0, 0 10074}; 10075 10076static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { 10077 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0 10078}; 10079 10080static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { 10081 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0 10082}; 10083 10084static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { 10085 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0 10086}; 10087 10088static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { 10089 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0 10090}; 10091 10092static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { 10093 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0 10094}; 10095 10096static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { 10097 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0 10098}; 10099 10100static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { 10101 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0 10102}; 10103 10104static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { 10105 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0 10106}; 10107 10108static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { 10109 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0 10110}; 10111 10112static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { 10113 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0 10114}; 10115 10116static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { 10117 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0 10118}; 10119 10120static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { 10121 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0 10122}; 10123 10124static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { 10125 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0 10126}; 10127 10128static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { 10129 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0 10130}; 10131 10132static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { 10133 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0 10134}; 10135 10136static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { 10137 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0 10138}; 10139 10140static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { 10141 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0 10142}; 10143 10144static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { 10145 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0 10146}; 10147 10148static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { 10149 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0 10150}; 10151 10152static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { 10153 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0 10154}; 10155 10156static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { 10157 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0 10158}; 10159 10160static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { 10161 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0 10162}; 10163 10164static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { 10165 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0 10166}; 10167 10168static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { 10169 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0 10170}; 10171 10172static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { 10173 Opcode_lddec_Slot_inst_encode, 0, 0 10174}; 10175 10176static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { 10177 Opcode_ldinc_Slot_inst_encode, 0, 0 10178}; 10179 10180static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { 10181 Opcode_rsr_m0_Slot_inst_encode, 0, 0 10182}; 10183 10184static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { 10185 Opcode_wsr_m0_Slot_inst_encode, 0, 0 10186}; 10187 10188static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { 10189 Opcode_xsr_m0_Slot_inst_encode, 0, 0 10190}; 10191 10192static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { 10193 Opcode_rsr_m1_Slot_inst_encode, 0, 0 10194}; 10195 10196static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { 10197 Opcode_wsr_m1_Slot_inst_encode, 0, 0 10198}; 10199 10200static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { 10201 Opcode_xsr_m1_Slot_inst_encode, 0, 0 10202}; 10203 10204static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { 10205 Opcode_rsr_m2_Slot_inst_encode, 0, 0 10206}; 10207 10208static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { 10209 Opcode_wsr_m2_Slot_inst_encode, 0, 0 10210}; 10211 10212static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { 10213 Opcode_xsr_m2_Slot_inst_encode, 0, 0 10214}; 10215 10216static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { 10217 Opcode_rsr_m3_Slot_inst_encode, 0, 0 10218}; 10219 10220static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { 10221 Opcode_wsr_m3_Slot_inst_encode, 0, 0 10222}; 10223 10224static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { 10225 Opcode_xsr_m3_Slot_inst_encode, 0, 0 10226}; 10227 10228static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { 10229 Opcode_rsr_acclo_Slot_inst_encode, 0, 0 10230}; 10231 10232static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { 10233 Opcode_wsr_acclo_Slot_inst_encode, 0, 0 10234}; 10235 10236static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { 10237 Opcode_xsr_acclo_Slot_inst_encode, 0, 0 10238}; 10239 10240static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { 10241 Opcode_rsr_acchi_Slot_inst_encode, 0, 0 10242}; 10243 10244static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { 10245 Opcode_wsr_acchi_Slot_inst_encode, 0, 0 10246}; 10247 10248static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { 10249 Opcode_xsr_acchi_Slot_inst_encode, 0, 0 10250}; 10251 10252static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { 10253 Opcode_rfi_Slot_inst_encode, 0, 0 10254}; 10255 10256static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { 10257 Opcode_waiti_Slot_inst_encode, 0, 0 10258}; 10259 10260static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { 10261 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0 10262}; 10263 10264static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { 10265 Opcode_wsr_intset_Slot_inst_encode, 0, 0 10266}; 10267 10268static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { 10269 Opcode_wsr_intclear_Slot_inst_encode, 0, 0 10270}; 10271 10272static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { 10273 Opcode_rsr_intenable_Slot_inst_encode, 0, 0 10274}; 10275 10276static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { 10277 Opcode_wsr_intenable_Slot_inst_encode, 0, 0 10278}; 10279 10280static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { 10281 Opcode_xsr_intenable_Slot_inst_encode, 0, 0 10282}; 10283 10284static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { 10285 Opcode_break_Slot_inst_encode, 0, 0 10286}; 10287 10288static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { 10289 0, 0, Opcode_break_n_Slot_inst16b_encode 10290}; 10291 10292static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { 10293 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0 10294}; 10295 10296static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { 10297 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0 10298}; 10299 10300static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { 10301 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0 10302}; 10303 10304static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { 10305 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0 10306}; 10307 10308static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { 10309 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0 10310}; 10311 10312static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { 10313 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0 10314}; 10315 10316static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { 10317 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0 10318}; 10319 10320static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { 10321 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0 10322}; 10323 10324static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { 10325 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0 10326}; 10327 10328static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { 10329 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0 10330}; 10331 10332static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { 10333 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0 10334}; 10335 10336static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { 10337 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0 10338}; 10339 10340static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { 10341 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0 10342}; 10343 10344static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { 10345 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0 10346}; 10347 10348static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { 10349 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0 10350}; 10351 10352static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { 10353 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0 10354}; 10355 10356static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { 10357 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0 10358}; 10359 10360static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { 10361 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0 10362}; 10363 10364static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { 10365 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0 10366}; 10367 10368static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { 10369 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0 10370}; 10371 10372static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { 10373 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0 10374}; 10375 10376static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { 10377 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0 10378}; 10379 10380static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { 10381 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0 10382}; 10383 10384static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { 10385 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0 10386}; 10387 10388static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { 10389 Opcode_rsr_icount_Slot_inst_encode, 0, 0 10390}; 10391 10392static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { 10393 Opcode_wsr_icount_Slot_inst_encode, 0, 0 10394}; 10395 10396static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { 10397 Opcode_xsr_icount_Slot_inst_encode, 0, 0 10398}; 10399 10400static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { 10401 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0 10402}; 10403 10404static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { 10405 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0 10406}; 10407 10408static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { 10409 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0 10410}; 10411 10412static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { 10413 Opcode_rsr_ddr_Slot_inst_encode, 0, 0 10414}; 10415 10416static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { 10417 Opcode_wsr_ddr_Slot_inst_encode, 0, 0 10418}; 10419 10420static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { 10421 Opcode_xsr_ddr_Slot_inst_encode, 0, 0 10422}; 10423 10424static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { 10425 Opcode_lddr32_p_Slot_inst_encode, 0, 0 10426}; 10427 10428static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { 10429 Opcode_sddr32_p_Slot_inst_encode, 0, 0 10430}; 10431 10432static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { 10433 Opcode_rfdo_Slot_inst_encode, 0, 0 10434}; 10435 10436static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { 10437 Opcode_rfdd_Slot_inst_encode, 0, 0 10438}; 10439 10440static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { 10441 Opcode_wsr_mmid_Slot_inst_encode, 0, 0 10442}; 10443 10444static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { 10445 Opcode_rsr_ccount_Slot_inst_encode, 0, 0 10446}; 10447 10448static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { 10449 Opcode_wsr_ccount_Slot_inst_encode, 0, 0 10450}; 10451 10452static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { 10453 Opcode_xsr_ccount_Slot_inst_encode, 0, 0 10454}; 10455 10456static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { 10457 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0 10458}; 10459 10460static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { 10461 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0 10462}; 10463 10464static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { 10465 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0 10466}; 10467 10468static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { 10469 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0 10470}; 10471 10472static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { 10473 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0 10474}; 10475 10476static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { 10477 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0 10478}; 10479 10480static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { 10481 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0 10482}; 10483 10484static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { 10485 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0 10486}; 10487 10488static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { 10489 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0 10490}; 10491 10492static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { 10493 Opcode_ipf_Slot_inst_encode, 0, 0 10494}; 10495 10496static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { 10497 Opcode_ihi_Slot_inst_encode, 0, 0 10498}; 10499 10500static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { 10501 Opcode_ipfl_Slot_inst_encode, 0, 0 10502}; 10503 10504static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { 10505 Opcode_ihu_Slot_inst_encode, 0, 0 10506}; 10507 10508static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { 10509 Opcode_iiu_Slot_inst_encode, 0, 0 10510}; 10511 10512static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { 10513 Opcode_iii_Slot_inst_encode, 0, 0 10514}; 10515 10516static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { 10517 Opcode_lict_Slot_inst_encode, 0, 0 10518}; 10519 10520static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { 10521 Opcode_licw_Slot_inst_encode, 0, 0 10522}; 10523 10524static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { 10525 Opcode_sict_Slot_inst_encode, 0, 0 10526}; 10527 10528static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { 10529 Opcode_sicw_Slot_inst_encode, 0, 0 10530}; 10531 10532static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { 10533 Opcode_dhwb_Slot_inst_encode, 0, 0 10534}; 10535 10536static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { 10537 Opcode_dhwbi_Slot_inst_encode, 0, 0 10538}; 10539 10540static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { 10541 Opcode_diwbui_p_Slot_inst_encode, 0, 0 10542}; 10543 10544static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { 10545 Opcode_diwb_Slot_inst_encode, 0, 0 10546}; 10547 10548static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { 10549 Opcode_diwbi_Slot_inst_encode, 0, 0 10550}; 10551 10552static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { 10553 Opcode_dhi_Slot_inst_encode, 0, 0 10554}; 10555 10556static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { 10557 Opcode_dii_Slot_inst_encode, 0, 0 10558}; 10559 10560static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { 10561 Opcode_dpfr_Slot_inst_encode, 0, 0 10562}; 10563 10564static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { 10565 Opcode_dpfw_Slot_inst_encode, 0, 0 10566}; 10567 10568static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { 10569 Opcode_dpfro_Slot_inst_encode, 0, 0 10570}; 10571 10572static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { 10573 Opcode_dpfwo_Slot_inst_encode, 0, 0 10574}; 10575 10576static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { 10577 Opcode_dpfl_Slot_inst_encode, 0, 0 10578}; 10579 10580static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { 10581 Opcode_dhu_Slot_inst_encode, 0, 0 10582}; 10583 10584static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { 10585 Opcode_diu_Slot_inst_encode, 0, 0 10586}; 10587 10588static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { 10589 Opcode_sdct_Slot_inst_encode, 0, 0 10590}; 10591 10592static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { 10593 Opcode_ldct_Slot_inst_encode, 0, 0 10594}; 10595 10596static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { 10597 Opcode_idtlb_Slot_inst_encode, 0, 0 10598}; 10599 10600static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { 10601 Opcode_pdtlb_Slot_inst_encode, 0, 0 10602}; 10603 10604static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { 10605 Opcode_rdtlb0_Slot_inst_encode, 0, 0 10606}; 10607 10608static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { 10609 Opcode_rdtlb1_Slot_inst_encode, 0, 0 10610}; 10611 10612static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { 10613 Opcode_wdtlb_Slot_inst_encode, 0, 0 10614}; 10615 10616static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { 10617 Opcode_iitlb_Slot_inst_encode, 0, 0 10618}; 10619 10620static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { 10621 Opcode_pitlb_Slot_inst_encode, 0, 0 10622}; 10623 10624static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { 10625 Opcode_ritlb0_Slot_inst_encode, 0, 0 10626}; 10627 10628static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { 10629 Opcode_ritlb1_Slot_inst_encode, 0, 0 10630}; 10631 10632static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { 10633 Opcode_witlb_Slot_inst_encode, 0, 0 10634}; 10635 10636static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { 10637 Opcode_clamps_Slot_inst_encode, 0, 0 10638}; 10639 10640static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { 10641 Opcode_min_Slot_inst_encode, 0, 0 10642}; 10643 10644static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { 10645 Opcode_max_Slot_inst_encode, 0, 0 10646}; 10647 10648static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { 10649 Opcode_minu_Slot_inst_encode, 0, 0 10650}; 10651 10652static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { 10653 Opcode_maxu_Slot_inst_encode, 0, 0 10654}; 10655 10656static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { 10657 Opcode_nsa_Slot_inst_encode, 0, 0 10658}; 10659 10660static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { 10661 Opcode_nsau_Slot_inst_encode, 0, 0 10662}; 10663 10664static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { 10665 Opcode_sext_Slot_inst_encode, 0, 0 10666}; 10667 10668static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { 10669 Opcode_l32ai_Slot_inst_encode, 0, 0 10670}; 10671 10672static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { 10673 Opcode_s32ri_Slot_inst_encode, 0, 0 10674}; 10675 10676static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { 10677 Opcode_s32c1i_Slot_inst_encode, 0, 0 10678}; 10679 10680static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { 10681 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0 10682}; 10683 10684static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { 10685 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0 10686}; 10687 10688static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { 10689 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0 10690}; 10691 10692static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { 10693 Opcode_rsr_atomctl_Slot_inst_encode, 0, 0 10694}; 10695 10696static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { 10697 Opcode_wsr_atomctl_Slot_inst_encode, 0, 0 10698}; 10699 10700static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { 10701 Opcode_xsr_atomctl_Slot_inst_encode, 0, 0 10702}; 10703 10704static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { 10705 Opcode_quou_Slot_inst_encode, 0, 0 10706}; 10707 10708static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { 10709 Opcode_quos_Slot_inst_encode, 0, 0 10710}; 10711 10712static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { 10713 Opcode_remu_Slot_inst_encode, 0, 0 10714}; 10715 10716static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { 10717 Opcode_rems_Slot_inst_encode, 0, 0 10718}; 10719 10720static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { 10721 Opcode_rer_Slot_inst_encode, 0, 0 10722}; 10723 10724static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { 10725 Opcode_wer_Slot_inst_encode, 0, 0 10726}; 10727 10728static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { 10729 Opcode_rur_expstate_Slot_inst_encode, 0, 0 10730}; 10731 10732static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { 10733 Opcode_wur_expstate_Slot_inst_encode, 0, 0 10734}; 10735 10736static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { 10737 Opcode_read_impwire_Slot_inst_encode, 0, 0 10738}; 10739 10740static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { 10741 Opcode_setb_expstate_Slot_inst_encode, 0, 0 10742}; 10743 10744static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { 10745 Opcode_clrb_expstate_Slot_inst_encode, 0, 0 10746}; 10747 10748static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { 10749 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0 10750}; 10751 10752 10753 10754 10755 10756/* Opcode table. */ 10757 10758static xtensa_opcode_internal opcodes[] = { 10759 { "excw", ICLASS_xt_iclass_excw, 10760 0, 10761 Opcode_excw_encode_fns, 0, 0 }, 10762 { "rfe", ICLASS_xt_iclass_rfe, 10763 XTENSA_OPCODE_IS_JUMP, 10764 Opcode_rfe_encode_fns, 0, 0 }, 10765 { "rfde", ICLASS_xt_iclass_rfde, 10766 XTENSA_OPCODE_IS_JUMP, 10767 Opcode_rfde_encode_fns, 0, 0 }, 10768 { "syscall", ICLASS_xt_iclass_syscall, 10769 0, 10770 Opcode_syscall_encode_fns, 0, 0 }, 10771 { "call12", ICLASS_xt_iclass_call12, 10772 XTENSA_OPCODE_IS_CALL, 10773 Opcode_call12_encode_fns, 0, 0 }, 10774 { "call8", ICLASS_xt_iclass_call8, 10775 XTENSA_OPCODE_IS_CALL, 10776 Opcode_call8_encode_fns, 0, 0 }, 10777 { "call4", ICLASS_xt_iclass_call4, 10778 XTENSA_OPCODE_IS_CALL, 10779 Opcode_call4_encode_fns, 0, 0 }, 10780 { "callx12", ICLASS_xt_iclass_callx12, 10781 XTENSA_OPCODE_IS_CALL, 10782 Opcode_callx12_encode_fns, 0, 0 }, 10783 { "callx8", ICLASS_xt_iclass_callx8, 10784 XTENSA_OPCODE_IS_CALL, 10785 Opcode_callx8_encode_fns, 0, 0 }, 10786 { "callx4", ICLASS_xt_iclass_callx4, 10787 XTENSA_OPCODE_IS_CALL, 10788 Opcode_callx4_encode_fns, 0, 0 }, 10789 { "entry", ICLASS_xt_iclass_entry, 10790 0, 10791 Opcode_entry_encode_fns, 0, 0 }, 10792 { "movsp", ICLASS_xt_iclass_movsp, 10793 0, 10794 Opcode_movsp_encode_fns, 0, 0 }, 10795 { "rotw", ICLASS_xt_iclass_rotw, 10796 0, 10797 Opcode_rotw_encode_fns, 0, 0 }, 10798 { "retw", ICLASS_xt_iclass_retw, 10799 XTENSA_OPCODE_IS_JUMP, 10800 Opcode_retw_encode_fns, 0, 0 }, 10801 { "retw.n", ICLASS_xt_iclass_retw, 10802 XTENSA_OPCODE_IS_JUMP, 10803 Opcode_retw_n_encode_fns, 0, 0 }, 10804 { "rfwo", ICLASS_xt_iclass_rfwou, 10805 XTENSA_OPCODE_IS_JUMP, 10806 Opcode_rfwo_encode_fns, 0, 0 }, 10807 { "rfwu", ICLASS_xt_iclass_rfwou, 10808 XTENSA_OPCODE_IS_JUMP, 10809 Opcode_rfwu_encode_fns, 0, 0 }, 10810 { "l32e", ICLASS_xt_iclass_l32e, 10811 0, 10812 Opcode_l32e_encode_fns, 0, 0 }, 10813 { "s32e", ICLASS_xt_iclass_s32e, 10814 0, 10815 Opcode_s32e_encode_fns, 0, 0 }, 10816 { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, 10817 0, 10818 Opcode_rsr_windowbase_encode_fns, 0, 0 }, 10819 { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, 10820 0, 10821 Opcode_wsr_windowbase_encode_fns, 0, 0 }, 10822 { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, 10823 0, 10824 Opcode_xsr_windowbase_encode_fns, 0, 0 }, 10825 { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, 10826 0, 10827 Opcode_rsr_windowstart_encode_fns, 0, 0 }, 10828 { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, 10829 0, 10830 Opcode_wsr_windowstart_encode_fns, 0, 0 }, 10831 { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, 10832 0, 10833 Opcode_xsr_windowstart_encode_fns, 0, 0 }, 10834 { "add.n", ICLASS_xt_iclass_add_n, 10835 0, 10836 Opcode_add_n_encode_fns, 0, 0 }, 10837 { "addi.n", ICLASS_xt_iclass_addi_n, 10838 0, 10839 Opcode_addi_n_encode_fns, 0, 0 }, 10840 { "beqz.n", ICLASS_xt_iclass_bz6, 10841 XTENSA_OPCODE_IS_BRANCH, 10842 Opcode_beqz_n_encode_fns, 0, 0 }, 10843 { "bnez.n", ICLASS_xt_iclass_bz6, 10844 XTENSA_OPCODE_IS_BRANCH, 10845 Opcode_bnez_n_encode_fns, 0, 0 }, 10846 { "ill.n", ICLASS_xt_iclass_ill_n, 10847 0, 10848 Opcode_ill_n_encode_fns, 0, 0 }, 10849 { "l32i.n", ICLASS_xt_iclass_loadi4, 10850 0, 10851 Opcode_l32i_n_encode_fns, 0, 0 }, 10852 { "mov.n", ICLASS_xt_iclass_mov_n, 10853 0, 10854 Opcode_mov_n_encode_fns, 0, 0 }, 10855 { "movi.n", ICLASS_xt_iclass_movi_n, 10856 0, 10857 Opcode_movi_n_encode_fns, 0, 0 }, 10858 { "nop.n", ICLASS_xt_iclass_nopn, 10859 0, 10860 Opcode_nop_n_encode_fns, 0, 0 }, 10861 { "ret.n", ICLASS_xt_iclass_retn, 10862 XTENSA_OPCODE_IS_JUMP, 10863 Opcode_ret_n_encode_fns, 0, 0 }, 10864 { "s32i.n", ICLASS_xt_iclass_storei4, 10865 0, 10866 Opcode_s32i_n_encode_fns, 0, 0 }, 10867 { "addi", ICLASS_xt_iclass_addi, 10868 0, 10869 Opcode_addi_encode_fns, 0, 0 }, 10870 { "addmi", ICLASS_xt_iclass_addmi, 10871 0, 10872 Opcode_addmi_encode_fns, 0, 0 }, 10873 { "add", ICLASS_xt_iclass_addsub, 10874 0, 10875 Opcode_add_encode_fns, 0, 0 }, 10876 { "sub", ICLASS_xt_iclass_addsub, 10877 0, 10878 Opcode_sub_encode_fns, 0, 0 }, 10879 { "addx2", ICLASS_xt_iclass_addsub, 10880 0, 10881 Opcode_addx2_encode_fns, 0, 0 }, 10882 { "addx4", ICLASS_xt_iclass_addsub, 10883 0, 10884 Opcode_addx4_encode_fns, 0, 0 }, 10885 { "addx8", ICLASS_xt_iclass_addsub, 10886 0, 10887 Opcode_addx8_encode_fns, 0, 0 }, 10888 { "subx2", ICLASS_xt_iclass_addsub, 10889 0, 10890 Opcode_subx2_encode_fns, 0, 0 }, 10891 { "subx4", ICLASS_xt_iclass_addsub, 10892 0, 10893 Opcode_subx4_encode_fns, 0, 0 }, 10894 { "subx8", ICLASS_xt_iclass_addsub, 10895 0, 10896 Opcode_subx8_encode_fns, 0, 0 }, 10897 { "and", ICLASS_xt_iclass_bit, 10898 0, 10899 Opcode_and_encode_fns, 0, 0 }, 10900 { "or", ICLASS_xt_iclass_bit, 10901 0, 10902 Opcode_or_encode_fns, 0, 0 }, 10903 { "xor", ICLASS_xt_iclass_bit, 10904 0, 10905 Opcode_xor_encode_fns, 0, 0 }, 10906 { "beqi", ICLASS_xt_iclass_bsi8, 10907 XTENSA_OPCODE_IS_BRANCH, 10908 Opcode_beqi_encode_fns, 0, 0 }, 10909 { "bnei", ICLASS_xt_iclass_bsi8, 10910 XTENSA_OPCODE_IS_BRANCH, 10911 Opcode_bnei_encode_fns, 0, 0 }, 10912 { "bgei", ICLASS_xt_iclass_bsi8, 10913 XTENSA_OPCODE_IS_BRANCH, 10914 Opcode_bgei_encode_fns, 0, 0 }, 10915 { "blti", ICLASS_xt_iclass_bsi8, 10916 XTENSA_OPCODE_IS_BRANCH, 10917 Opcode_blti_encode_fns, 0, 0 }, 10918 { "bbci", ICLASS_xt_iclass_bsi8b, 10919 XTENSA_OPCODE_IS_BRANCH, 10920 Opcode_bbci_encode_fns, 0, 0 }, 10921 { "bbsi", ICLASS_xt_iclass_bsi8b, 10922 XTENSA_OPCODE_IS_BRANCH, 10923 Opcode_bbsi_encode_fns, 0, 0 }, 10924 { "bgeui", ICLASS_xt_iclass_bsi8u, 10925 XTENSA_OPCODE_IS_BRANCH, 10926 Opcode_bgeui_encode_fns, 0, 0 }, 10927 { "bltui", ICLASS_xt_iclass_bsi8u, 10928 XTENSA_OPCODE_IS_BRANCH, 10929 Opcode_bltui_encode_fns, 0, 0 }, 10930 { "beq", ICLASS_xt_iclass_bst8, 10931 XTENSA_OPCODE_IS_BRANCH, 10932 Opcode_beq_encode_fns, 0, 0 }, 10933 { "bne", ICLASS_xt_iclass_bst8, 10934 XTENSA_OPCODE_IS_BRANCH, 10935 Opcode_bne_encode_fns, 0, 0 }, 10936 { "bge", ICLASS_xt_iclass_bst8, 10937 XTENSA_OPCODE_IS_BRANCH, 10938 Opcode_bge_encode_fns, 0, 0 }, 10939 { "blt", ICLASS_xt_iclass_bst8, 10940 XTENSA_OPCODE_IS_BRANCH, 10941 Opcode_blt_encode_fns, 0, 0 }, 10942 { "bgeu", ICLASS_xt_iclass_bst8, 10943 XTENSA_OPCODE_IS_BRANCH, 10944 Opcode_bgeu_encode_fns, 0, 0 }, 10945 { "bltu", ICLASS_xt_iclass_bst8, 10946 XTENSA_OPCODE_IS_BRANCH, 10947 Opcode_bltu_encode_fns, 0, 0 }, 10948 { "bany", ICLASS_xt_iclass_bst8, 10949 XTENSA_OPCODE_IS_BRANCH, 10950 Opcode_bany_encode_fns, 0, 0 }, 10951 { "bnone", ICLASS_xt_iclass_bst8, 10952 XTENSA_OPCODE_IS_BRANCH, 10953 Opcode_bnone_encode_fns, 0, 0 }, 10954 { "ball", ICLASS_xt_iclass_bst8, 10955 XTENSA_OPCODE_IS_BRANCH, 10956 Opcode_ball_encode_fns, 0, 0 }, 10957 { "bnall", ICLASS_xt_iclass_bst8, 10958 XTENSA_OPCODE_IS_BRANCH, 10959 Opcode_bnall_encode_fns, 0, 0 }, 10960 { "bbc", ICLASS_xt_iclass_bst8, 10961 XTENSA_OPCODE_IS_BRANCH, 10962 Opcode_bbc_encode_fns, 0, 0 }, 10963 { "bbs", ICLASS_xt_iclass_bst8, 10964 XTENSA_OPCODE_IS_BRANCH, 10965 Opcode_bbs_encode_fns, 0, 0 }, 10966 { "beqz", ICLASS_xt_iclass_bsz12, 10967 XTENSA_OPCODE_IS_BRANCH, 10968 Opcode_beqz_encode_fns, 0, 0 }, 10969 { "bnez", ICLASS_xt_iclass_bsz12, 10970 XTENSA_OPCODE_IS_BRANCH, 10971 Opcode_bnez_encode_fns, 0, 0 }, 10972 { "bgez", ICLASS_xt_iclass_bsz12, 10973 XTENSA_OPCODE_IS_BRANCH, 10974 Opcode_bgez_encode_fns, 0, 0 }, 10975 { "bltz", ICLASS_xt_iclass_bsz12, 10976 XTENSA_OPCODE_IS_BRANCH, 10977 Opcode_bltz_encode_fns, 0, 0 }, 10978 { "call0", ICLASS_xt_iclass_call0, 10979 XTENSA_OPCODE_IS_CALL, 10980 Opcode_call0_encode_fns, 0, 0 }, 10981 { "callx0", ICLASS_xt_iclass_callx0, 10982 XTENSA_OPCODE_IS_CALL, 10983 Opcode_callx0_encode_fns, 0, 0 }, 10984 { "extui", ICLASS_xt_iclass_exti, 10985 0, 10986 Opcode_extui_encode_fns, 0, 0 }, 10987 { "ill", ICLASS_xt_iclass_ill, 10988 0, 10989 Opcode_ill_encode_fns, 0, 0 }, 10990 { "j", ICLASS_xt_iclass_jump, 10991 XTENSA_OPCODE_IS_JUMP, 10992 Opcode_j_encode_fns, 0, 0 }, 10993 { "jx", ICLASS_xt_iclass_jumpx, 10994 XTENSA_OPCODE_IS_JUMP, 10995 Opcode_jx_encode_fns, 0, 0 }, 10996 { "l16ui", ICLASS_xt_iclass_l16ui, 10997 0, 10998 Opcode_l16ui_encode_fns, 0, 0 }, 10999 { "l16si", ICLASS_xt_iclass_l16si, 11000 0, 11001 Opcode_l16si_encode_fns, 0, 0 }, 11002 { "l32i", ICLASS_xt_iclass_l32i, 11003 0, 11004 Opcode_l32i_encode_fns, 0, 0 }, 11005 { "l32r", ICLASS_xt_iclass_l32r, 11006 0, 11007 Opcode_l32r_encode_fns, 0, 0 }, 11008 { "l8ui", ICLASS_xt_iclass_l8i, 11009 0, 11010 Opcode_l8ui_encode_fns, 0, 0 }, 11011 { "loop", ICLASS_xt_iclass_loop, 11012 XTENSA_OPCODE_IS_LOOP, 11013 Opcode_loop_encode_fns, 0, 0 }, 11014 { "loopnez", ICLASS_xt_iclass_loopz, 11015 XTENSA_OPCODE_IS_LOOP, 11016 Opcode_loopnez_encode_fns, 0, 0 }, 11017 { "loopgtz", ICLASS_xt_iclass_loopz, 11018 XTENSA_OPCODE_IS_LOOP, 11019 Opcode_loopgtz_encode_fns, 0, 0 }, 11020 { "movi", ICLASS_xt_iclass_movi, 11021 0, 11022 Opcode_movi_encode_fns, 0, 0 }, 11023 { "moveqz", ICLASS_xt_iclass_movz, 11024 0, 11025 Opcode_moveqz_encode_fns, 0, 0 }, 11026 { "movnez", ICLASS_xt_iclass_movz, 11027 0, 11028 Opcode_movnez_encode_fns, 0, 0 }, 11029 { "movltz", ICLASS_xt_iclass_movz, 11030 0, 11031 Opcode_movltz_encode_fns, 0, 0 }, 11032 { "movgez", ICLASS_xt_iclass_movz, 11033 0, 11034 Opcode_movgez_encode_fns, 0, 0 }, 11035 { "neg", ICLASS_xt_iclass_neg, 11036 0, 11037 Opcode_neg_encode_fns, 0, 0 }, 11038 { "abs", ICLASS_xt_iclass_neg, 11039 0, 11040 Opcode_abs_encode_fns, 0, 0 }, 11041 { "nop", ICLASS_xt_iclass_nop, 11042 0, 11043 Opcode_nop_encode_fns, 0, 0 }, 11044 { "ret", ICLASS_xt_iclass_return, 11045 XTENSA_OPCODE_IS_JUMP, 11046 Opcode_ret_encode_fns, 0, 0 }, 11047 { "simcall", ICLASS_xt_iclass_simcall, 11048 0, 11049 Opcode_simcall_encode_fns, 0, 0 }, 11050 { "s16i", ICLASS_xt_iclass_s16i, 11051 0, 11052 Opcode_s16i_encode_fns, 0, 0 }, 11053 { "s32i", ICLASS_xt_iclass_s32i, 11054 0, 11055 Opcode_s32i_encode_fns, 0, 0 }, 11056 { "s32nb", ICLASS_xt_iclass_s32nb, 11057 0, 11058 Opcode_s32nb_encode_fns, 0, 0 }, 11059 { "s8i", ICLASS_xt_iclass_s8i, 11060 0, 11061 Opcode_s8i_encode_fns, 0, 0 }, 11062 { "ssr", ICLASS_xt_iclass_sar, 11063 0, 11064 Opcode_ssr_encode_fns, 0, 0 }, 11065 { "ssl", ICLASS_xt_iclass_sar, 11066 0, 11067 Opcode_ssl_encode_fns, 0, 0 }, 11068 { "ssa8l", ICLASS_xt_iclass_sar, 11069 0, 11070 Opcode_ssa8l_encode_fns, 0, 0 }, 11071 { "ssa8b", ICLASS_xt_iclass_sar, 11072 0, 11073 Opcode_ssa8b_encode_fns, 0, 0 }, 11074 { "ssai", ICLASS_xt_iclass_sari, 11075 0, 11076 Opcode_ssai_encode_fns, 0, 0 }, 11077 { "sll", ICLASS_xt_iclass_shifts, 11078 0, 11079 Opcode_sll_encode_fns, 0, 0 }, 11080 { "src", ICLASS_xt_iclass_shiftst, 11081 0, 11082 Opcode_src_encode_fns, 0, 0 }, 11083 { "srl", ICLASS_xt_iclass_shiftt, 11084 0, 11085 Opcode_srl_encode_fns, 0, 0 }, 11086 { "sra", ICLASS_xt_iclass_shiftt, 11087 0, 11088 Opcode_sra_encode_fns, 0, 0 }, 11089 { "slli", ICLASS_xt_iclass_slli, 11090 0, 11091 Opcode_slli_encode_fns, 0, 0 }, 11092 { "srai", ICLASS_xt_iclass_srai, 11093 0, 11094 Opcode_srai_encode_fns, 0, 0 }, 11095 { "srli", ICLASS_xt_iclass_srli, 11096 0, 11097 Opcode_srli_encode_fns, 0, 0 }, 11098 { "memw", ICLASS_xt_iclass_memw, 11099 0, 11100 Opcode_memw_encode_fns, 0, 0 }, 11101 { "extw", ICLASS_xt_iclass_extw, 11102 0, 11103 Opcode_extw_encode_fns, 0, 0 }, 11104 { "isync", ICLASS_xt_iclass_isync, 11105 0, 11106 Opcode_isync_encode_fns, 0, 0 }, 11107 { "rsync", ICLASS_xt_iclass_sync, 11108 0, 11109 Opcode_rsync_encode_fns, 0, 0 }, 11110 { "esync", ICLASS_xt_iclass_sync, 11111 0, 11112 Opcode_esync_encode_fns, 0, 0 }, 11113 { "dsync", ICLASS_xt_iclass_sync, 11114 0, 11115 Opcode_dsync_encode_fns, 0, 0 }, 11116 { "rsil", ICLASS_xt_iclass_rsil, 11117 0, 11118 Opcode_rsil_encode_fns, 0, 0 }, 11119 { "rsr.lend", ICLASS_xt_iclass_rsr_lend, 11120 0, 11121 Opcode_rsr_lend_encode_fns, 0, 0 }, 11122 { "wsr.lend", ICLASS_xt_iclass_wsr_lend, 11123 0, 11124 Opcode_wsr_lend_encode_fns, 0, 0 }, 11125 { "xsr.lend", ICLASS_xt_iclass_xsr_lend, 11126 0, 11127 Opcode_xsr_lend_encode_fns, 0, 0 }, 11128 { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, 11129 0, 11130 Opcode_rsr_lcount_encode_fns, 0, 0 }, 11131 { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, 11132 0, 11133 Opcode_wsr_lcount_encode_fns, 0, 0 }, 11134 { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, 11135 0, 11136 Opcode_xsr_lcount_encode_fns, 0, 0 }, 11137 { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, 11138 0, 11139 Opcode_rsr_lbeg_encode_fns, 0, 0 }, 11140 { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, 11141 0, 11142 Opcode_wsr_lbeg_encode_fns, 0, 0 }, 11143 { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, 11144 0, 11145 Opcode_xsr_lbeg_encode_fns, 0, 0 }, 11146 { "rsr.sar", ICLASS_xt_iclass_rsr_sar, 11147 0, 11148 Opcode_rsr_sar_encode_fns, 0, 0 }, 11149 { "wsr.sar", ICLASS_xt_iclass_wsr_sar, 11150 0, 11151 Opcode_wsr_sar_encode_fns, 0, 0 }, 11152 { "xsr.sar", ICLASS_xt_iclass_xsr_sar, 11153 0, 11154 Opcode_xsr_sar_encode_fns, 0, 0 }, 11155 { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, 11156 0, 11157 Opcode_rsr_memctl_encode_fns, 0, 0 }, 11158 { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, 11159 0, 11160 Opcode_wsr_memctl_encode_fns, 0, 0 }, 11161 { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, 11162 0, 11163 Opcode_xsr_memctl_encode_fns, 0, 0 }, 11164 { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, 11165 0, 11166 Opcode_rsr_litbase_encode_fns, 0, 0 }, 11167 { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, 11168 0, 11169 Opcode_wsr_litbase_encode_fns, 0, 0 }, 11170 { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, 11171 0, 11172 Opcode_xsr_litbase_encode_fns, 0, 0 }, 11173 { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, 11174 0, 11175 Opcode_rsr_configid0_encode_fns, 0, 0 }, 11176 { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, 11177 0, 11178 Opcode_wsr_configid0_encode_fns, 0, 0 }, 11179 { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, 11180 0, 11181 Opcode_rsr_configid1_encode_fns, 0, 0 }, 11182 { "rsr.ps", ICLASS_xt_iclass_rsr_ps, 11183 0, 11184 Opcode_rsr_ps_encode_fns, 0, 0 }, 11185 { "wsr.ps", ICLASS_xt_iclass_wsr_ps, 11186 0, 11187 Opcode_wsr_ps_encode_fns, 0, 0 }, 11188 { "xsr.ps", ICLASS_xt_iclass_xsr_ps, 11189 0, 11190 Opcode_xsr_ps_encode_fns, 0, 0 }, 11191 { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, 11192 0, 11193 Opcode_rsr_epc1_encode_fns, 0, 0 }, 11194 { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, 11195 0, 11196 Opcode_wsr_epc1_encode_fns, 0, 0 }, 11197 { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, 11198 0, 11199 Opcode_xsr_epc1_encode_fns, 0, 0 }, 11200 { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, 11201 0, 11202 Opcode_rsr_excsave1_encode_fns, 0, 0 }, 11203 { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, 11204 0, 11205 Opcode_wsr_excsave1_encode_fns, 0, 0 }, 11206 { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, 11207 0, 11208 Opcode_xsr_excsave1_encode_fns, 0, 0 }, 11209 { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, 11210 0, 11211 Opcode_rsr_epc2_encode_fns, 0, 0 }, 11212 { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, 11213 0, 11214 Opcode_wsr_epc2_encode_fns, 0, 0 }, 11215 { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, 11216 0, 11217 Opcode_xsr_epc2_encode_fns, 0, 0 }, 11218 { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, 11219 0, 11220 Opcode_rsr_excsave2_encode_fns, 0, 0 }, 11221 { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, 11222 0, 11223 Opcode_wsr_excsave2_encode_fns, 0, 0 }, 11224 { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, 11225 0, 11226 Opcode_xsr_excsave2_encode_fns, 0, 0 }, 11227 { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, 11228 0, 11229 Opcode_rsr_epc3_encode_fns, 0, 0 }, 11230 { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, 11231 0, 11232 Opcode_wsr_epc3_encode_fns, 0, 0 }, 11233 { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, 11234 0, 11235 Opcode_xsr_epc3_encode_fns, 0, 0 }, 11236 { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, 11237 0, 11238 Opcode_rsr_excsave3_encode_fns, 0, 0 }, 11239 { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, 11240 0, 11241 Opcode_wsr_excsave3_encode_fns, 0, 0 }, 11242 { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, 11243 0, 11244 Opcode_xsr_excsave3_encode_fns, 0, 0 }, 11245 { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, 11246 0, 11247 Opcode_rsr_epc4_encode_fns, 0, 0 }, 11248 { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, 11249 0, 11250 Opcode_wsr_epc4_encode_fns, 0, 0 }, 11251 { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, 11252 0, 11253 Opcode_xsr_epc4_encode_fns, 0, 0 }, 11254 { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, 11255 0, 11256 Opcode_rsr_excsave4_encode_fns, 0, 0 }, 11257 { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, 11258 0, 11259 Opcode_wsr_excsave4_encode_fns, 0, 0 }, 11260 { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, 11261 0, 11262 Opcode_xsr_excsave4_encode_fns, 0, 0 }, 11263 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, 11264 0, 11265 Opcode_rsr_epc5_encode_fns, 0, 0 }, 11266 { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, 11267 0, 11268 Opcode_wsr_epc5_encode_fns, 0, 0 }, 11269 { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, 11270 0, 11271 Opcode_xsr_epc5_encode_fns, 0, 0 }, 11272 { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, 11273 0, 11274 Opcode_rsr_excsave5_encode_fns, 0, 0 }, 11275 { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, 11276 0, 11277 Opcode_wsr_excsave5_encode_fns, 0, 0 }, 11278 { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, 11279 0, 11280 Opcode_xsr_excsave5_encode_fns, 0, 0 }, 11281 { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, 11282 0, 11283 Opcode_rsr_epc6_encode_fns, 0, 0 }, 11284 { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, 11285 0, 11286 Opcode_wsr_epc6_encode_fns, 0, 0 }, 11287 { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, 11288 0, 11289 Opcode_xsr_epc6_encode_fns, 0, 0 }, 11290 { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, 11291 0, 11292 Opcode_rsr_excsave6_encode_fns, 0, 0 }, 11293 { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, 11294 0, 11295 Opcode_wsr_excsave6_encode_fns, 0, 0 }, 11296 { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, 11297 0, 11298 Opcode_xsr_excsave6_encode_fns, 0, 0 }, 11299 { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, 11300 0, 11301 Opcode_rsr_epc7_encode_fns, 0, 0 }, 11302 { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, 11303 0, 11304 Opcode_wsr_epc7_encode_fns, 0, 0 }, 11305 { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, 11306 0, 11307 Opcode_xsr_epc7_encode_fns, 0, 0 }, 11308 { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, 11309 0, 11310 Opcode_rsr_excsave7_encode_fns, 0, 0 }, 11311 { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, 11312 0, 11313 Opcode_wsr_excsave7_encode_fns, 0, 0 }, 11314 { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, 11315 0, 11316 Opcode_xsr_excsave7_encode_fns, 0, 0 }, 11317 { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, 11318 0, 11319 Opcode_rsr_eps2_encode_fns, 0, 0 }, 11320 { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, 11321 0, 11322 Opcode_wsr_eps2_encode_fns, 0, 0 }, 11323 { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, 11324 0, 11325 Opcode_xsr_eps2_encode_fns, 0, 0 }, 11326 { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, 11327 0, 11328 Opcode_rsr_eps3_encode_fns, 0, 0 }, 11329 { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, 11330 0, 11331 Opcode_wsr_eps3_encode_fns, 0, 0 }, 11332 { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, 11333 0, 11334 Opcode_xsr_eps3_encode_fns, 0, 0 }, 11335 { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, 11336 0, 11337 Opcode_rsr_eps4_encode_fns, 0, 0 }, 11338 { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, 11339 0, 11340 Opcode_wsr_eps4_encode_fns, 0, 0 }, 11341 { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, 11342 0, 11343 Opcode_xsr_eps4_encode_fns, 0, 0 }, 11344 { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, 11345 0, 11346 Opcode_rsr_eps5_encode_fns, 0, 0 }, 11347 { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, 11348 0, 11349 Opcode_wsr_eps5_encode_fns, 0, 0 }, 11350 { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, 11351 0, 11352 Opcode_xsr_eps5_encode_fns, 0, 0 }, 11353 { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, 11354 0, 11355 Opcode_rsr_eps6_encode_fns, 0, 0 }, 11356 { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, 11357 0, 11358 Opcode_wsr_eps6_encode_fns, 0, 0 }, 11359 { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, 11360 0, 11361 Opcode_xsr_eps6_encode_fns, 0, 0 }, 11362 { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, 11363 0, 11364 Opcode_rsr_eps7_encode_fns, 0, 0 }, 11365 { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, 11366 0, 11367 Opcode_wsr_eps7_encode_fns, 0, 0 }, 11368 { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, 11369 0, 11370 Opcode_xsr_eps7_encode_fns, 0, 0 }, 11371 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, 11372 0, 11373 Opcode_rsr_excvaddr_encode_fns, 0, 0 }, 11374 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, 11375 0, 11376 Opcode_wsr_excvaddr_encode_fns, 0, 0 }, 11377 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, 11378 0, 11379 Opcode_xsr_excvaddr_encode_fns, 0, 0 }, 11380 { "rsr.depc", ICLASS_xt_iclass_rsr_depc, 11381 0, 11382 Opcode_rsr_depc_encode_fns, 0, 0 }, 11383 { "wsr.depc", ICLASS_xt_iclass_wsr_depc, 11384 0, 11385 Opcode_wsr_depc_encode_fns, 0, 0 }, 11386 { "xsr.depc", ICLASS_xt_iclass_xsr_depc, 11387 0, 11388 Opcode_xsr_depc_encode_fns, 0, 0 }, 11389 { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, 11390 0, 11391 Opcode_rsr_exccause_encode_fns, 0, 0 }, 11392 { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, 11393 0, 11394 Opcode_wsr_exccause_encode_fns, 0, 0 }, 11395 { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, 11396 0, 11397 Opcode_xsr_exccause_encode_fns, 0, 0 }, 11398 { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, 11399 0, 11400 Opcode_rsr_misc0_encode_fns, 0, 0 }, 11401 { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, 11402 0, 11403 Opcode_wsr_misc0_encode_fns, 0, 0 }, 11404 { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, 11405 0, 11406 Opcode_xsr_misc0_encode_fns, 0, 0 }, 11407 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, 11408 0, 11409 Opcode_rsr_misc1_encode_fns, 0, 0 }, 11410 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, 11411 0, 11412 Opcode_wsr_misc1_encode_fns, 0, 0 }, 11413 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, 11414 0, 11415 Opcode_xsr_misc1_encode_fns, 0, 0 }, 11416 { "rsr.prid", ICLASS_xt_iclass_rsr_prid, 11417 0, 11418 Opcode_rsr_prid_encode_fns, 0, 0 }, 11419 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, 11420 0, 11421 Opcode_rsr_vecbase_encode_fns, 0, 0 }, 11422 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, 11423 0, 11424 Opcode_wsr_vecbase_encode_fns, 0, 0 }, 11425 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, 11426 0, 11427 Opcode_xsr_vecbase_encode_fns, 0, 0 }, 11428 { "mul16u", ICLASS_xt_mul16, 11429 0, 11430 Opcode_mul16u_encode_fns, 0, 0 }, 11431 { "mul16s", ICLASS_xt_mul16, 11432 0, 11433 Opcode_mul16s_encode_fns, 0, 0 }, 11434 { "mull", ICLASS_xt_mul32, 11435 0, 11436 Opcode_mull_encode_fns, 0, 0 }, 11437 { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, 11438 0, 11439 Opcode_mul_aa_ll_encode_fns, 0, 0 }, 11440 { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, 11441 0, 11442 Opcode_mul_aa_hl_encode_fns, 0, 0 }, 11443 { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, 11444 0, 11445 Opcode_mul_aa_lh_encode_fns, 0, 0 }, 11446 { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, 11447 0, 11448 Opcode_mul_aa_hh_encode_fns, 0, 0 }, 11449 { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, 11450 0, 11451 Opcode_umul_aa_ll_encode_fns, 0, 0 }, 11452 { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, 11453 0, 11454 Opcode_umul_aa_hl_encode_fns, 0, 0 }, 11455 { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, 11456 0, 11457 Opcode_umul_aa_lh_encode_fns, 0, 0 }, 11458 { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, 11459 0, 11460 Opcode_umul_aa_hh_encode_fns, 0, 0 }, 11461 { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, 11462 0, 11463 Opcode_mul_ad_ll_encode_fns, 0, 0 }, 11464 { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, 11465 0, 11466 Opcode_mul_ad_hl_encode_fns, 0, 0 }, 11467 { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, 11468 0, 11469 Opcode_mul_ad_lh_encode_fns, 0, 0 }, 11470 { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, 11471 0, 11472 Opcode_mul_ad_hh_encode_fns, 0, 0 }, 11473 { "mul.da.ll", ICLASS_xt_iclass_mac16_da, 11474 0, 11475 Opcode_mul_da_ll_encode_fns, 0, 0 }, 11476 { "mul.da.hl", ICLASS_xt_iclass_mac16_da, 11477 0, 11478 Opcode_mul_da_hl_encode_fns, 0, 0 }, 11479 { "mul.da.lh", ICLASS_xt_iclass_mac16_da, 11480 0, 11481 Opcode_mul_da_lh_encode_fns, 0, 0 }, 11482 { "mul.da.hh", ICLASS_xt_iclass_mac16_da, 11483 0, 11484 Opcode_mul_da_hh_encode_fns, 0, 0 }, 11485 { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, 11486 0, 11487 Opcode_mul_dd_ll_encode_fns, 0, 0 }, 11488 { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, 11489 0, 11490 Opcode_mul_dd_hl_encode_fns, 0, 0 }, 11491 { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, 11492 0, 11493 Opcode_mul_dd_lh_encode_fns, 0, 0 }, 11494 { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, 11495 0, 11496 Opcode_mul_dd_hh_encode_fns, 0, 0 }, 11497 { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, 11498 0, 11499 Opcode_mula_aa_ll_encode_fns, 0, 0 }, 11500 { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, 11501 0, 11502 Opcode_mula_aa_hl_encode_fns, 0, 0 }, 11503 { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, 11504 0, 11505 Opcode_mula_aa_lh_encode_fns, 0, 0 }, 11506 { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, 11507 0, 11508 Opcode_mula_aa_hh_encode_fns, 0, 0 }, 11509 { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, 11510 0, 11511 Opcode_muls_aa_ll_encode_fns, 0, 0 }, 11512 { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, 11513 0, 11514 Opcode_muls_aa_hl_encode_fns, 0, 0 }, 11515 { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, 11516 0, 11517 Opcode_muls_aa_lh_encode_fns, 0, 0 }, 11518 { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, 11519 0, 11520 Opcode_muls_aa_hh_encode_fns, 0, 0 }, 11521 { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, 11522 0, 11523 Opcode_mula_ad_ll_encode_fns, 0, 0 }, 11524 { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, 11525 0, 11526 Opcode_mula_ad_hl_encode_fns, 0, 0 }, 11527 { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, 11528 0, 11529 Opcode_mula_ad_lh_encode_fns, 0, 0 }, 11530 { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, 11531 0, 11532 Opcode_mula_ad_hh_encode_fns, 0, 0 }, 11533 { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, 11534 0, 11535 Opcode_muls_ad_ll_encode_fns, 0, 0 }, 11536 { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, 11537 0, 11538 Opcode_muls_ad_hl_encode_fns, 0, 0 }, 11539 { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, 11540 0, 11541 Opcode_muls_ad_lh_encode_fns, 0, 0 }, 11542 { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, 11543 0, 11544 Opcode_muls_ad_hh_encode_fns, 0, 0 }, 11545 { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, 11546 0, 11547 Opcode_mula_da_ll_encode_fns, 0, 0 }, 11548 { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, 11549 0, 11550 Opcode_mula_da_hl_encode_fns, 0, 0 }, 11551 { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, 11552 0, 11553 Opcode_mula_da_lh_encode_fns, 0, 0 }, 11554 { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, 11555 0, 11556 Opcode_mula_da_hh_encode_fns, 0, 0 }, 11557 { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, 11558 0, 11559 Opcode_muls_da_ll_encode_fns, 0, 0 }, 11560 { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, 11561 0, 11562 Opcode_muls_da_hl_encode_fns, 0, 0 }, 11563 { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, 11564 0, 11565 Opcode_muls_da_lh_encode_fns, 0, 0 }, 11566 { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, 11567 0, 11568 Opcode_muls_da_hh_encode_fns, 0, 0 }, 11569 { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, 11570 0, 11571 Opcode_mula_dd_ll_encode_fns, 0, 0 }, 11572 { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, 11573 0, 11574 Opcode_mula_dd_hl_encode_fns, 0, 0 }, 11575 { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, 11576 0, 11577 Opcode_mula_dd_lh_encode_fns, 0, 0 }, 11578 { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, 11579 0, 11580 Opcode_mula_dd_hh_encode_fns, 0, 0 }, 11581 { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, 11582 0, 11583 Opcode_muls_dd_ll_encode_fns, 0, 0 }, 11584 { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, 11585 0, 11586 Opcode_muls_dd_hl_encode_fns, 0, 0 }, 11587 { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, 11588 0, 11589 Opcode_muls_dd_lh_encode_fns, 0, 0 }, 11590 { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, 11591 0, 11592 Opcode_muls_dd_hh_encode_fns, 0, 0 }, 11593 { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, 11594 0, 11595 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, 11596 { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, 11597 0, 11598 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, 11599 { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, 11600 0, 11601 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, 11602 { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, 11603 0, 11604 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, 11605 { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, 11606 0, 11607 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, 11608 { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, 11609 0, 11610 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, 11611 { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, 11612 0, 11613 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, 11614 { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, 11615 0, 11616 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, 11617 { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, 11618 0, 11619 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, 11620 { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, 11621 0, 11622 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, 11623 { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, 11624 0, 11625 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, 11626 { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, 11627 0, 11628 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, 11629 { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, 11630 0, 11631 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, 11632 { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, 11633 0, 11634 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, 11635 { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, 11636 0, 11637 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, 11638 { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, 11639 0, 11640 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, 11641 { "lddec", ICLASS_xt_iclass_mac16_l, 11642 0, 11643 Opcode_lddec_encode_fns, 0, 0 }, 11644 { "ldinc", ICLASS_xt_iclass_mac16_l, 11645 0, 11646 Opcode_ldinc_encode_fns, 0, 0 }, 11647 { "rsr.m0", ICLASS_xt_iclass_rsr_m0, 11648 0, 11649 Opcode_rsr_m0_encode_fns, 0, 0 }, 11650 { "wsr.m0", ICLASS_xt_iclass_wsr_m0, 11651 0, 11652 Opcode_wsr_m0_encode_fns, 0, 0 }, 11653 { "xsr.m0", ICLASS_xt_iclass_xsr_m0, 11654 0, 11655 Opcode_xsr_m0_encode_fns, 0, 0 }, 11656 { "rsr.m1", ICLASS_xt_iclass_rsr_m1, 11657 0, 11658 Opcode_rsr_m1_encode_fns, 0, 0 }, 11659 { "wsr.m1", ICLASS_xt_iclass_wsr_m1, 11660 0, 11661 Opcode_wsr_m1_encode_fns, 0, 0 }, 11662 { "xsr.m1", ICLASS_xt_iclass_xsr_m1, 11663 0, 11664 Opcode_xsr_m1_encode_fns, 0, 0 }, 11665 { "rsr.m2", ICLASS_xt_iclass_rsr_m2, 11666 0, 11667 Opcode_rsr_m2_encode_fns, 0, 0 }, 11668 { "wsr.m2", ICLASS_xt_iclass_wsr_m2, 11669 0, 11670 Opcode_wsr_m2_encode_fns, 0, 0 }, 11671 { "xsr.m2", ICLASS_xt_iclass_xsr_m2, 11672 0, 11673 Opcode_xsr_m2_encode_fns, 0, 0 }, 11674 { "rsr.m3", ICLASS_xt_iclass_rsr_m3, 11675 0, 11676 Opcode_rsr_m3_encode_fns, 0, 0 }, 11677 { "wsr.m3", ICLASS_xt_iclass_wsr_m3, 11678 0, 11679 Opcode_wsr_m3_encode_fns, 0, 0 }, 11680 { "xsr.m3", ICLASS_xt_iclass_xsr_m3, 11681 0, 11682 Opcode_xsr_m3_encode_fns, 0, 0 }, 11683 { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, 11684 0, 11685 Opcode_rsr_acclo_encode_fns, 0, 0 }, 11686 { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, 11687 0, 11688 Opcode_wsr_acclo_encode_fns, 0, 0 }, 11689 { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, 11690 0, 11691 Opcode_xsr_acclo_encode_fns, 0, 0 }, 11692 { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, 11693 0, 11694 Opcode_rsr_acchi_encode_fns, 0, 0 }, 11695 { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, 11696 0, 11697 Opcode_wsr_acchi_encode_fns, 0, 0 }, 11698 { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, 11699 0, 11700 Opcode_xsr_acchi_encode_fns, 0, 0 }, 11701 { "rfi", ICLASS_xt_iclass_rfi, 11702 XTENSA_OPCODE_IS_JUMP, 11703 Opcode_rfi_encode_fns, 0, 0 }, 11704 { "waiti", ICLASS_xt_iclass_wait, 11705 0, 11706 Opcode_waiti_encode_fns, 0, 0 }, 11707 { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, 11708 0, 11709 Opcode_rsr_interrupt_encode_fns, 0, 0 }, 11710 { "wsr.intset", ICLASS_xt_iclass_wsr_intset, 11711 0, 11712 Opcode_wsr_intset_encode_fns, 0, 0 }, 11713 { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, 11714 0, 11715 Opcode_wsr_intclear_encode_fns, 0, 0 }, 11716 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, 11717 0, 11718 Opcode_rsr_intenable_encode_fns, 0, 0 }, 11719 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, 11720 0, 11721 Opcode_wsr_intenable_encode_fns, 0, 0 }, 11722 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, 11723 0, 11724 Opcode_xsr_intenable_encode_fns, 0, 0 }, 11725 { "break", ICLASS_xt_iclass_break, 11726 0, 11727 Opcode_break_encode_fns, 0, 0 }, 11728 { "break.n", ICLASS_xt_iclass_break_n, 11729 0, 11730 Opcode_break_n_encode_fns, 0, 0 }, 11731 { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, 11732 0, 11733 Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, 11734 { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, 11735 0, 11736 Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, 11737 { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, 11738 0, 11739 Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, 11740 { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, 11741 0, 11742 Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, 11743 { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, 11744 0, 11745 Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, 11746 { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, 11747 0, 11748 Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, 11749 { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, 11750 0, 11751 Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, 11752 { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, 11753 0, 11754 Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, 11755 { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, 11756 0, 11757 Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, 11758 { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, 11759 0, 11760 Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, 11761 { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, 11762 0, 11763 Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, 11764 { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, 11765 0, 11766 Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, 11767 { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, 11768 0, 11769 Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, 11770 { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, 11771 0, 11772 Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, 11773 { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, 11774 0, 11775 Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, 11776 { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, 11777 0, 11778 Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, 11779 { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, 11780 0, 11781 Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, 11782 { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, 11783 0, 11784 Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, 11785 { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, 11786 0, 11787 Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, 11788 { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, 11789 0, 11790 Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, 11791 { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, 11792 0, 11793 Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, 11794 { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, 11795 0, 11796 Opcode_rsr_debugcause_encode_fns, 0, 0 }, 11797 { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, 11798 0, 11799 Opcode_wsr_debugcause_encode_fns, 0, 0 }, 11800 { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, 11801 0, 11802 Opcode_xsr_debugcause_encode_fns, 0, 0 }, 11803 { "rsr.icount", ICLASS_xt_iclass_rsr_icount, 11804 0, 11805 Opcode_rsr_icount_encode_fns, 0, 0 }, 11806 { "wsr.icount", ICLASS_xt_iclass_wsr_icount, 11807 0, 11808 Opcode_wsr_icount_encode_fns, 0, 0 }, 11809 { "xsr.icount", ICLASS_xt_iclass_xsr_icount, 11810 0, 11811 Opcode_xsr_icount_encode_fns, 0, 0 }, 11812 { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, 11813 0, 11814 Opcode_rsr_icountlevel_encode_fns, 0, 0 }, 11815 { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, 11816 0, 11817 Opcode_wsr_icountlevel_encode_fns, 0, 0 }, 11818 { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, 11819 0, 11820 Opcode_xsr_icountlevel_encode_fns, 0, 0 }, 11821 { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, 11822 0, 11823 Opcode_rsr_ddr_encode_fns, 0, 0 }, 11824 { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, 11825 0, 11826 Opcode_wsr_ddr_encode_fns, 0, 0 }, 11827 { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, 11828 0, 11829 Opcode_xsr_ddr_encode_fns, 0, 0 }, 11830 { "lddr32.p", ICLASS_xt_iclass_lddr32_p, 11831 0, 11832 Opcode_lddr32_p_encode_fns, 0, 0 }, 11833 { "sddr32.p", ICLASS_xt_iclass_sddr32_p, 11834 0, 11835 Opcode_sddr32_p_encode_fns, 0, 0 }, 11836 { "rfdo", ICLASS_xt_iclass_rfdo, 11837 XTENSA_OPCODE_IS_JUMP, 11838 Opcode_rfdo_encode_fns, 0, 0 }, 11839 { "rfdd", ICLASS_xt_iclass_rfdd, 11840 XTENSA_OPCODE_IS_JUMP, 11841 Opcode_rfdd_encode_fns, 0, 0 }, 11842 { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, 11843 0, 11844 Opcode_wsr_mmid_encode_fns, 0, 0 }, 11845 { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, 11846 0, 11847 Opcode_rsr_ccount_encode_fns, 0, 0 }, 11848 { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, 11849 0, 11850 Opcode_wsr_ccount_encode_fns, 0, 0 }, 11851 { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, 11852 0, 11853 Opcode_xsr_ccount_encode_fns, 0, 0 }, 11854 { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, 11855 0, 11856 Opcode_rsr_ccompare0_encode_fns, 0, 0 }, 11857 { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, 11858 0, 11859 Opcode_wsr_ccompare0_encode_fns, 0, 0 }, 11860 { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, 11861 0, 11862 Opcode_xsr_ccompare0_encode_fns, 0, 0 }, 11863 { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, 11864 0, 11865 Opcode_rsr_ccompare1_encode_fns, 0, 0 }, 11866 { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, 11867 0, 11868 Opcode_wsr_ccompare1_encode_fns, 0, 0 }, 11869 { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, 11870 0, 11871 Opcode_xsr_ccompare1_encode_fns, 0, 0 }, 11872 { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, 11873 0, 11874 Opcode_rsr_ccompare2_encode_fns, 0, 0 }, 11875 { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, 11876 0, 11877 Opcode_wsr_ccompare2_encode_fns, 0, 0 }, 11878 { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, 11879 0, 11880 Opcode_xsr_ccompare2_encode_fns, 0, 0 }, 11881 { "ipf", ICLASS_xt_iclass_icache, 11882 0, 11883 Opcode_ipf_encode_fns, 0, 0 }, 11884 { "ihi", ICLASS_xt_iclass_icache, 11885 0, 11886 Opcode_ihi_encode_fns, 0, 0 }, 11887 { "ipfl", ICLASS_xt_iclass_icache_lock, 11888 0, 11889 Opcode_ipfl_encode_fns, 0, 0 }, 11890 { "ihu", ICLASS_xt_iclass_icache_lock, 11891 0, 11892 Opcode_ihu_encode_fns, 0, 0 }, 11893 { "iiu", ICLASS_xt_iclass_icache_lock, 11894 0, 11895 Opcode_iiu_encode_fns, 0, 0 }, 11896 { "iii", ICLASS_xt_iclass_icache_inv, 11897 0, 11898 Opcode_iii_encode_fns, 0, 0 }, 11899 { "lict", ICLASS_xt_iclass_licx, 11900 0, 11901 Opcode_lict_encode_fns, 0, 0 }, 11902 { "licw", ICLASS_xt_iclass_licx, 11903 0, 11904 Opcode_licw_encode_fns, 0, 0 }, 11905 { "sict", ICLASS_xt_iclass_sicx, 11906 0, 11907 Opcode_sict_encode_fns, 0, 0 }, 11908 { "sicw", ICLASS_xt_iclass_sicx, 11909 0, 11910 Opcode_sicw_encode_fns, 0, 0 }, 11911 { "dhwb", ICLASS_xt_iclass_dcache, 11912 0, 11913 Opcode_dhwb_encode_fns, 0, 0 }, 11914 { "dhwbi", ICLASS_xt_iclass_dcache, 11915 0, 11916 Opcode_dhwbi_encode_fns, 0, 0 }, 11917 { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, 11918 0, 11919 Opcode_diwbui_p_encode_fns, 0, 0 }, 11920 { "diwb", ICLASS_xt_iclass_dcache_ind, 11921 0, 11922 Opcode_diwb_encode_fns, 0, 0 }, 11923 { "diwbi", ICLASS_xt_iclass_dcache_ind, 11924 0, 11925 Opcode_diwbi_encode_fns, 0, 0 }, 11926 { "dhi", ICLASS_xt_iclass_dcache_inv, 11927 0, 11928 Opcode_dhi_encode_fns, 0, 0 }, 11929 { "dii", ICLASS_xt_iclass_dcache_inv, 11930 0, 11931 Opcode_dii_encode_fns, 0, 0 }, 11932 { "dpfr", ICLASS_xt_iclass_dpf, 11933 0, 11934 Opcode_dpfr_encode_fns, 0, 0 }, 11935 { "dpfw", ICLASS_xt_iclass_dpf, 11936 0, 11937 Opcode_dpfw_encode_fns, 0, 0 }, 11938 { "dpfro", ICLASS_xt_iclass_dpf, 11939 0, 11940 Opcode_dpfro_encode_fns, 0, 0 }, 11941 { "dpfwo", ICLASS_xt_iclass_dpf, 11942 0, 11943 Opcode_dpfwo_encode_fns, 0, 0 }, 11944 { "dpfl", ICLASS_xt_iclass_dcache_lock, 11945 0, 11946 Opcode_dpfl_encode_fns, 0, 0 }, 11947 { "dhu", ICLASS_xt_iclass_dcache_lock, 11948 0, 11949 Opcode_dhu_encode_fns, 0, 0 }, 11950 { "diu", ICLASS_xt_iclass_dcache_lock, 11951 0, 11952 Opcode_diu_encode_fns, 0, 0 }, 11953 { "sdct", ICLASS_xt_iclass_sdct, 11954 0, 11955 Opcode_sdct_encode_fns, 0, 0 }, 11956 { "ldct", ICLASS_xt_iclass_ldct, 11957 0, 11958 Opcode_ldct_encode_fns, 0, 0 }, 11959 { "idtlb", ICLASS_xt_iclass_idtlb, 11960 0, 11961 Opcode_idtlb_encode_fns, 0, 0 }, 11962 { "pdtlb", ICLASS_xt_iclass_rdtlb, 11963 0, 11964 Opcode_pdtlb_encode_fns, 0, 0 }, 11965 { "rdtlb0", ICLASS_xt_iclass_rdtlb, 11966 0, 11967 Opcode_rdtlb0_encode_fns, 0, 0 }, 11968 { "rdtlb1", ICLASS_xt_iclass_rdtlb, 11969 0, 11970 Opcode_rdtlb1_encode_fns, 0, 0 }, 11971 { "wdtlb", ICLASS_xt_iclass_wdtlb, 11972 0, 11973 Opcode_wdtlb_encode_fns, 0, 0 }, 11974 { "iitlb", ICLASS_xt_iclass_iitlb, 11975 0, 11976 Opcode_iitlb_encode_fns, 0, 0 }, 11977 { "pitlb", ICLASS_xt_iclass_ritlb, 11978 0, 11979 Opcode_pitlb_encode_fns, 0, 0 }, 11980 { "ritlb0", ICLASS_xt_iclass_ritlb, 11981 0, 11982 Opcode_ritlb0_encode_fns, 0, 0 }, 11983 { "ritlb1", ICLASS_xt_iclass_ritlb, 11984 0, 11985 Opcode_ritlb1_encode_fns, 0, 0 }, 11986 { "witlb", ICLASS_xt_iclass_witlb, 11987 0, 11988 Opcode_witlb_encode_fns, 0, 0 }, 11989 { "clamps", ICLASS_xt_iclass_clamp, 11990 0, 11991 Opcode_clamps_encode_fns, 0, 0 }, 11992 { "min", ICLASS_xt_iclass_minmax, 11993 0, 11994 Opcode_min_encode_fns, 0, 0 }, 11995 { "max", ICLASS_xt_iclass_minmax, 11996 0, 11997 Opcode_max_encode_fns, 0, 0 }, 11998 { "minu", ICLASS_xt_iclass_minmax, 11999 0, 12000 Opcode_minu_encode_fns, 0, 0 }, 12001 { "maxu", ICLASS_xt_iclass_minmax, 12002 0, 12003 Opcode_maxu_encode_fns, 0, 0 }, 12004 { "nsa", ICLASS_xt_iclass_nsa, 12005 0, 12006 Opcode_nsa_encode_fns, 0, 0 }, 12007 { "nsau", ICLASS_xt_iclass_nsa, 12008 0, 12009 Opcode_nsau_encode_fns, 0, 0 }, 12010 { "sext", ICLASS_xt_iclass_sx, 12011 0, 12012 Opcode_sext_encode_fns, 0, 0 }, 12013 { "l32ai", ICLASS_xt_iclass_l32ai, 12014 0, 12015 Opcode_l32ai_encode_fns, 0, 0 }, 12016 { "s32ri", ICLASS_xt_iclass_s32ri, 12017 0, 12018 Opcode_s32ri_encode_fns, 0, 0 }, 12019 { "s32c1i", ICLASS_xt_iclass_s32c1i, 12020 0, 12021 Opcode_s32c1i_encode_fns, 0, 0 }, 12022 { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, 12023 0, 12024 Opcode_rsr_scompare1_encode_fns, 0, 0 }, 12025 { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, 12026 0, 12027 Opcode_wsr_scompare1_encode_fns, 0, 0 }, 12028 { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, 12029 0, 12030 Opcode_xsr_scompare1_encode_fns, 0, 0 }, 12031 { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, 12032 0, 12033 Opcode_rsr_atomctl_encode_fns, 0, 0 }, 12034 { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, 12035 0, 12036 Opcode_wsr_atomctl_encode_fns, 0, 0 }, 12037 { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, 12038 0, 12039 Opcode_xsr_atomctl_encode_fns, 0, 0 }, 12040 { "quou", ICLASS_xt_iclass_div, 12041 0, 12042 Opcode_quou_encode_fns, 0, 0 }, 12043 { "quos", ICLASS_xt_iclass_div, 12044 0, 12045 Opcode_quos_encode_fns, 0, 0 }, 12046 { "remu", ICLASS_xt_iclass_div, 12047 0, 12048 Opcode_remu_encode_fns, 0, 0 }, 12049 { "rems", ICLASS_xt_iclass_div, 12050 0, 12051 Opcode_rems_encode_fns, 0, 0 }, 12052 { "rer", ICLASS_xt_iclass_rer, 12053 0, 12054 Opcode_rer_encode_fns, 0, 0 }, 12055 { "wer", ICLASS_xt_iclass_wer, 12056 0, 12057 Opcode_wer_encode_fns, 0, 0 }, 12058 { "rur.expstate", ICLASS_rur_expstate, 12059 0, 12060 Opcode_rur_expstate_encode_fns, 0, 0 }, 12061 { "wur.expstate", ICLASS_wur_expstate, 12062 0, 12063 Opcode_wur_expstate_encode_fns, 0, 0 }, 12064 { "read_impwire", ICLASS_iclass_READ_IMPWIRE, 12065 0, 12066 Opcode_read_impwire_encode_fns, 0, 0 }, 12067 { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, 12068 0, 12069 Opcode_setb_expstate_encode_fns, 0, 0 }, 12070 { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, 12071 0, 12072 Opcode_clrb_expstate_encode_fns, 0, 0 }, 12073 { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, 12074 0, 12075 Opcode_wrmsk_expstate_encode_fns, 0, 0 } 12076}; 12077 12078enum xtensa_opcode_id { 12079 OPCODE_EXCW, 12080 OPCODE_RFE, 12081 OPCODE_RFDE, 12082 OPCODE_SYSCALL, 12083 OPCODE_CALL12, 12084 OPCODE_CALL8, 12085 OPCODE_CALL4, 12086 OPCODE_CALLX12, 12087 OPCODE_CALLX8, 12088 OPCODE_CALLX4, 12089 OPCODE_ENTRY, 12090 OPCODE_MOVSP, 12091 OPCODE_ROTW, 12092 OPCODE_RETW, 12093 OPCODE_RETW_N, 12094 OPCODE_RFWO, 12095 OPCODE_RFWU, 12096 OPCODE_L32E, 12097 OPCODE_S32E, 12098 OPCODE_RSR_WINDOWBASE, 12099 OPCODE_WSR_WINDOWBASE, 12100 OPCODE_XSR_WINDOWBASE, 12101 OPCODE_RSR_WINDOWSTART, 12102 OPCODE_WSR_WINDOWSTART, 12103 OPCODE_XSR_WINDOWSTART, 12104 OPCODE_ADD_N, 12105 OPCODE_ADDI_N, 12106 OPCODE_BEQZ_N, 12107 OPCODE_BNEZ_N, 12108 OPCODE_ILL_N, 12109 OPCODE_L32I_N, 12110 OPCODE_MOV_N, 12111 OPCODE_MOVI_N, 12112 OPCODE_NOP_N, 12113 OPCODE_RET_N, 12114 OPCODE_S32I_N, 12115 OPCODE_ADDI, 12116 OPCODE_ADDMI, 12117 OPCODE_ADD, 12118 OPCODE_SUB, 12119 OPCODE_ADDX2, 12120 OPCODE_ADDX4, 12121 OPCODE_ADDX8, 12122 OPCODE_SUBX2, 12123 OPCODE_SUBX4, 12124 OPCODE_SUBX8, 12125 OPCODE_AND, 12126 OPCODE_OR, 12127 OPCODE_XOR, 12128 OPCODE_BEQI, 12129 OPCODE_BNEI, 12130 OPCODE_BGEI, 12131 OPCODE_BLTI, 12132 OPCODE_BBCI, 12133 OPCODE_BBSI, 12134 OPCODE_BGEUI, 12135 OPCODE_BLTUI, 12136 OPCODE_BEQ, 12137 OPCODE_BNE, 12138 OPCODE_BGE, 12139 OPCODE_BLT, 12140 OPCODE_BGEU, 12141 OPCODE_BLTU, 12142 OPCODE_BANY, 12143 OPCODE_BNONE, 12144 OPCODE_BALL, 12145 OPCODE_BNALL, 12146 OPCODE_BBC, 12147 OPCODE_BBS, 12148 OPCODE_BEQZ, 12149 OPCODE_BNEZ, 12150 OPCODE_BGEZ, 12151 OPCODE_BLTZ, 12152 OPCODE_CALL0, 12153 OPCODE_CALLX0, 12154 OPCODE_EXTUI, 12155 OPCODE_ILL, 12156 OPCODE_J, 12157 OPCODE_JX, 12158 OPCODE_L16UI, 12159 OPCODE_L16SI, 12160 OPCODE_L32I, 12161 OPCODE_L32R, 12162 OPCODE_L8UI, 12163 OPCODE_LOOP, 12164 OPCODE_LOOPNEZ, 12165 OPCODE_LOOPGTZ, 12166 OPCODE_MOVI, 12167 OPCODE_MOVEQZ, 12168 OPCODE_MOVNEZ, 12169 OPCODE_MOVLTZ, 12170 OPCODE_MOVGEZ, 12171 OPCODE_NEG, 12172 OPCODE_ABS, 12173 OPCODE_NOP, 12174 OPCODE_RET, 12175 OPCODE_SIMCALL, 12176 OPCODE_S16I, 12177 OPCODE_S32I, 12178 OPCODE_S32NB, 12179 OPCODE_S8I, 12180 OPCODE_SSR, 12181 OPCODE_SSL, 12182 OPCODE_SSA8L, 12183 OPCODE_SSA8B, 12184 OPCODE_SSAI, 12185 OPCODE_SLL, 12186 OPCODE_SRC, 12187 OPCODE_SRL, 12188 OPCODE_SRA, 12189 OPCODE_SLLI, 12190 OPCODE_SRAI, 12191 OPCODE_SRLI, 12192 OPCODE_MEMW, 12193 OPCODE_EXTW, 12194 OPCODE_ISYNC, 12195 OPCODE_RSYNC, 12196 OPCODE_ESYNC, 12197 OPCODE_DSYNC, 12198 OPCODE_RSIL, 12199 OPCODE_RSR_LEND, 12200 OPCODE_WSR_LEND, 12201 OPCODE_XSR_LEND, 12202 OPCODE_RSR_LCOUNT, 12203 OPCODE_WSR_LCOUNT, 12204 OPCODE_XSR_LCOUNT, 12205 OPCODE_RSR_LBEG, 12206 OPCODE_WSR_LBEG, 12207 OPCODE_XSR_LBEG, 12208 OPCODE_RSR_SAR, 12209 OPCODE_WSR_SAR, 12210 OPCODE_XSR_SAR, 12211 OPCODE_RSR_MEMCTL, 12212 OPCODE_WSR_MEMCTL, 12213 OPCODE_XSR_MEMCTL, 12214 OPCODE_RSR_LITBASE, 12215 OPCODE_WSR_LITBASE, 12216 OPCODE_XSR_LITBASE, 12217 OPCODE_RSR_CONFIGID0, 12218 OPCODE_WSR_CONFIGID0, 12219 OPCODE_RSR_CONFIGID1, 12220 OPCODE_RSR_PS, 12221 OPCODE_WSR_PS, 12222 OPCODE_XSR_PS, 12223 OPCODE_RSR_EPC1, 12224 OPCODE_WSR_EPC1, 12225 OPCODE_XSR_EPC1, 12226 OPCODE_RSR_EXCSAVE1, 12227 OPCODE_WSR_EXCSAVE1, 12228 OPCODE_XSR_EXCSAVE1, 12229 OPCODE_RSR_EPC2, 12230 OPCODE_WSR_EPC2, 12231 OPCODE_XSR_EPC2, 12232 OPCODE_RSR_EXCSAVE2, 12233 OPCODE_WSR_EXCSAVE2, 12234 OPCODE_XSR_EXCSAVE2, 12235 OPCODE_RSR_EPC3, 12236 OPCODE_WSR_EPC3, 12237 OPCODE_XSR_EPC3, 12238 OPCODE_RSR_EXCSAVE3, 12239 OPCODE_WSR_EXCSAVE3, 12240 OPCODE_XSR_EXCSAVE3, 12241 OPCODE_RSR_EPC4, 12242 OPCODE_WSR_EPC4, 12243 OPCODE_XSR_EPC4, 12244 OPCODE_RSR_EXCSAVE4, 12245 OPCODE_WSR_EXCSAVE4, 12246 OPCODE_XSR_EXCSAVE4, 12247 OPCODE_RSR_EPC5, 12248 OPCODE_WSR_EPC5, 12249 OPCODE_XSR_EPC5, 12250 OPCODE_RSR_EXCSAVE5, 12251 OPCODE_WSR_EXCSAVE5, 12252 OPCODE_XSR_EXCSAVE5, 12253 OPCODE_RSR_EPC6, 12254 OPCODE_WSR_EPC6, 12255 OPCODE_XSR_EPC6, 12256 OPCODE_RSR_EXCSAVE6, 12257 OPCODE_WSR_EXCSAVE6, 12258 OPCODE_XSR_EXCSAVE6, 12259 OPCODE_RSR_EPC7, 12260 OPCODE_WSR_EPC7, 12261 OPCODE_XSR_EPC7, 12262 OPCODE_RSR_EXCSAVE7, 12263 OPCODE_WSR_EXCSAVE7, 12264 OPCODE_XSR_EXCSAVE7, 12265 OPCODE_RSR_EPS2, 12266 OPCODE_WSR_EPS2, 12267 OPCODE_XSR_EPS2, 12268 OPCODE_RSR_EPS3, 12269 OPCODE_WSR_EPS3, 12270 OPCODE_XSR_EPS3, 12271 OPCODE_RSR_EPS4, 12272 OPCODE_WSR_EPS4, 12273 OPCODE_XSR_EPS4, 12274 OPCODE_RSR_EPS5, 12275 OPCODE_WSR_EPS5, 12276 OPCODE_XSR_EPS5, 12277 OPCODE_RSR_EPS6, 12278 OPCODE_WSR_EPS6, 12279 OPCODE_XSR_EPS6, 12280 OPCODE_RSR_EPS7, 12281 OPCODE_WSR_EPS7, 12282 OPCODE_XSR_EPS7, 12283 OPCODE_RSR_EXCVADDR, 12284 OPCODE_WSR_EXCVADDR, 12285 OPCODE_XSR_EXCVADDR, 12286 OPCODE_RSR_DEPC, 12287 OPCODE_WSR_DEPC, 12288 OPCODE_XSR_DEPC, 12289 OPCODE_RSR_EXCCAUSE, 12290 OPCODE_WSR_EXCCAUSE, 12291 OPCODE_XSR_EXCCAUSE, 12292 OPCODE_RSR_MISC0, 12293 OPCODE_WSR_MISC0, 12294 OPCODE_XSR_MISC0, 12295 OPCODE_RSR_MISC1, 12296 OPCODE_WSR_MISC1, 12297 OPCODE_XSR_MISC1, 12298 OPCODE_RSR_PRID, 12299 OPCODE_RSR_VECBASE, 12300 OPCODE_WSR_VECBASE, 12301 OPCODE_XSR_VECBASE, 12302 OPCODE_MUL16U, 12303 OPCODE_MUL16S, 12304 OPCODE_MULL, 12305 OPCODE_MUL_AA_LL, 12306 OPCODE_MUL_AA_HL, 12307 OPCODE_MUL_AA_LH, 12308 OPCODE_MUL_AA_HH, 12309 OPCODE_UMUL_AA_LL, 12310 OPCODE_UMUL_AA_HL, 12311 OPCODE_UMUL_AA_LH, 12312 OPCODE_UMUL_AA_HH, 12313 OPCODE_MUL_AD_LL, 12314 OPCODE_MUL_AD_HL, 12315 OPCODE_MUL_AD_LH, 12316 OPCODE_MUL_AD_HH, 12317 OPCODE_MUL_DA_LL, 12318 OPCODE_MUL_DA_HL, 12319 OPCODE_MUL_DA_LH, 12320 OPCODE_MUL_DA_HH, 12321 OPCODE_MUL_DD_LL, 12322 OPCODE_MUL_DD_HL, 12323 OPCODE_MUL_DD_LH, 12324 OPCODE_MUL_DD_HH, 12325 OPCODE_MULA_AA_LL, 12326 OPCODE_MULA_AA_HL, 12327 OPCODE_MULA_AA_LH, 12328 OPCODE_MULA_AA_HH, 12329 OPCODE_MULS_AA_LL, 12330 OPCODE_MULS_AA_HL, 12331 OPCODE_MULS_AA_LH, 12332 OPCODE_MULS_AA_HH, 12333 OPCODE_MULA_AD_LL, 12334 OPCODE_MULA_AD_HL, 12335 OPCODE_MULA_AD_LH, 12336 OPCODE_MULA_AD_HH, 12337 OPCODE_MULS_AD_LL, 12338 OPCODE_MULS_AD_HL, 12339 OPCODE_MULS_AD_LH, 12340 OPCODE_MULS_AD_HH, 12341 OPCODE_MULA_DA_LL, 12342 OPCODE_MULA_DA_HL, 12343 OPCODE_MULA_DA_LH, 12344 OPCODE_MULA_DA_HH, 12345 OPCODE_MULS_DA_LL, 12346 OPCODE_MULS_DA_HL, 12347 OPCODE_MULS_DA_LH, 12348 OPCODE_MULS_DA_HH, 12349 OPCODE_MULA_DD_LL, 12350 OPCODE_MULA_DD_HL, 12351 OPCODE_MULA_DD_LH, 12352 OPCODE_MULA_DD_HH, 12353 OPCODE_MULS_DD_LL, 12354 OPCODE_MULS_DD_HL, 12355 OPCODE_MULS_DD_LH, 12356 OPCODE_MULS_DD_HH, 12357 OPCODE_MULA_DA_LL_LDDEC, 12358 OPCODE_MULA_DA_LL_LDINC, 12359 OPCODE_MULA_DA_HL_LDDEC, 12360 OPCODE_MULA_DA_HL_LDINC, 12361 OPCODE_MULA_DA_LH_LDDEC, 12362 OPCODE_MULA_DA_LH_LDINC, 12363 OPCODE_MULA_DA_HH_LDDEC, 12364 OPCODE_MULA_DA_HH_LDINC, 12365 OPCODE_MULA_DD_LL_LDDEC, 12366 OPCODE_MULA_DD_LL_LDINC, 12367 OPCODE_MULA_DD_HL_LDDEC, 12368 OPCODE_MULA_DD_HL_LDINC, 12369 OPCODE_MULA_DD_LH_LDDEC, 12370 OPCODE_MULA_DD_LH_LDINC, 12371 OPCODE_MULA_DD_HH_LDDEC, 12372 OPCODE_MULA_DD_HH_LDINC, 12373 OPCODE_LDDEC, 12374 OPCODE_LDINC, 12375 OPCODE_RSR_M0, 12376 OPCODE_WSR_M0, 12377 OPCODE_XSR_M0, 12378 OPCODE_RSR_M1, 12379 OPCODE_WSR_M1, 12380 OPCODE_XSR_M1, 12381 OPCODE_RSR_M2, 12382 OPCODE_WSR_M2, 12383 OPCODE_XSR_M2, 12384 OPCODE_RSR_M3, 12385 OPCODE_WSR_M3, 12386 OPCODE_XSR_M3, 12387 OPCODE_RSR_ACCLO, 12388 OPCODE_WSR_ACCLO, 12389 OPCODE_XSR_ACCLO, 12390 OPCODE_RSR_ACCHI, 12391 OPCODE_WSR_ACCHI, 12392 OPCODE_XSR_ACCHI, 12393 OPCODE_RFI, 12394 OPCODE_WAITI, 12395 OPCODE_RSR_INTERRUPT, 12396 OPCODE_WSR_INTSET, 12397 OPCODE_WSR_INTCLEAR, 12398 OPCODE_RSR_INTENABLE, 12399 OPCODE_WSR_INTENABLE, 12400 OPCODE_XSR_INTENABLE, 12401 OPCODE_BREAK, 12402 OPCODE_BREAK_N, 12403 OPCODE_RSR_DBREAKA0, 12404 OPCODE_WSR_DBREAKA0, 12405 OPCODE_XSR_DBREAKA0, 12406 OPCODE_RSR_DBREAKC0, 12407 OPCODE_WSR_DBREAKC0, 12408 OPCODE_XSR_DBREAKC0, 12409 OPCODE_RSR_DBREAKA1, 12410 OPCODE_WSR_DBREAKA1, 12411 OPCODE_XSR_DBREAKA1, 12412 OPCODE_RSR_DBREAKC1, 12413 OPCODE_WSR_DBREAKC1, 12414 OPCODE_XSR_DBREAKC1, 12415 OPCODE_RSR_IBREAKA0, 12416 OPCODE_WSR_IBREAKA0, 12417 OPCODE_XSR_IBREAKA0, 12418 OPCODE_RSR_IBREAKA1, 12419 OPCODE_WSR_IBREAKA1, 12420 OPCODE_XSR_IBREAKA1, 12421 OPCODE_RSR_IBREAKENABLE, 12422 OPCODE_WSR_IBREAKENABLE, 12423 OPCODE_XSR_IBREAKENABLE, 12424 OPCODE_RSR_DEBUGCAUSE, 12425 OPCODE_WSR_DEBUGCAUSE, 12426 OPCODE_XSR_DEBUGCAUSE, 12427 OPCODE_RSR_ICOUNT, 12428 OPCODE_WSR_ICOUNT, 12429 OPCODE_XSR_ICOUNT, 12430 OPCODE_RSR_ICOUNTLEVEL, 12431 OPCODE_WSR_ICOUNTLEVEL, 12432 OPCODE_XSR_ICOUNTLEVEL, 12433 OPCODE_RSR_DDR, 12434 OPCODE_WSR_DDR, 12435 OPCODE_XSR_DDR, 12436 OPCODE_LDDR32_P, 12437 OPCODE_SDDR32_P, 12438 OPCODE_RFDO, 12439 OPCODE_RFDD, 12440 OPCODE_WSR_MMID, 12441 OPCODE_RSR_CCOUNT, 12442 OPCODE_WSR_CCOUNT, 12443 OPCODE_XSR_CCOUNT, 12444 OPCODE_RSR_CCOMPARE0, 12445 OPCODE_WSR_CCOMPARE0, 12446 OPCODE_XSR_CCOMPARE0, 12447 OPCODE_RSR_CCOMPARE1, 12448 OPCODE_WSR_CCOMPARE1, 12449 OPCODE_XSR_CCOMPARE1, 12450 OPCODE_RSR_CCOMPARE2, 12451 OPCODE_WSR_CCOMPARE2, 12452 OPCODE_XSR_CCOMPARE2, 12453 OPCODE_IPF, 12454 OPCODE_IHI, 12455 OPCODE_IPFL, 12456 OPCODE_IHU, 12457 OPCODE_IIU, 12458 OPCODE_III, 12459 OPCODE_LICT, 12460 OPCODE_LICW, 12461 OPCODE_SICT, 12462 OPCODE_SICW, 12463 OPCODE_DHWB, 12464 OPCODE_DHWBI, 12465 OPCODE_DIWBUI_P, 12466 OPCODE_DIWB, 12467 OPCODE_DIWBI, 12468 OPCODE_DHI, 12469 OPCODE_DII, 12470 OPCODE_DPFR, 12471 OPCODE_DPFW, 12472 OPCODE_DPFRO, 12473 OPCODE_DPFWO, 12474 OPCODE_DPFL, 12475 OPCODE_DHU, 12476 OPCODE_DIU, 12477 OPCODE_SDCT, 12478 OPCODE_LDCT, 12479 OPCODE_IDTLB, 12480 OPCODE_PDTLB, 12481 OPCODE_RDTLB0, 12482 OPCODE_RDTLB1, 12483 OPCODE_WDTLB, 12484 OPCODE_IITLB, 12485 OPCODE_PITLB, 12486 OPCODE_RITLB0, 12487 OPCODE_RITLB1, 12488 OPCODE_WITLB, 12489 OPCODE_CLAMPS, 12490 OPCODE_MIN, 12491 OPCODE_MAX, 12492 OPCODE_MINU, 12493 OPCODE_MAXU, 12494 OPCODE_NSA, 12495 OPCODE_NSAU, 12496 OPCODE_SEXT, 12497 OPCODE_L32AI, 12498 OPCODE_S32RI, 12499 OPCODE_S32C1I, 12500 OPCODE_RSR_SCOMPARE1, 12501 OPCODE_WSR_SCOMPARE1, 12502 OPCODE_XSR_SCOMPARE1, 12503 OPCODE_RSR_ATOMCTL, 12504 OPCODE_WSR_ATOMCTL, 12505 OPCODE_XSR_ATOMCTL, 12506 OPCODE_QUOU, 12507 OPCODE_QUOS, 12508 OPCODE_REMU, 12509 OPCODE_REMS, 12510 OPCODE_RER, 12511 OPCODE_WER, 12512 OPCODE_RUR_EXPSTATE, 12513 OPCODE_WUR_EXPSTATE, 12514 OPCODE_READ_IMPWIRE, 12515 OPCODE_SETB_EXPSTATE, 12516 OPCODE_CLRB_EXPSTATE, 12517 OPCODE_WRMSK_EXPSTATE 12518}; 12519 12520 12521/* Slot-specific opcode decode functions. */ 12522 12523static int 12524Slot_inst_decode (const xtensa_insnbuf insn) 12525{ 12526 if (Field_op0_Slot_inst_get (insn) == 0) 12527 { 12528 if (Field_op1_Slot_inst_get (insn) == 0) 12529 { 12530 if (Field_op2_Slot_inst_get (insn) == 0) 12531 { 12532 if (Field_r_Slot_inst_get (insn) == 0) 12533 { 12534 if (Field_m_Slot_inst_get (insn) == 0 && 12535 Field_s_Slot_inst_get (insn) == 0 && 12536 Field_n_Slot_inst_get (insn) == 0) 12537 return OPCODE_ILL; 12538 if (Field_m_Slot_inst_get (insn) == 2) 12539 { 12540 if (Field_n_Slot_inst_get (insn) == 0) 12541 return OPCODE_RET; 12542 if (Field_n_Slot_inst_get (insn) == 1) 12543 return OPCODE_RETW; 12544 if (Field_n_Slot_inst_get (insn) == 2) 12545 return OPCODE_JX; 12546 } 12547 if (Field_m_Slot_inst_get (insn) == 3) 12548 { 12549 if (Field_n_Slot_inst_get (insn) == 0) 12550 return OPCODE_CALLX0; 12551 if (Field_n_Slot_inst_get (insn) == 1) 12552 return OPCODE_CALLX4; 12553 if (Field_n_Slot_inst_get (insn) == 2) 12554 return OPCODE_CALLX8; 12555 if (Field_n_Slot_inst_get (insn) == 3) 12556 return OPCODE_CALLX12; 12557 } 12558 } 12559 if (Field_r_Slot_inst_get (insn) == 1) 12560 return OPCODE_MOVSP; 12561 if (Field_r_Slot_inst_get (insn) == 2) 12562 { 12563 if (Field_s_Slot_inst_get (insn) == 0) 12564 { 12565 if (Field_t_Slot_inst_get (insn) == 0) 12566 return OPCODE_ISYNC; 12567 if (Field_t_Slot_inst_get (insn) == 1) 12568 return OPCODE_RSYNC; 12569 if (Field_t_Slot_inst_get (insn) == 2) 12570 return OPCODE_ESYNC; 12571 if (Field_t_Slot_inst_get (insn) == 3) 12572 return OPCODE_DSYNC; 12573 if (Field_t_Slot_inst_get (insn) == 8) 12574 return OPCODE_EXCW; 12575 if (Field_t_Slot_inst_get (insn) == 12) 12576 return OPCODE_MEMW; 12577 if (Field_t_Slot_inst_get (insn) == 13) 12578 return OPCODE_EXTW; 12579 if (Field_t_Slot_inst_get (insn) == 15) 12580 return OPCODE_NOP; 12581 } 12582 } 12583 if (Field_r_Slot_inst_get (insn) == 3) 12584 { 12585 if (Field_t_Slot_inst_get (insn) == 0) 12586 { 12587 if (Field_s_Slot_inst_get (insn) == 0) 12588 return OPCODE_RFE; 12589 if (Field_s_Slot_inst_get (insn) == 2) 12590 return OPCODE_RFDE; 12591 if (Field_s_Slot_inst_get (insn) == 4) 12592 return OPCODE_RFWO; 12593 if (Field_s_Slot_inst_get (insn) == 5) 12594 return OPCODE_RFWU; 12595 } 12596 if (Field_t_Slot_inst_get (insn) == 1) 12597 return OPCODE_RFI; 12598 } 12599 if (Field_r_Slot_inst_get (insn) == 4) 12600 return OPCODE_BREAK; 12601 if (Field_r_Slot_inst_get (insn) == 5) 12602 { 12603 if (Field_s_Slot_inst_get (insn) == 0 && 12604 Field_t_Slot_inst_get (insn) == 0) 12605 return OPCODE_SYSCALL; 12606 if (Field_s_Slot_inst_get (insn) == 1 && 12607 Field_t_Slot_inst_get (insn) == 0) 12608 return OPCODE_SIMCALL; 12609 } 12610 if (Field_r_Slot_inst_get (insn) == 6) 12611 return OPCODE_RSIL; 12612 if (Field_r_Slot_inst_get (insn) == 7 && 12613 Field_t_Slot_inst_get (insn) == 0) 12614 return OPCODE_WAITI; 12615 if (Field_r_Slot_inst_get (insn) == 7) 12616 { 12617 if (Field_t_Slot_inst_get (insn) == 14) 12618 return OPCODE_LDDR32_P; 12619 if (Field_t_Slot_inst_get (insn) == 15) 12620 return OPCODE_SDDR32_P; 12621 } 12622 } 12623 if (Field_op2_Slot_inst_get (insn) == 1) 12624 return OPCODE_AND; 12625 if (Field_op2_Slot_inst_get (insn) == 2) 12626 return OPCODE_OR; 12627 if (Field_op2_Slot_inst_get (insn) == 3) 12628 return OPCODE_XOR; 12629 if (Field_op2_Slot_inst_get (insn) == 4) 12630 { 12631 if (Field_r_Slot_inst_get (insn) == 0 && 12632 Field_t_Slot_inst_get (insn) == 0) 12633 return OPCODE_SSR; 12634 if (Field_r_Slot_inst_get (insn) == 1 && 12635 Field_t_Slot_inst_get (insn) == 0) 12636 return OPCODE_SSL; 12637 if (Field_r_Slot_inst_get (insn) == 2 && 12638 Field_t_Slot_inst_get (insn) == 0) 12639 return OPCODE_SSA8L; 12640 if (Field_r_Slot_inst_get (insn) == 3 && 12641 Field_t_Slot_inst_get (insn) == 0) 12642 return OPCODE_SSA8B; 12643 if (Field_r_Slot_inst_get (insn) == 4 && 12644 Field_thi3_Slot_inst_get (insn) == 0) 12645 return OPCODE_SSAI; 12646 if (Field_r_Slot_inst_get (insn) == 6) 12647 return OPCODE_RER; 12648 if (Field_r_Slot_inst_get (insn) == 7) 12649 return OPCODE_WER; 12650 if (Field_r_Slot_inst_get (insn) == 8 && 12651 Field_s_Slot_inst_get (insn) == 0) 12652 return OPCODE_ROTW; 12653 if (Field_r_Slot_inst_get (insn) == 14) 12654 return OPCODE_NSA; 12655 if (Field_r_Slot_inst_get (insn) == 15) 12656 return OPCODE_NSAU; 12657 } 12658 if (Field_op2_Slot_inst_get (insn) == 5) 12659 { 12660 if (Field_r_Slot_inst_get (insn) == 3) 12661 return OPCODE_RITLB0; 12662 if (Field_r_Slot_inst_get (insn) == 4 && 12663 Field_t_Slot_inst_get (insn) == 0) 12664 return OPCODE_IITLB; 12665 if (Field_r_Slot_inst_get (insn) == 5) 12666 return OPCODE_PITLB; 12667 if (Field_r_Slot_inst_get (insn) == 6) 12668 return OPCODE_WITLB; 12669 if (Field_r_Slot_inst_get (insn) == 7) 12670 return OPCODE_RITLB1; 12671 if (Field_r_Slot_inst_get (insn) == 11) 12672 return OPCODE_RDTLB0; 12673 if (Field_r_Slot_inst_get (insn) == 12 && 12674 Field_t_Slot_inst_get (insn) == 0) 12675 return OPCODE_IDTLB; 12676 if (Field_r_Slot_inst_get (insn) == 13) 12677 return OPCODE_PDTLB; 12678 if (Field_r_Slot_inst_get (insn) == 14) 12679 return OPCODE_WDTLB; 12680 if (Field_r_Slot_inst_get (insn) == 15) 12681 return OPCODE_RDTLB1; 12682 } 12683 if (Field_op2_Slot_inst_get (insn) == 6) 12684 { 12685 if (Field_s_Slot_inst_get (insn) == 0) 12686 return OPCODE_NEG; 12687 if (Field_s_Slot_inst_get (insn) == 1) 12688 return OPCODE_ABS; 12689 } 12690 if (Field_op2_Slot_inst_get (insn) == 8) 12691 return OPCODE_ADD; 12692 if (Field_op2_Slot_inst_get (insn) == 9) 12693 return OPCODE_ADDX2; 12694 if (Field_op2_Slot_inst_get (insn) == 10) 12695 return OPCODE_ADDX4; 12696 if (Field_op2_Slot_inst_get (insn) == 11) 12697 return OPCODE_ADDX8; 12698 if (Field_op2_Slot_inst_get (insn) == 12) 12699 return OPCODE_SUB; 12700 if (Field_op2_Slot_inst_get (insn) == 13) 12701 return OPCODE_SUBX2; 12702 if (Field_op2_Slot_inst_get (insn) == 14) 12703 return OPCODE_SUBX4; 12704 if (Field_op2_Slot_inst_get (insn) == 15) 12705 return OPCODE_SUBX8; 12706 } 12707 if (Field_op1_Slot_inst_get (insn) == 1) 12708 { 12709 if ((Field_op2_Slot_inst_get (insn) == 0 || 12710 Field_op2_Slot_inst_get (insn) == 1)) 12711 return OPCODE_SLLI; 12712 if ((Field_op2_Slot_inst_get (insn) == 2 || 12713 Field_op2_Slot_inst_get (insn) == 3)) 12714 return OPCODE_SRAI; 12715 if (Field_op2_Slot_inst_get (insn) == 4) 12716 return OPCODE_SRLI; 12717 if (Field_op2_Slot_inst_get (insn) == 6) 12718 { 12719 if (Field_sr_Slot_inst_get (insn) == 0) 12720 return OPCODE_XSR_LBEG; 12721 if (Field_sr_Slot_inst_get (insn) == 1) 12722 return OPCODE_XSR_LEND; 12723 if (Field_sr_Slot_inst_get (insn) == 2) 12724 return OPCODE_XSR_LCOUNT; 12725 if (Field_sr_Slot_inst_get (insn) == 3) 12726 return OPCODE_XSR_SAR; 12727 if (Field_sr_Slot_inst_get (insn) == 5) 12728 return OPCODE_XSR_LITBASE; 12729 if (Field_sr_Slot_inst_get (insn) == 12) 12730 return OPCODE_XSR_SCOMPARE1; 12731 if (Field_sr_Slot_inst_get (insn) == 16) 12732 return OPCODE_XSR_ACCLO; 12733 if (Field_sr_Slot_inst_get (insn) == 17) 12734 return OPCODE_XSR_ACCHI; 12735 if (Field_sr_Slot_inst_get (insn) == 32) 12736 return OPCODE_XSR_M0; 12737 if (Field_sr_Slot_inst_get (insn) == 33) 12738 return OPCODE_XSR_M1; 12739 if (Field_sr_Slot_inst_get (insn) == 34) 12740 return OPCODE_XSR_M2; 12741 if (Field_sr_Slot_inst_get (insn) == 35) 12742 return OPCODE_XSR_M3; 12743 if (Field_sr_Slot_inst_get (insn) == 72) 12744 return OPCODE_XSR_WINDOWBASE; 12745 if (Field_sr_Slot_inst_get (insn) == 73) 12746 return OPCODE_XSR_WINDOWSTART; 12747 if (Field_sr_Slot_inst_get (insn) == 96) 12748 return OPCODE_XSR_IBREAKENABLE; 12749 if (Field_sr_Slot_inst_get (insn) == 97) 12750 return OPCODE_XSR_MEMCTL; 12751 if (Field_sr_Slot_inst_get (insn) == 99) 12752 return OPCODE_XSR_ATOMCTL; 12753 if (Field_sr_Slot_inst_get (insn) == 104) 12754 return OPCODE_XSR_DDR; 12755 if (Field_sr_Slot_inst_get (insn) == 128) 12756 return OPCODE_XSR_IBREAKA0; 12757 if (Field_sr_Slot_inst_get (insn) == 129) 12758 return OPCODE_XSR_IBREAKA1; 12759 if (Field_sr_Slot_inst_get (insn) == 144) 12760 return OPCODE_XSR_DBREAKA0; 12761 if (Field_sr_Slot_inst_get (insn) == 145) 12762 return OPCODE_XSR_DBREAKA1; 12763 if (Field_sr_Slot_inst_get (insn) == 160) 12764 return OPCODE_XSR_DBREAKC0; 12765 if (Field_sr_Slot_inst_get (insn) == 161) 12766 return OPCODE_XSR_DBREAKC1; 12767 if (Field_sr_Slot_inst_get (insn) == 177) 12768 return OPCODE_XSR_EPC1; 12769 if (Field_sr_Slot_inst_get (insn) == 178) 12770 return OPCODE_XSR_EPC2; 12771 if (Field_sr_Slot_inst_get (insn) == 179) 12772 return OPCODE_XSR_EPC3; 12773 if (Field_sr_Slot_inst_get (insn) == 180) 12774 return OPCODE_XSR_EPC4; 12775 if (Field_sr_Slot_inst_get (insn) == 181) 12776 return OPCODE_XSR_EPC5; 12777 if (Field_sr_Slot_inst_get (insn) == 182) 12778 return OPCODE_XSR_EPC6; 12779 if (Field_sr_Slot_inst_get (insn) == 183) 12780 return OPCODE_XSR_EPC7; 12781 if (Field_sr_Slot_inst_get (insn) == 192) 12782 return OPCODE_XSR_DEPC; 12783 if (Field_sr_Slot_inst_get (insn) == 194) 12784 return OPCODE_XSR_EPS2; 12785 if (Field_sr_Slot_inst_get (insn) == 195) 12786 return OPCODE_XSR_EPS3; 12787 if (Field_sr_Slot_inst_get (insn) == 196) 12788 return OPCODE_XSR_EPS4; 12789 if (Field_sr_Slot_inst_get (insn) == 197) 12790 return OPCODE_XSR_EPS5; 12791 if (Field_sr_Slot_inst_get (insn) == 198) 12792 return OPCODE_XSR_EPS6; 12793 if (Field_sr_Slot_inst_get (insn) == 199) 12794 return OPCODE_XSR_EPS7; 12795 if (Field_sr_Slot_inst_get (insn) == 209) 12796 return OPCODE_XSR_EXCSAVE1; 12797 if (Field_sr_Slot_inst_get (insn) == 210) 12798 return OPCODE_XSR_EXCSAVE2; 12799 if (Field_sr_Slot_inst_get (insn) == 211) 12800 return OPCODE_XSR_EXCSAVE3; 12801 if (Field_sr_Slot_inst_get (insn) == 212) 12802 return OPCODE_XSR_EXCSAVE4; 12803 if (Field_sr_Slot_inst_get (insn) == 213) 12804 return OPCODE_XSR_EXCSAVE5; 12805 if (Field_sr_Slot_inst_get (insn) == 214) 12806 return OPCODE_XSR_EXCSAVE6; 12807 if (Field_sr_Slot_inst_get (insn) == 215) 12808 return OPCODE_XSR_EXCSAVE7; 12809 if (Field_sr_Slot_inst_get (insn) == 228) 12810 return OPCODE_XSR_INTENABLE; 12811 if (Field_sr_Slot_inst_get (insn) == 230) 12812 return OPCODE_XSR_PS; 12813 if (Field_sr_Slot_inst_get (insn) == 231) 12814 return OPCODE_XSR_VECBASE; 12815 if (Field_sr_Slot_inst_get (insn) == 232) 12816 return OPCODE_XSR_EXCCAUSE; 12817 if (Field_sr_Slot_inst_get (insn) == 233) 12818 return OPCODE_XSR_DEBUGCAUSE; 12819 if (Field_sr_Slot_inst_get (insn) == 234) 12820 return OPCODE_XSR_CCOUNT; 12821 if (Field_sr_Slot_inst_get (insn) == 236) 12822 return OPCODE_XSR_ICOUNT; 12823 if (Field_sr_Slot_inst_get (insn) == 237) 12824 return OPCODE_XSR_ICOUNTLEVEL; 12825 if (Field_sr_Slot_inst_get (insn) == 238) 12826 return OPCODE_XSR_EXCVADDR; 12827 if (Field_sr_Slot_inst_get (insn) == 240) 12828 return OPCODE_XSR_CCOMPARE0; 12829 if (Field_sr_Slot_inst_get (insn) == 241) 12830 return OPCODE_XSR_CCOMPARE1; 12831 if (Field_sr_Slot_inst_get (insn) == 242) 12832 return OPCODE_XSR_CCOMPARE2; 12833 if (Field_sr_Slot_inst_get (insn) == 244) 12834 return OPCODE_XSR_MISC0; 12835 if (Field_sr_Slot_inst_get (insn) == 245) 12836 return OPCODE_XSR_MISC1; 12837 } 12838 if (Field_op2_Slot_inst_get (insn) == 8) 12839 return OPCODE_SRC; 12840 if (Field_op2_Slot_inst_get (insn) == 9 && 12841 Field_s_Slot_inst_get (insn) == 0) 12842 return OPCODE_SRL; 12843 if (Field_op2_Slot_inst_get (insn) == 10 && 12844 Field_t_Slot_inst_get (insn) == 0) 12845 return OPCODE_SLL; 12846 if (Field_op2_Slot_inst_get (insn) == 11 && 12847 Field_s_Slot_inst_get (insn) == 0) 12848 return OPCODE_SRA; 12849 if (Field_op2_Slot_inst_get (insn) == 12) 12850 return OPCODE_MUL16U; 12851 if (Field_op2_Slot_inst_get (insn) == 13) 12852 return OPCODE_MUL16S; 12853 if (Field_op2_Slot_inst_get (insn) == 15) 12854 { 12855 if (Field_r_Slot_inst_get (insn) == 0) 12856 return OPCODE_LICT; 12857 if (Field_r_Slot_inst_get (insn) == 1) 12858 return OPCODE_SICT; 12859 if (Field_r_Slot_inst_get (insn) == 2) 12860 return OPCODE_LICW; 12861 if (Field_r_Slot_inst_get (insn) == 3) 12862 return OPCODE_SICW; 12863 if (Field_r_Slot_inst_get (insn) == 8) 12864 return OPCODE_LDCT; 12865 if (Field_r_Slot_inst_get (insn) == 9) 12866 return OPCODE_SDCT; 12867 if (Field_r_Slot_inst_get (insn) == 14 && 12868 Field_t_Slot_inst_get (insn) == 0) 12869 return OPCODE_RFDO; 12870 if (Field_r_Slot_inst_get (insn) == 14 && 12871 Field_t_Slot_inst_get (insn) == 1) 12872 return OPCODE_RFDD; 12873 } 12874 } 12875 if (Field_op1_Slot_inst_get (insn) == 2) 12876 { 12877 if (Field_op2_Slot_inst_get (insn) == 8) 12878 return OPCODE_MULL; 12879 if (Field_op2_Slot_inst_get (insn) == 12) 12880 return OPCODE_QUOU; 12881 if (Field_op2_Slot_inst_get (insn) == 13) 12882 return OPCODE_QUOS; 12883 if (Field_op2_Slot_inst_get (insn) == 14) 12884 return OPCODE_REMU; 12885 if (Field_op2_Slot_inst_get (insn) == 15) 12886 return OPCODE_REMS; 12887 } 12888 if (Field_op1_Slot_inst_get (insn) == 3) 12889 { 12890 if (Field_op2_Slot_inst_get (insn) == 0) 12891 { 12892 if (Field_sr_Slot_inst_get (insn) == 0) 12893 return OPCODE_RSR_LBEG; 12894 if (Field_sr_Slot_inst_get (insn) == 1) 12895 return OPCODE_RSR_LEND; 12896 if (Field_sr_Slot_inst_get (insn) == 2) 12897 return OPCODE_RSR_LCOUNT; 12898 if (Field_sr_Slot_inst_get (insn) == 3) 12899 return OPCODE_RSR_SAR; 12900 if (Field_sr_Slot_inst_get (insn) == 5) 12901 return OPCODE_RSR_LITBASE; 12902 if (Field_sr_Slot_inst_get (insn) == 12) 12903 return OPCODE_RSR_SCOMPARE1; 12904 if (Field_sr_Slot_inst_get (insn) == 16) 12905 return OPCODE_RSR_ACCLO; 12906 if (Field_sr_Slot_inst_get (insn) == 17) 12907 return OPCODE_RSR_ACCHI; 12908 if (Field_sr_Slot_inst_get (insn) == 32) 12909 return OPCODE_RSR_M0; 12910 if (Field_sr_Slot_inst_get (insn) == 33) 12911 return OPCODE_RSR_M1; 12912 if (Field_sr_Slot_inst_get (insn) == 34) 12913 return OPCODE_RSR_M2; 12914 if (Field_sr_Slot_inst_get (insn) == 35) 12915 return OPCODE_RSR_M3; 12916 if (Field_sr_Slot_inst_get (insn) == 72) 12917 return OPCODE_RSR_WINDOWBASE; 12918 if (Field_sr_Slot_inst_get (insn) == 73) 12919 return OPCODE_RSR_WINDOWSTART; 12920 if (Field_sr_Slot_inst_get (insn) == 96) 12921 return OPCODE_RSR_IBREAKENABLE; 12922 if (Field_sr_Slot_inst_get (insn) == 97) 12923 return OPCODE_RSR_MEMCTL; 12924 if (Field_sr_Slot_inst_get (insn) == 99) 12925 return OPCODE_RSR_ATOMCTL; 12926 if (Field_sr_Slot_inst_get (insn) == 104) 12927 return OPCODE_RSR_DDR; 12928 if (Field_sr_Slot_inst_get (insn) == 128) 12929 return OPCODE_RSR_IBREAKA0; 12930 if (Field_sr_Slot_inst_get (insn) == 129) 12931 return OPCODE_RSR_IBREAKA1; 12932 if (Field_sr_Slot_inst_get (insn) == 144) 12933 return OPCODE_RSR_DBREAKA0; 12934 if (Field_sr_Slot_inst_get (insn) == 145) 12935 return OPCODE_RSR_DBREAKA1; 12936 if (Field_sr_Slot_inst_get (insn) == 160) 12937 return OPCODE_RSR_DBREAKC0; 12938 if (Field_sr_Slot_inst_get (insn) == 161) 12939 return OPCODE_RSR_DBREAKC1; 12940 if (Field_sr_Slot_inst_get (insn) == 176) 12941 return OPCODE_RSR_CONFIGID0; 12942 if (Field_sr_Slot_inst_get (insn) == 177) 12943 return OPCODE_RSR_EPC1; 12944 if (Field_sr_Slot_inst_get (insn) == 178) 12945 return OPCODE_RSR_EPC2; 12946 if (Field_sr_Slot_inst_get (insn) == 179) 12947 return OPCODE_RSR_EPC3; 12948 if (Field_sr_Slot_inst_get (insn) == 180) 12949 return OPCODE_RSR_EPC4; 12950 if (Field_sr_Slot_inst_get (insn) == 181) 12951 return OPCODE_RSR_EPC5; 12952 if (Field_sr_Slot_inst_get (insn) == 182) 12953 return OPCODE_RSR_EPC6; 12954 if (Field_sr_Slot_inst_get (insn) == 183) 12955 return OPCODE_RSR_EPC7; 12956 if (Field_sr_Slot_inst_get (insn) == 192) 12957 return OPCODE_RSR_DEPC; 12958 if (Field_sr_Slot_inst_get (insn) == 194) 12959 return OPCODE_RSR_EPS2; 12960 if (Field_sr_Slot_inst_get (insn) == 195) 12961 return OPCODE_RSR_EPS3; 12962 if (Field_sr_Slot_inst_get (insn) == 196) 12963 return OPCODE_RSR_EPS4; 12964 if (Field_sr_Slot_inst_get (insn) == 197) 12965 return OPCODE_RSR_EPS5; 12966 if (Field_sr_Slot_inst_get (insn) == 198) 12967 return OPCODE_RSR_EPS6; 12968 if (Field_sr_Slot_inst_get (insn) == 199) 12969 return OPCODE_RSR_EPS7; 12970 if (Field_sr_Slot_inst_get (insn) == 208) 12971 return OPCODE_RSR_CONFIGID1; 12972 if (Field_sr_Slot_inst_get (insn) == 209) 12973 return OPCODE_RSR_EXCSAVE1; 12974 if (Field_sr_Slot_inst_get (insn) == 210) 12975 return OPCODE_RSR_EXCSAVE2; 12976 if (Field_sr_Slot_inst_get (insn) == 211) 12977 return OPCODE_RSR_EXCSAVE3; 12978 if (Field_sr_Slot_inst_get (insn) == 212) 12979 return OPCODE_RSR_EXCSAVE4; 12980 if (Field_sr_Slot_inst_get (insn) == 213) 12981 return OPCODE_RSR_EXCSAVE5; 12982 if (Field_sr_Slot_inst_get (insn) == 214) 12983 return OPCODE_RSR_EXCSAVE6; 12984 if (Field_sr_Slot_inst_get (insn) == 215) 12985 return OPCODE_RSR_EXCSAVE7; 12986 if (Field_sr_Slot_inst_get (insn) == 226) 12987 return OPCODE_RSR_INTERRUPT; 12988 if (Field_sr_Slot_inst_get (insn) == 228) 12989 return OPCODE_RSR_INTENABLE; 12990 if (Field_sr_Slot_inst_get (insn) == 230) 12991 return OPCODE_RSR_PS; 12992 if (Field_sr_Slot_inst_get (insn) == 231) 12993 return OPCODE_RSR_VECBASE; 12994 if (Field_sr_Slot_inst_get (insn) == 232) 12995 return OPCODE_RSR_EXCCAUSE; 12996 if (Field_sr_Slot_inst_get (insn) == 233) 12997 return OPCODE_RSR_DEBUGCAUSE; 12998 if (Field_sr_Slot_inst_get (insn) == 234) 12999 return OPCODE_RSR_CCOUNT; 13000 if (Field_sr_Slot_inst_get (insn) == 235) 13001 return OPCODE_RSR_PRID; 13002 if (Field_sr_Slot_inst_get (insn) == 236) 13003 return OPCODE_RSR_ICOUNT; 13004 if (Field_sr_Slot_inst_get (insn) == 237) 13005 return OPCODE_RSR_ICOUNTLEVEL; 13006 if (Field_sr_Slot_inst_get (insn) == 238) 13007 return OPCODE_RSR_EXCVADDR; 13008 if (Field_sr_Slot_inst_get (insn) == 240) 13009 return OPCODE_RSR_CCOMPARE0; 13010 if (Field_sr_Slot_inst_get (insn) == 241) 13011 return OPCODE_RSR_CCOMPARE1; 13012 if (Field_sr_Slot_inst_get (insn) == 242) 13013 return OPCODE_RSR_CCOMPARE2; 13014 if (Field_sr_Slot_inst_get (insn) == 244) 13015 return OPCODE_RSR_MISC0; 13016 if (Field_sr_Slot_inst_get (insn) == 245) 13017 return OPCODE_RSR_MISC1; 13018 } 13019 if (Field_op2_Slot_inst_get (insn) == 1) 13020 { 13021 if (Field_sr_Slot_inst_get (insn) == 0) 13022 return OPCODE_WSR_LBEG; 13023 if (Field_sr_Slot_inst_get (insn) == 1) 13024 return OPCODE_WSR_LEND; 13025 if (Field_sr_Slot_inst_get (insn) == 2) 13026 return OPCODE_WSR_LCOUNT; 13027 if (Field_sr_Slot_inst_get (insn) == 3) 13028 return OPCODE_WSR_SAR; 13029 if (Field_sr_Slot_inst_get (insn) == 5) 13030 return OPCODE_WSR_LITBASE; 13031 if (Field_sr_Slot_inst_get (insn) == 12) 13032 return OPCODE_WSR_SCOMPARE1; 13033 if (Field_sr_Slot_inst_get (insn) == 16) 13034 return OPCODE_WSR_ACCLO; 13035 if (Field_sr_Slot_inst_get (insn) == 17) 13036 return OPCODE_WSR_ACCHI; 13037 if (Field_sr_Slot_inst_get (insn) == 32) 13038 return OPCODE_WSR_M0; 13039 if (Field_sr_Slot_inst_get (insn) == 33) 13040 return OPCODE_WSR_M1; 13041 if (Field_sr_Slot_inst_get (insn) == 34) 13042 return OPCODE_WSR_M2; 13043 if (Field_sr_Slot_inst_get (insn) == 35) 13044 return OPCODE_WSR_M3; 13045 if (Field_sr_Slot_inst_get (insn) == 72) 13046 return OPCODE_WSR_WINDOWBASE; 13047 if (Field_sr_Slot_inst_get (insn) == 73) 13048 return OPCODE_WSR_WINDOWSTART; 13049 if (Field_sr_Slot_inst_get (insn) == 89) 13050 return OPCODE_WSR_MMID; 13051 if (Field_sr_Slot_inst_get (insn) == 96) 13052 return OPCODE_WSR_IBREAKENABLE; 13053 if (Field_sr_Slot_inst_get (insn) == 97) 13054 return OPCODE_WSR_MEMCTL; 13055 if (Field_sr_Slot_inst_get (insn) == 99) 13056 return OPCODE_WSR_ATOMCTL; 13057 if (Field_sr_Slot_inst_get (insn) == 104) 13058 return OPCODE_WSR_DDR; 13059 if (Field_sr_Slot_inst_get (insn) == 128) 13060 return OPCODE_WSR_IBREAKA0; 13061 if (Field_sr_Slot_inst_get (insn) == 129) 13062 return OPCODE_WSR_IBREAKA1; 13063 if (Field_sr_Slot_inst_get (insn) == 144) 13064 return OPCODE_WSR_DBREAKA0; 13065 if (Field_sr_Slot_inst_get (insn) == 145) 13066 return OPCODE_WSR_DBREAKA1; 13067 if (Field_sr_Slot_inst_get (insn) == 160) 13068 return OPCODE_WSR_DBREAKC0; 13069 if (Field_sr_Slot_inst_get (insn) == 161) 13070 return OPCODE_WSR_DBREAKC1; 13071 if (Field_sr_Slot_inst_get (insn) == 176) 13072 return OPCODE_WSR_CONFIGID0; 13073 if (Field_sr_Slot_inst_get (insn) == 177) 13074 return OPCODE_WSR_EPC1; 13075 if (Field_sr_Slot_inst_get (insn) == 178) 13076 return OPCODE_WSR_EPC2; 13077 if (Field_sr_Slot_inst_get (insn) == 179) 13078 return OPCODE_WSR_EPC3; 13079 if (Field_sr_Slot_inst_get (insn) == 180) 13080 return OPCODE_WSR_EPC4; 13081 if (Field_sr_Slot_inst_get (insn) == 181) 13082 return OPCODE_WSR_EPC5; 13083 if (Field_sr_Slot_inst_get (insn) == 182) 13084 return OPCODE_WSR_EPC6; 13085 if (Field_sr_Slot_inst_get (insn) == 183) 13086 return OPCODE_WSR_EPC7; 13087 if (Field_sr_Slot_inst_get (insn) == 192) 13088 return OPCODE_WSR_DEPC; 13089 if (Field_sr_Slot_inst_get (insn) == 194) 13090 return OPCODE_WSR_EPS2; 13091 if (Field_sr_Slot_inst_get (insn) == 195) 13092 return OPCODE_WSR_EPS3; 13093 if (Field_sr_Slot_inst_get (insn) == 196) 13094 return OPCODE_WSR_EPS4; 13095 if (Field_sr_Slot_inst_get (insn) == 197) 13096 return OPCODE_WSR_EPS5; 13097 if (Field_sr_Slot_inst_get (insn) == 198) 13098 return OPCODE_WSR_EPS6; 13099 if (Field_sr_Slot_inst_get (insn) == 199) 13100 return OPCODE_WSR_EPS7; 13101 if (Field_sr_Slot_inst_get (insn) == 209) 13102 return OPCODE_WSR_EXCSAVE1; 13103 if (Field_sr_Slot_inst_get (insn) == 210) 13104 return OPCODE_WSR_EXCSAVE2; 13105 if (Field_sr_Slot_inst_get (insn) == 211) 13106 return OPCODE_WSR_EXCSAVE3; 13107 if (Field_sr_Slot_inst_get (insn) == 212) 13108 return OPCODE_WSR_EXCSAVE4; 13109 if (Field_sr_Slot_inst_get (insn) == 213) 13110 return OPCODE_WSR_EXCSAVE5; 13111 if (Field_sr_Slot_inst_get (insn) == 214) 13112 return OPCODE_WSR_EXCSAVE6; 13113 if (Field_sr_Slot_inst_get (insn) == 215) 13114 return OPCODE_WSR_EXCSAVE7; 13115 if (Field_sr_Slot_inst_get (insn) == 226) 13116 return OPCODE_WSR_INTSET; 13117 if (Field_sr_Slot_inst_get (insn) == 227) 13118 return OPCODE_WSR_INTCLEAR; 13119 if (Field_sr_Slot_inst_get (insn) == 228) 13120 return OPCODE_WSR_INTENABLE; 13121 if (Field_sr_Slot_inst_get (insn) == 230) 13122 return OPCODE_WSR_PS; 13123 if (Field_sr_Slot_inst_get (insn) == 231) 13124 return OPCODE_WSR_VECBASE; 13125 if (Field_sr_Slot_inst_get (insn) == 232) 13126 return OPCODE_WSR_EXCCAUSE; 13127 if (Field_sr_Slot_inst_get (insn) == 233) 13128 return OPCODE_WSR_DEBUGCAUSE; 13129 if (Field_sr_Slot_inst_get (insn) == 234) 13130 return OPCODE_WSR_CCOUNT; 13131 if (Field_sr_Slot_inst_get (insn) == 236) 13132 return OPCODE_WSR_ICOUNT; 13133 if (Field_sr_Slot_inst_get (insn) == 237) 13134 return OPCODE_WSR_ICOUNTLEVEL; 13135 if (Field_sr_Slot_inst_get (insn) == 238) 13136 return OPCODE_WSR_EXCVADDR; 13137 if (Field_sr_Slot_inst_get (insn) == 240) 13138 return OPCODE_WSR_CCOMPARE0; 13139 if (Field_sr_Slot_inst_get (insn) == 241) 13140 return OPCODE_WSR_CCOMPARE1; 13141 if (Field_sr_Slot_inst_get (insn) == 242) 13142 return OPCODE_WSR_CCOMPARE2; 13143 if (Field_sr_Slot_inst_get (insn) == 244) 13144 return OPCODE_WSR_MISC0; 13145 if (Field_sr_Slot_inst_get (insn) == 245) 13146 return OPCODE_WSR_MISC1; 13147 } 13148 if (Field_op2_Slot_inst_get (insn) == 2) 13149 return OPCODE_SEXT; 13150 if (Field_op2_Slot_inst_get (insn) == 3) 13151 return OPCODE_CLAMPS; 13152 if (Field_op2_Slot_inst_get (insn) == 4) 13153 return OPCODE_MIN; 13154 if (Field_op2_Slot_inst_get (insn) == 5) 13155 return OPCODE_MAX; 13156 if (Field_op2_Slot_inst_get (insn) == 6) 13157 return OPCODE_MINU; 13158 if (Field_op2_Slot_inst_get (insn) == 7) 13159 return OPCODE_MAXU; 13160 if (Field_op2_Slot_inst_get (insn) == 8) 13161 return OPCODE_MOVEQZ; 13162 if (Field_op2_Slot_inst_get (insn) == 9) 13163 return OPCODE_MOVNEZ; 13164 if (Field_op2_Slot_inst_get (insn) == 10) 13165 return OPCODE_MOVLTZ; 13166 if (Field_op2_Slot_inst_get (insn) == 11) 13167 return OPCODE_MOVGEZ; 13168 if (Field_op2_Slot_inst_get (insn) == 14) 13169 { 13170 if (Field_st_Slot_inst_get (insn) == 230) 13171 return OPCODE_RUR_EXPSTATE; 13172 } 13173 if (Field_op2_Slot_inst_get (insn) == 15) 13174 { 13175 if (Field_sr_Slot_inst_get (insn) == 230) 13176 return OPCODE_WUR_EXPSTATE; 13177 } 13178 } 13179 if ((Field_op1_Slot_inst_get (insn) == 4 || 13180 Field_op1_Slot_inst_get (insn) == 5)) 13181 return OPCODE_EXTUI; 13182 if (Field_op1_Slot_inst_get (insn) == 9) 13183 { 13184 if (Field_op2_Slot_inst_get (insn) == 0) 13185 return OPCODE_L32E; 13186 if (Field_op2_Slot_inst_get (insn) == 4) 13187 return OPCODE_S32E; 13188 if (Field_op2_Slot_inst_get (insn) == 5) 13189 return OPCODE_S32NB; 13190 } 13191 if (Field_r_Slot_inst_get (insn) == 0 && 13192 Field_s_Slot_inst_get (insn) == 0 && 13193 Field_op2_Slot_inst_get (insn) == 0 && 13194 Field_op1_Slot_inst_get (insn) == 14) 13195 return OPCODE_READ_IMPWIRE; 13196 if (Field_r_Slot_inst_get (insn) == 1 && 13197 Field_s3to1_Slot_inst_get (insn) == 0 && 13198 Field_op2_Slot_inst_get (insn) == 0 && 13199 Field_op1_Slot_inst_get (insn) == 14) 13200 return OPCODE_SETB_EXPSTATE; 13201 if (Field_r_Slot_inst_get (insn) == 1 && 13202 Field_s3to1_Slot_inst_get (insn) == 1 && 13203 Field_op2_Slot_inst_get (insn) == 0 && 13204 Field_op1_Slot_inst_get (insn) == 14) 13205 return OPCODE_CLRB_EXPSTATE; 13206 if (Field_r_Slot_inst_get (insn) == 2 && 13207 Field_op2_Slot_inst_get (insn) == 0 && 13208 Field_op1_Slot_inst_get (insn) == 14) 13209 return OPCODE_WRMSK_EXPSTATE; 13210 } 13211 if (Field_op0_Slot_inst_get (insn) == 1) 13212 return OPCODE_L32R; 13213 if (Field_op0_Slot_inst_get (insn) == 2) 13214 { 13215 if (Field_r_Slot_inst_get (insn) == 0) 13216 return OPCODE_L8UI; 13217 if (Field_r_Slot_inst_get (insn) == 1) 13218 return OPCODE_L16UI; 13219 if (Field_r_Slot_inst_get (insn) == 2) 13220 return OPCODE_L32I; 13221 if (Field_r_Slot_inst_get (insn) == 4) 13222 return OPCODE_S8I; 13223 if (Field_r_Slot_inst_get (insn) == 5) 13224 return OPCODE_S16I; 13225 if (Field_r_Slot_inst_get (insn) == 6) 13226 return OPCODE_S32I; 13227 if (Field_r_Slot_inst_get (insn) == 7) 13228 { 13229 if (Field_t_Slot_inst_get (insn) == 0) 13230 return OPCODE_DPFR; 13231 if (Field_t_Slot_inst_get (insn) == 1) 13232 return OPCODE_DPFW; 13233 if (Field_t_Slot_inst_get (insn) == 2) 13234 return OPCODE_DPFRO; 13235 if (Field_t_Slot_inst_get (insn) == 3) 13236 return OPCODE_DPFWO; 13237 if (Field_t_Slot_inst_get (insn) == 4) 13238 return OPCODE_DHWB; 13239 if (Field_t_Slot_inst_get (insn) == 5) 13240 return OPCODE_DHWBI; 13241 if (Field_t_Slot_inst_get (insn) == 6) 13242 return OPCODE_DHI; 13243 if (Field_t_Slot_inst_get (insn) == 7) 13244 return OPCODE_DII; 13245 if (Field_t_Slot_inst_get (insn) == 8) 13246 { 13247 if (Field_op1_Slot_inst_get (insn) == 0) 13248 return OPCODE_DPFL; 13249 if (Field_op1_Slot_inst_get (insn) == 2) 13250 return OPCODE_DHU; 13251 if (Field_op1_Slot_inst_get (insn) == 3) 13252 return OPCODE_DIU; 13253 if (Field_op1_Slot_inst_get (insn) == 4) 13254 return OPCODE_DIWB; 13255 if (Field_op1_Slot_inst_get (insn) == 5) 13256 return OPCODE_DIWBI; 13257 if (Field_op1_Slot_inst_get (insn) == 15 && 13258 Field_op2_Slot_inst_get (insn) == 0) 13259 return OPCODE_DIWBUI_P; 13260 } 13261 if (Field_t_Slot_inst_get (insn) == 12) 13262 return OPCODE_IPF; 13263 if (Field_t_Slot_inst_get (insn) == 13) 13264 { 13265 if (Field_op1_Slot_inst_get (insn) == 0) 13266 return OPCODE_IPFL; 13267 if (Field_op1_Slot_inst_get (insn) == 2) 13268 return OPCODE_IHU; 13269 if (Field_op1_Slot_inst_get (insn) == 3) 13270 return OPCODE_IIU; 13271 } 13272 if (Field_t_Slot_inst_get (insn) == 14) 13273 return OPCODE_IHI; 13274 if (Field_t_Slot_inst_get (insn) == 15) 13275 return OPCODE_III; 13276 } 13277 if (Field_r_Slot_inst_get (insn) == 9) 13278 return OPCODE_L16SI; 13279 if (Field_r_Slot_inst_get (insn) == 10) 13280 return OPCODE_MOVI; 13281 if (Field_r_Slot_inst_get (insn) == 11) 13282 return OPCODE_L32AI; 13283 if (Field_r_Slot_inst_get (insn) == 12) 13284 return OPCODE_ADDI; 13285 if (Field_r_Slot_inst_get (insn) == 13) 13286 return OPCODE_ADDMI; 13287 if (Field_r_Slot_inst_get (insn) == 14) 13288 return OPCODE_S32C1I; 13289 if (Field_r_Slot_inst_get (insn) == 15) 13290 return OPCODE_S32RI; 13291 } 13292 if (Field_op0_Slot_inst_get (insn) == 4) 13293 { 13294 if (Field_op2_Slot_inst_get (insn) == 0) 13295 { 13296 if (Field_op1_Slot_inst_get (insn) == 8 && 13297 Field_t3_Slot_inst_get (insn) == 0 && 13298 Field_tlo_Slot_inst_get (insn) == 0 && 13299 Field_r3_Slot_inst_get (insn) == 0) 13300 return OPCODE_MULA_DD_LL_LDINC; 13301 if (Field_op1_Slot_inst_get (insn) == 9 && 13302 Field_t3_Slot_inst_get (insn) == 0 && 13303 Field_tlo_Slot_inst_get (insn) == 0 && 13304 Field_r3_Slot_inst_get (insn) == 0) 13305 return OPCODE_MULA_DD_HL_LDINC; 13306 if (Field_op1_Slot_inst_get (insn) == 10 && 13307 Field_t3_Slot_inst_get (insn) == 0 && 13308 Field_tlo_Slot_inst_get (insn) == 0 && 13309 Field_r3_Slot_inst_get (insn) == 0) 13310 return OPCODE_MULA_DD_LH_LDINC; 13311 if (Field_op1_Slot_inst_get (insn) == 11 && 13312 Field_t3_Slot_inst_get (insn) == 0 && 13313 Field_tlo_Slot_inst_get (insn) == 0 && 13314 Field_r3_Slot_inst_get (insn) == 0) 13315 return OPCODE_MULA_DD_HH_LDINC; 13316 } 13317 if (Field_op2_Slot_inst_get (insn) == 1) 13318 { 13319 if (Field_op1_Slot_inst_get (insn) == 8 && 13320 Field_t3_Slot_inst_get (insn) == 0 && 13321 Field_tlo_Slot_inst_get (insn) == 0 && 13322 Field_r3_Slot_inst_get (insn) == 0) 13323 return OPCODE_MULA_DD_LL_LDDEC; 13324 if (Field_op1_Slot_inst_get (insn) == 9 && 13325 Field_t3_Slot_inst_get (insn) == 0 && 13326 Field_tlo_Slot_inst_get (insn) == 0 && 13327 Field_r3_Slot_inst_get (insn) == 0) 13328 return OPCODE_MULA_DD_HL_LDDEC; 13329 if (Field_op1_Slot_inst_get (insn) == 10 && 13330 Field_t3_Slot_inst_get (insn) == 0 && 13331 Field_tlo_Slot_inst_get (insn) == 0 && 13332 Field_r3_Slot_inst_get (insn) == 0) 13333 return OPCODE_MULA_DD_LH_LDDEC; 13334 if (Field_op1_Slot_inst_get (insn) == 11 && 13335 Field_t3_Slot_inst_get (insn) == 0 && 13336 Field_tlo_Slot_inst_get (insn) == 0 && 13337 Field_r3_Slot_inst_get (insn) == 0) 13338 return OPCODE_MULA_DD_HH_LDDEC; 13339 } 13340 if (Field_op2_Slot_inst_get (insn) == 2) 13341 { 13342 if (Field_op1_Slot_inst_get (insn) == 4 && 13343 Field_s_Slot_inst_get (insn) == 0 && 13344 Field_w_Slot_inst_get (insn) == 0 && 13345 Field_r3_Slot_inst_get (insn) == 0 && 13346 Field_t3_Slot_inst_get (insn) == 0 && 13347 Field_tlo_Slot_inst_get (insn) == 0) 13348 return OPCODE_MUL_DD_LL; 13349 if (Field_op1_Slot_inst_get (insn) == 5 && 13350 Field_s_Slot_inst_get (insn) == 0 && 13351 Field_w_Slot_inst_get (insn) == 0 && 13352 Field_r3_Slot_inst_get (insn) == 0 && 13353 Field_t3_Slot_inst_get (insn) == 0 && 13354 Field_tlo_Slot_inst_get (insn) == 0) 13355 return OPCODE_MUL_DD_HL; 13356 if (Field_op1_Slot_inst_get (insn) == 6 && 13357 Field_s_Slot_inst_get (insn) == 0 && 13358 Field_w_Slot_inst_get (insn) == 0 && 13359 Field_r3_Slot_inst_get (insn) == 0 && 13360 Field_t3_Slot_inst_get (insn) == 0 && 13361 Field_tlo_Slot_inst_get (insn) == 0) 13362 return OPCODE_MUL_DD_LH; 13363 if (Field_op1_Slot_inst_get (insn) == 7 && 13364 Field_s_Slot_inst_get (insn) == 0 && 13365 Field_w_Slot_inst_get (insn) == 0 && 13366 Field_r3_Slot_inst_get (insn) == 0 && 13367 Field_t3_Slot_inst_get (insn) == 0 && 13368 Field_tlo_Slot_inst_get (insn) == 0) 13369 return OPCODE_MUL_DD_HH; 13370 if (Field_op1_Slot_inst_get (insn) == 8 && 13371 Field_s_Slot_inst_get (insn) == 0 && 13372 Field_w_Slot_inst_get (insn) == 0 && 13373 Field_r3_Slot_inst_get (insn) == 0 && 13374 Field_t3_Slot_inst_get (insn) == 0 && 13375 Field_tlo_Slot_inst_get (insn) == 0) 13376 return OPCODE_MULA_DD_LL; 13377 if (Field_op1_Slot_inst_get (insn) == 9 && 13378 Field_s_Slot_inst_get (insn) == 0 && 13379 Field_w_Slot_inst_get (insn) == 0 && 13380 Field_r3_Slot_inst_get (insn) == 0 && 13381 Field_t3_Slot_inst_get (insn) == 0 && 13382 Field_tlo_Slot_inst_get (insn) == 0) 13383 return OPCODE_MULA_DD_HL; 13384 if (Field_op1_Slot_inst_get (insn) == 10 && 13385 Field_s_Slot_inst_get (insn) == 0 && 13386 Field_w_Slot_inst_get (insn) == 0 && 13387 Field_r3_Slot_inst_get (insn) == 0 && 13388 Field_t3_Slot_inst_get (insn) == 0 && 13389 Field_tlo_Slot_inst_get (insn) == 0) 13390 return OPCODE_MULA_DD_LH; 13391 if (Field_op1_Slot_inst_get (insn) == 11 && 13392 Field_s_Slot_inst_get (insn) == 0 && 13393 Field_w_Slot_inst_get (insn) == 0 && 13394 Field_r3_Slot_inst_get (insn) == 0 && 13395 Field_t3_Slot_inst_get (insn) == 0 && 13396 Field_tlo_Slot_inst_get (insn) == 0) 13397 return OPCODE_MULA_DD_HH; 13398 if (Field_op1_Slot_inst_get (insn) == 12 && 13399 Field_s_Slot_inst_get (insn) == 0 && 13400 Field_w_Slot_inst_get (insn) == 0 && 13401 Field_r3_Slot_inst_get (insn) == 0 && 13402 Field_t3_Slot_inst_get (insn) == 0 && 13403 Field_tlo_Slot_inst_get (insn) == 0) 13404 return OPCODE_MULS_DD_LL; 13405 if (Field_op1_Slot_inst_get (insn) == 13 && 13406 Field_s_Slot_inst_get (insn) == 0 && 13407 Field_w_Slot_inst_get (insn) == 0 && 13408 Field_r3_Slot_inst_get (insn) == 0 && 13409 Field_t3_Slot_inst_get (insn) == 0 && 13410 Field_tlo_Slot_inst_get (insn) == 0) 13411 return OPCODE_MULS_DD_HL; 13412 if (Field_op1_Slot_inst_get (insn) == 14 && 13413 Field_s_Slot_inst_get (insn) == 0 && 13414 Field_w_Slot_inst_get (insn) == 0 && 13415 Field_r3_Slot_inst_get (insn) == 0 && 13416 Field_t3_Slot_inst_get (insn) == 0 && 13417 Field_tlo_Slot_inst_get (insn) == 0) 13418 return OPCODE_MULS_DD_LH; 13419 if (Field_op1_Slot_inst_get (insn) == 15 && 13420 Field_s_Slot_inst_get (insn) == 0 && 13421 Field_w_Slot_inst_get (insn) == 0 && 13422 Field_r3_Slot_inst_get (insn) == 0 && 13423 Field_t3_Slot_inst_get (insn) == 0 && 13424 Field_tlo_Slot_inst_get (insn) == 0) 13425 return OPCODE_MULS_DD_HH; 13426 } 13427 if (Field_op2_Slot_inst_get (insn) == 3) 13428 { 13429 if (Field_op1_Slot_inst_get (insn) == 4 && 13430 Field_r_Slot_inst_get (insn) == 0 && 13431 Field_t3_Slot_inst_get (insn) == 0 && 13432 Field_tlo_Slot_inst_get (insn) == 0) 13433 return OPCODE_MUL_AD_LL; 13434 if (Field_op1_Slot_inst_get (insn) == 5 && 13435 Field_r_Slot_inst_get (insn) == 0 && 13436 Field_t3_Slot_inst_get (insn) == 0 && 13437 Field_tlo_Slot_inst_get (insn) == 0) 13438 return OPCODE_MUL_AD_HL; 13439 if (Field_op1_Slot_inst_get (insn) == 6 && 13440 Field_r_Slot_inst_get (insn) == 0 && 13441 Field_t3_Slot_inst_get (insn) == 0 && 13442 Field_tlo_Slot_inst_get (insn) == 0) 13443 return OPCODE_MUL_AD_LH; 13444 if (Field_op1_Slot_inst_get (insn) == 7 && 13445 Field_r_Slot_inst_get (insn) == 0 && 13446 Field_t3_Slot_inst_get (insn) == 0 && 13447 Field_tlo_Slot_inst_get (insn) == 0) 13448 return OPCODE_MUL_AD_HH; 13449 if (Field_op1_Slot_inst_get (insn) == 8 && 13450 Field_r_Slot_inst_get (insn) == 0 && 13451 Field_t3_Slot_inst_get (insn) == 0 && 13452 Field_tlo_Slot_inst_get (insn) == 0) 13453 return OPCODE_MULA_AD_LL; 13454 if (Field_op1_Slot_inst_get (insn) == 9 && 13455 Field_r_Slot_inst_get (insn) == 0 && 13456 Field_t3_Slot_inst_get (insn) == 0 && 13457 Field_tlo_Slot_inst_get (insn) == 0) 13458 return OPCODE_MULA_AD_HL; 13459 if (Field_op1_Slot_inst_get (insn) == 10 && 13460 Field_r_Slot_inst_get (insn) == 0 && 13461 Field_t3_Slot_inst_get (insn) == 0 && 13462 Field_tlo_Slot_inst_get (insn) == 0) 13463 return OPCODE_MULA_AD_LH; 13464 if (Field_op1_Slot_inst_get (insn) == 11 && 13465 Field_r_Slot_inst_get (insn) == 0 && 13466 Field_t3_Slot_inst_get (insn) == 0 && 13467 Field_tlo_Slot_inst_get (insn) == 0) 13468 return OPCODE_MULA_AD_HH; 13469 if (Field_op1_Slot_inst_get (insn) == 12 && 13470 Field_r_Slot_inst_get (insn) == 0 && 13471 Field_t3_Slot_inst_get (insn) == 0 && 13472 Field_tlo_Slot_inst_get (insn) == 0) 13473 return OPCODE_MULS_AD_LL; 13474 if (Field_op1_Slot_inst_get (insn) == 13 && 13475 Field_r_Slot_inst_get (insn) == 0 && 13476 Field_t3_Slot_inst_get (insn) == 0 && 13477 Field_tlo_Slot_inst_get (insn) == 0) 13478 return OPCODE_MULS_AD_HL; 13479 if (Field_op1_Slot_inst_get (insn) == 14 && 13480 Field_r_Slot_inst_get (insn) == 0 && 13481 Field_t3_Slot_inst_get (insn) == 0 && 13482 Field_tlo_Slot_inst_get (insn) == 0) 13483 return OPCODE_MULS_AD_LH; 13484 if (Field_op1_Slot_inst_get (insn) == 15 && 13485 Field_r_Slot_inst_get (insn) == 0 && 13486 Field_t3_Slot_inst_get (insn) == 0 && 13487 Field_tlo_Slot_inst_get (insn) == 0) 13488 return OPCODE_MULS_AD_HH; 13489 } 13490 if (Field_op2_Slot_inst_get (insn) == 4) 13491 { 13492 if (Field_op1_Slot_inst_get (insn) == 8 && 13493 Field_r3_Slot_inst_get (insn) == 0) 13494 return OPCODE_MULA_DA_LL_LDINC; 13495 if (Field_op1_Slot_inst_get (insn) == 9 && 13496 Field_r3_Slot_inst_get (insn) == 0) 13497 return OPCODE_MULA_DA_HL_LDINC; 13498 if (Field_op1_Slot_inst_get (insn) == 10 && 13499 Field_r3_Slot_inst_get (insn) == 0) 13500 return OPCODE_MULA_DA_LH_LDINC; 13501 if (Field_op1_Slot_inst_get (insn) == 11 && 13502 Field_r3_Slot_inst_get (insn) == 0) 13503 return OPCODE_MULA_DA_HH_LDINC; 13504 } 13505 if (Field_op2_Slot_inst_get (insn) == 5) 13506 { 13507 if (Field_op1_Slot_inst_get (insn) == 8 && 13508 Field_r3_Slot_inst_get (insn) == 0) 13509 return OPCODE_MULA_DA_LL_LDDEC; 13510 if (Field_op1_Slot_inst_get (insn) == 9 && 13511 Field_r3_Slot_inst_get (insn) == 0) 13512 return OPCODE_MULA_DA_HL_LDDEC; 13513 if (Field_op1_Slot_inst_get (insn) == 10 && 13514 Field_r3_Slot_inst_get (insn) == 0) 13515 return OPCODE_MULA_DA_LH_LDDEC; 13516 if (Field_op1_Slot_inst_get (insn) == 11 && 13517 Field_r3_Slot_inst_get (insn) == 0) 13518 return OPCODE_MULA_DA_HH_LDDEC; 13519 } 13520 if (Field_op2_Slot_inst_get (insn) == 6) 13521 { 13522 if (Field_op1_Slot_inst_get (insn) == 4 && 13523 Field_s_Slot_inst_get (insn) == 0 && 13524 Field_w_Slot_inst_get (insn) == 0 && 13525 Field_r3_Slot_inst_get (insn) == 0) 13526 return OPCODE_MUL_DA_LL; 13527 if (Field_op1_Slot_inst_get (insn) == 5 && 13528 Field_s_Slot_inst_get (insn) == 0 && 13529 Field_w_Slot_inst_get (insn) == 0 && 13530 Field_r3_Slot_inst_get (insn) == 0) 13531 return OPCODE_MUL_DA_HL; 13532 if (Field_op1_Slot_inst_get (insn) == 6 && 13533 Field_s_Slot_inst_get (insn) == 0 && 13534 Field_w_Slot_inst_get (insn) == 0 && 13535 Field_r3_Slot_inst_get (insn) == 0) 13536 return OPCODE_MUL_DA_LH; 13537 if (Field_op1_Slot_inst_get (insn) == 7 && 13538 Field_s_Slot_inst_get (insn) == 0 && 13539 Field_w_Slot_inst_get (insn) == 0 && 13540 Field_r3_Slot_inst_get (insn) == 0) 13541 return OPCODE_MUL_DA_HH; 13542 if (Field_op1_Slot_inst_get (insn) == 8 && 13543 Field_s_Slot_inst_get (insn) == 0 && 13544 Field_w_Slot_inst_get (insn) == 0 && 13545 Field_r3_Slot_inst_get (insn) == 0) 13546 return OPCODE_MULA_DA_LL; 13547 if (Field_op1_Slot_inst_get (insn) == 9 && 13548 Field_s_Slot_inst_get (insn) == 0 && 13549 Field_w_Slot_inst_get (insn) == 0 && 13550 Field_r3_Slot_inst_get (insn) == 0) 13551 return OPCODE_MULA_DA_HL; 13552 if (Field_op1_Slot_inst_get (insn) == 10 && 13553 Field_s_Slot_inst_get (insn) == 0 && 13554 Field_w_Slot_inst_get (insn) == 0 && 13555 Field_r3_Slot_inst_get (insn) == 0) 13556 return OPCODE_MULA_DA_LH; 13557 if (Field_op1_Slot_inst_get (insn) == 11 && 13558 Field_s_Slot_inst_get (insn) == 0 && 13559 Field_w_Slot_inst_get (insn) == 0 && 13560 Field_r3_Slot_inst_get (insn) == 0) 13561 return OPCODE_MULA_DA_HH; 13562 if (Field_op1_Slot_inst_get (insn) == 12 && 13563 Field_s_Slot_inst_get (insn) == 0 && 13564 Field_w_Slot_inst_get (insn) == 0 && 13565 Field_r3_Slot_inst_get (insn) == 0) 13566 return OPCODE_MULS_DA_LL; 13567 if (Field_op1_Slot_inst_get (insn) == 13 && 13568 Field_s_Slot_inst_get (insn) == 0 && 13569 Field_w_Slot_inst_get (insn) == 0 && 13570 Field_r3_Slot_inst_get (insn) == 0) 13571 return OPCODE_MULS_DA_HL; 13572 if (Field_op1_Slot_inst_get (insn) == 14 && 13573 Field_s_Slot_inst_get (insn) == 0 && 13574 Field_w_Slot_inst_get (insn) == 0 && 13575 Field_r3_Slot_inst_get (insn) == 0) 13576 return OPCODE_MULS_DA_LH; 13577 if (Field_op1_Slot_inst_get (insn) == 15 && 13578 Field_s_Slot_inst_get (insn) == 0 && 13579 Field_w_Slot_inst_get (insn) == 0 && 13580 Field_r3_Slot_inst_get (insn) == 0) 13581 return OPCODE_MULS_DA_HH; 13582 } 13583 if (Field_op2_Slot_inst_get (insn) == 7) 13584 { 13585 if (Field_op1_Slot_inst_get (insn) == 0 && 13586 Field_r_Slot_inst_get (insn) == 0) 13587 return OPCODE_UMUL_AA_LL; 13588 if (Field_op1_Slot_inst_get (insn) == 1 && 13589 Field_r_Slot_inst_get (insn) == 0) 13590 return OPCODE_UMUL_AA_HL; 13591 if (Field_op1_Slot_inst_get (insn) == 2 && 13592 Field_r_Slot_inst_get (insn) == 0) 13593 return OPCODE_UMUL_AA_LH; 13594 if (Field_op1_Slot_inst_get (insn) == 3 && 13595 Field_r_Slot_inst_get (insn) == 0) 13596 return OPCODE_UMUL_AA_HH; 13597 if (Field_op1_Slot_inst_get (insn) == 4 && 13598 Field_r_Slot_inst_get (insn) == 0) 13599 return OPCODE_MUL_AA_LL; 13600 if (Field_op1_Slot_inst_get (insn) == 5 && 13601 Field_r_Slot_inst_get (insn) == 0) 13602 return OPCODE_MUL_AA_HL; 13603 if (Field_op1_Slot_inst_get (insn) == 6 && 13604 Field_r_Slot_inst_get (insn) == 0) 13605 return OPCODE_MUL_AA_LH; 13606 if (Field_op1_Slot_inst_get (insn) == 7 && 13607 Field_r_Slot_inst_get (insn) == 0) 13608 return OPCODE_MUL_AA_HH; 13609 if (Field_op1_Slot_inst_get (insn) == 8 && 13610 Field_r_Slot_inst_get (insn) == 0) 13611 return OPCODE_MULA_AA_LL; 13612 if (Field_op1_Slot_inst_get (insn) == 9 && 13613 Field_r_Slot_inst_get (insn) == 0) 13614 return OPCODE_MULA_AA_HL; 13615 if (Field_op1_Slot_inst_get (insn) == 10 && 13616 Field_r_Slot_inst_get (insn) == 0) 13617 return OPCODE_MULA_AA_LH; 13618 if (Field_op1_Slot_inst_get (insn) == 11 && 13619 Field_r_Slot_inst_get (insn) == 0) 13620 return OPCODE_MULA_AA_HH; 13621 if (Field_op1_Slot_inst_get (insn) == 12 && 13622 Field_r_Slot_inst_get (insn) == 0) 13623 return OPCODE_MULS_AA_LL; 13624 if (Field_op1_Slot_inst_get (insn) == 13 && 13625 Field_r_Slot_inst_get (insn) == 0) 13626 return OPCODE_MULS_AA_HL; 13627 if (Field_op1_Slot_inst_get (insn) == 14 && 13628 Field_r_Slot_inst_get (insn) == 0) 13629 return OPCODE_MULS_AA_LH; 13630 if (Field_op1_Slot_inst_get (insn) == 15 && 13631 Field_r_Slot_inst_get (insn) == 0) 13632 return OPCODE_MULS_AA_HH; 13633 } 13634 if (Field_op2_Slot_inst_get (insn) == 8) 13635 { 13636 if (Field_op1_Slot_inst_get (insn) == 0 && 13637 Field_t_Slot_inst_get (insn) == 0 && 13638 Field_rhi_Slot_inst_get (insn) == 0) 13639 return OPCODE_LDINC; 13640 } 13641 if (Field_op2_Slot_inst_get (insn) == 9) 13642 { 13643 if (Field_op1_Slot_inst_get (insn) == 0 && 13644 Field_t_Slot_inst_get (insn) == 0 && 13645 Field_rhi_Slot_inst_get (insn) == 0) 13646 return OPCODE_LDDEC; 13647 } 13648 } 13649 if (Field_op0_Slot_inst_get (insn) == 5) 13650 { 13651 if (Field_n_Slot_inst_get (insn) == 0) 13652 return OPCODE_CALL0; 13653 if (Field_n_Slot_inst_get (insn) == 1) 13654 return OPCODE_CALL4; 13655 if (Field_n_Slot_inst_get (insn) == 2) 13656 return OPCODE_CALL8; 13657 if (Field_n_Slot_inst_get (insn) == 3) 13658 return OPCODE_CALL12; 13659 } 13660 if (Field_op0_Slot_inst_get (insn) == 6) 13661 { 13662 if (Field_n_Slot_inst_get (insn) == 0) 13663 return OPCODE_J; 13664 if (Field_n_Slot_inst_get (insn) == 1) 13665 { 13666 if (Field_m_Slot_inst_get (insn) == 0) 13667 return OPCODE_BEQZ; 13668 if (Field_m_Slot_inst_get (insn) == 1) 13669 return OPCODE_BNEZ; 13670 if (Field_m_Slot_inst_get (insn) == 2) 13671 return OPCODE_BLTZ; 13672 if (Field_m_Slot_inst_get (insn) == 3) 13673 return OPCODE_BGEZ; 13674 } 13675 if (Field_n_Slot_inst_get (insn) == 2) 13676 { 13677 if (Field_m_Slot_inst_get (insn) == 0) 13678 return OPCODE_BEQI; 13679 if (Field_m_Slot_inst_get (insn) == 1) 13680 return OPCODE_BNEI; 13681 if (Field_m_Slot_inst_get (insn) == 2) 13682 return OPCODE_BLTI; 13683 if (Field_m_Slot_inst_get (insn) == 3) 13684 return OPCODE_BGEI; 13685 } 13686 if (Field_n_Slot_inst_get (insn) == 3) 13687 { 13688 if (Field_m_Slot_inst_get (insn) == 0) 13689 return OPCODE_ENTRY; 13690 if (Field_m_Slot_inst_get (insn) == 1) 13691 { 13692 if (Field_r_Slot_inst_get (insn) == 8) 13693 return OPCODE_LOOP; 13694 if (Field_r_Slot_inst_get (insn) == 9) 13695 return OPCODE_LOOPNEZ; 13696 if (Field_r_Slot_inst_get (insn) == 10) 13697 return OPCODE_LOOPGTZ; 13698 } 13699 if (Field_m_Slot_inst_get (insn) == 2) 13700 return OPCODE_BLTUI; 13701 if (Field_m_Slot_inst_get (insn) == 3) 13702 return OPCODE_BGEUI; 13703 } 13704 } 13705 if (Field_op0_Slot_inst_get (insn) == 7) 13706 { 13707 if (Field_r_Slot_inst_get (insn) == 0) 13708 return OPCODE_BNONE; 13709 if (Field_r_Slot_inst_get (insn) == 1) 13710 return OPCODE_BEQ; 13711 if (Field_r_Slot_inst_get (insn) == 2) 13712 return OPCODE_BLT; 13713 if (Field_r_Slot_inst_get (insn) == 3) 13714 return OPCODE_BLTU; 13715 if (Field_r_Slot_inst_get (insn) == 4) 13716 return OPCODE_BALL; 13717 if (Field_r_Slot_inst_get (insn) == 5) 13718 return OPCODE_BBC; 13719 if ((Field_r_Slot_inst_get (insn) == 6 || 13720 Field_r_Slot_inst_get (insn) == 7)) 13721 return OPCODE_BBCI; 13722 if (Field_r_Slot_inst_get (insn) == 8) 13723 return OPCODE_BANY; 13724 if (Field_r_Slot_inst_get (insn) == 9) 13725 return OPCODE_BNE; 13726 if (Field_r_Slot_inst_get (insn) == 10) 13727 return OPCODE_BGE; 13728 if (Field_r_Slot_inst_get (insn) == 11) 13729 return OPCODE_BGEU; 13730 if (Field_r_Slot_inst_get (insn) == 12) 13731 return OPCODE_BNALL; 13732 if (Field_r_Slot_inst_get (insn) == 13) 13733 return OPCODE_BBS; 13734 if ((Field_r_Slot_inst_get (insn) == 14 || 13735 Field_r_Slot_inst_get (insn) == 15)) 13736 return OPCODE_BBSI; 13737 } 13738 return XTENSA_UNDEFINED; 13739} 13740 13741static int 13742Slot_inst16b_decode (const xtensa_insnbuf insn) 13743{ 13744 if (Field_op0_Slot_inst16b_get (insn) == 12) 13745 { 13746 if (Field_i_Slot_inst16b_get (insn) == 0) 13747 return OPCODE_MOVI_N; 13748 if (Field_i_Slot_inst16b_get (insn) == 1) 13749 { 13750 if (Field_z_Slot_inst16b_get (insn) == 0) 13751 return OPCODE_BEQZ_N; 13752 if (Field_z_Slot_inst16b_get (insn) == 1) 13753 return OPCODE_BNEZ_N; 13754 } 13755 } 13756 if (Field_op0_Slot_inst16b_get (insn) == 13) 13757 { 13758 if (Field_r_Slot_inst16b_get (insn) == 0) 13759 return OPCODE_MOV_N; 13760 if (Field_r_Slot_inst16b_get (insn) == 15) 13761 { 13762 if (Field_t_Slot_inst16b_get (insn) == 0) 13763 return OPCODE_RET_N; 13764 if (Field_t_Slot_inst16b_get (insn) == 1) 13765 return OPCODE_RETW_N; 13766 if (Field_t_Slot_inst16b_get (insn) == 2) 13767 return OPCODE_BREAK_N; 13768 if (Field_t_Slot_inst16b_get (insn) == 3 && 13769 Field_s_Slot_inst16b_get (insn) == 0) 13770 return OPCODE_NOP_N; 13771 if (Field_t_Slot_inst16b_get (insn) == 6 && 13772 Field_s_Slot_inst16b_get (insn) == 0) 13773 return OPCODE_ILL_N; 13774 } 13775 } 13776 return XTENSA_UNDEFINED; 13777} 13778 13779static int 13780Slot_inst16a_decode (const xtensa_insnbuf insn) 13781{ 13782 if (Field_op0_Slot_inst16a_get (insn) == 8) 13783 return OPCODE_L32I_N; 13784 if (Field_op0_Slot_inst16a_get (insn) == 9) 13785 return OPCODE_S32I_N; 13786 if (Field_op0_Slot_inst16a_get (insn) == 10) 13787 return OPCODE_ADD_N; 13788 if (Field_op0_Slot_inst16a_get (insn) == 11) 13789 return OPCODE_ADDI_N; 13790 return XTENSA_UNDEFINED; 13791} 13792 13793 13794/* Instruction slots. */ 13795 13796static void 13797Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, 13798 xtensa_insnbuf slotbuf) 13799{ 13800 slotbuf[0] = (insn[0] & 0xffffff); 13801} 13802 13803static void 13804Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, 13805 const xtensa_insnbuf slotbuf) 13806{ 13807 insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff); 13808} 13809 13810static void 13811Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, 13812 xtensa_insnbuf slotbuf) 13813{ 13814 slotbuf[0] = (insn[0] & 0xffff); 13815} 13816 13817static void 13818Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, 13819 const xtensa_insnbuf slotbuf) 13820{ 13821 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); 13822} 13823 13824static void 13825Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, 13826 xtensa_insnbuf slotbuf) 13827{ 13828 slotbuf[0] = (insn[0] & 0xffff); 13829} 13830 13831static void 13832Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, 13833 const xtensa_insnbuf slotbuf) 13834{ 13835 insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff); 13836} 13837 13838static xtensa_get_field_fn 13839Slot_inst_get_field_fns[] = { 13840 Field_t_Slot_inst_get, 13841 Field_bbi4_Slot_inst_get, 13842 Field_bbi_Slot_inst_get, 13843 Field_imm12_Slot_inst_get, 13844 Field_imm8_Slot_inst_get, 13845 Field_s_Slot_inst_get, 13846 Field_imm12b_Slot_inst_get, 13847 Field_imm16_Slot_inst_get, 13848 Field_m_Slot_inst_get, 13849 Field_n_Slot_inst_get, 13850 Field_offset_Slot_inst_get, 13851 Field_op0_Slot_inst_get, 13852 Field_op1_Slot_inst_get, 13853 Field_op2_Slot_inst_get, 13854 Field_r_Slot_inst_get, 13855 Field_sa4_Slot_inst_get, 13856 Field_sae4_Slot_inst_get, 13857 Field_sae_Slot_inst_get, 13858 Field_sal_Slot_inst_get, 13859 Field_sargt_Slot_inst_get, 13860 Field_sas4_Slot_inst_get, 13861 Field_sas_Slot_inst_get, 13862 Field_sr_Slot_inst_get, 13863 Field_st_Slot_inst_get, 13864 Field_thi3_Slot_inst_get, 13865 Field_imm4_Slot_inst_get, 13866 Field_mn_Slot_inst_get, 13867 0, 13868 0, 13869 0, 13870 0, 13871 0, 13872 0, 13873 0, 13874 0, 13875 Field_r3_Slot_inst_get, 13876 Field_rbit2_Slot_inst_get, 13877 Field_rhi_Slot_inst_get, 13878 Field_t3_Slot_inst_get, 13879 Field_tbit2_Slot_inst_get, 13880 Field_tlo_Slot_inst_get, 13881 Field_w_Slot_inst_get, 13882 Field_y_Slot_inst_get, 13883 Field_x_Slot_inst_get, 13884 Field_xt_wbr15_imm_Slot_inst_get, 13885 Field_xt_wbr18_imm_Slot_inst_get, 13886 Field_bitindex_Slot_inst_get, 13887 Field_s3to1_Slot_inst_get, 13888 Implicit_Field_ar0_get, 13889 Implicit_Field_ar4_get, 13890 Implicit_Field_ar8_get, 13891 Implicit_Field_ar12_get, 13892 Implicit_Field_mr0_get, 13893 Implicit_Field_mr1_get, 13894 Implicit_Field_mr2_get, 13895 Implicit_Field_mr3_get 13896}; 13897 13898static xtensa_set_field_fn 13899Slot_inst_set_field_fns[] = { 13900 Field_t_Slot_inst_set, 13901 Field_bbi4_Slot_inst_set, 13902 Field_bbi_Slot_inst_set, 13903 Field_imm12_Slot_inst_set, 13904 Field_imm8_Slot_inst_set, 13905 Field_s_Slot_inst_set, 13906 Field_imm12b_Slot_inst_set, 13907 Field_imm16_Slot_inst_set, 13908 Field_m_Slot_inst_set, 13909 Field_n_Slot_inst_set, 13910 Field_offset_Slot_inst_set, 13911 Field_op0_Slot_inst_set, 13912 Field_op1_Slot_inst_set, 13913 Field_op2_Slot_inst_set, 13914 Field_r_Slot_inst_set, 13915 Field_sa4_Slot_inst_set, 13916 Field_sae4_Slot_inst_set, 13917 Field_sae_Slot_inst_set, 13918 Field_sal_Slot_inst_set, 13919 Field_sargt_Slot_inst_set, 13920 Field_sas4_Slot_inst_set, 13921 Field_sas_Slot_inst_set, 13922 Field_sr_Slot_inst_set, 13923 Field_st_Slot_inst_set, 13924 Field_thi3_Slot_inst_set, 13925 Field_imm4_Slot_inst_set, 13926 Field_mn_Slot_inst_set, 13927 0, 13928 0, 13929 0, 13930 0, 13931 0, 13932 0, 13933 0, 13934 0, 13935 Field_r3_Slot_inst_set, 13936 Field_rbit2_Slot_inst_set, 13937 Field_rhi_Slot_inst_set, 13938 Field_t3_Slot_inst_set, 13939 Field_tbit2_Slot_inst_set, 13940 Field_tlo_Slot_inst_set, 13941 Field_w_Slot_inst_set, 13942 Field_y_Slot_inst_set, 13943 Field_x_Slot_inst_set, 13944 Field_xt_wbr15_imm_Slot_inst_set, 13945 Field_xt_wbr18_imm_Slot_inst_set, 13946 Field_bitindex_Slot_inst_set, 13947 Field_s3to1_Slot_inst_set, 13948 Implicit_Field_set, 13949 Implicit_Field_set, 13950 Implicit_Field_set, 13951 Implicit_Field_set, 13952 Implicit_Field_set, 13953 Implicit_Field_set, 13954 Implicit_Field_set, 13955 Implicit_Field_set 13956}; 13957 13958static xtensa_get_field_fn 13959Slot_inst16a_get_field_fns[] = { 13960 Field_t_Slot_inst16a_get, 13961 0, 13962 0, 13963 0, 13964 0, 13965 Field_s_Slot_inst16a_get, 13966 0, 13967 0, 13968 0, 13969 0, 13970 0, 13971 Field_op0_Slot_inst16a_get, 13972 0, 13973 0, 13974 Field_r_Slot_inst16a_get, 13975 0, 13976 0, 13977 0, 13978 0, 13979 0, 13980 0, 13981 0, 13982 Field_sr_Slot_inst16a_get, 13983 Field_st_Slot_inst16a_get, 13984 0, 13985 Field_imm4_Slot_inst16a_get, 13986 0, 13987 Field_i_Slot_inst16a_get, 13988 Field_imm6lo_Slot_inst16a_get, 13989 Field_imm6hi_Slot_inst16a_get, 13990 Field_imm7lo_Slot_inst16a_get, 13991 Field_imm7hi_Slot_inst16a_get, 13992 Field_z_Slot_inst16a_get, 13993 Field_imm6_Slot_inst16a_get, 13994 Field_imm7_Slot_inst16a_get, 13995 0, 13996 0, 13997 0, 13998 0, 13999 0, 14000 0, 14001 0, 14002 0, 14003 0, 14004 0, 14005 0, 14006 Field_bitindex_Slot_inst16a_get, 14007 Field_s3to1_Slot_inst16a_get, 14008 Implicit_Field_ar0_get, 14009 Implicit_Field_ar4_get, 14010 Implicit_Field_ar8_get, 14011 Implicit_Field_ar12_get, 14012 Implicit_Field_mr0_get, 14013 Implicit_Field_mr1_get, 14014 Implicit_Field_mr2_get, 14015 Implicit_Field_mr3_get 14016}; 14017 14018static xtensa_set_field_fn 14019Slot_inst16a_set_field_fns[] = { 14020 Field_t_Slot_inst16a_set, 14021 0, 14022 0, 14023 0, 14024 0, 14025 Field_s_Slot_inst16a_set, 14026 0, 14027 0, 14028 0, 14029 0, 14030 0, 14031 Field_op0_Slot_inst16a_set, 14032 0, 14033 0, 14034 Field_r_Slot_inst16a_set, 14035 0, 14036 0, 14037 0, 14038 0, 14039 0, 14040 0, 14041 0, 14042 Field_sr_Slot_inst16a_set, 14043 Field_st_Slot_inst16a_set, 14044 0, 14045 Field_imm4_Slot_inst16a_set, 14046 0, 14047 Field_i_Slot_inst16a_set, 14048 Field_imm6lo_Slot_inst16a_set, 14049 Field_imm6hi_Slot_inst16a_set, 14050 Field_imm7lo_Slot_inst16a_set, 14051 Field_imm7hi_Slot_inst16a_set, 14052 Field_z_Slot_inst16a_set, 14053 Field_imm6_Slot_inst16a_set, 14054 Field_imm7_Slot_inst16a_set, 14055 0, 14056 0, 14057 0, 14058 0, 14059 0, 14060 0, 14061 0, 14062 0, 14063 0, 14064 0, 14065 0, 14066 Field_bitindex_Slot_inst16a_set, 14067 Field_s3to1_Slot_inst16a_set, 14068 Implicit_Field_set, 14069 Implicit_Field_set, 14070 Implicit_Field_set, 14071 Implicit_Field_set, 14072 Implicit_Field_set, 14073 Implicit_Field_set, 14074 Implicit_Field_set, 14075 Implicit_Field_set 14076}; 14077 14078static xtensa_get_field_fn 14079Slot_inst16b_get_field_fns[] = { 14080 Field_t_Slot_inst16b_get, 14081 0, 14082 0, 14083 0, 14084 0, 14085 Field_s_Slot_inst16b_get, 14086 0, 14087 0, 14088 0, 14089 0, 14090 0, 14091 Field_op0_Slot_inst16b_get, 14092 0, 14093 0, 14094 Field_r_Slot_inst16b_get, 14095 0, 14096 0, 14097 0, 14098 0, 14099 0, 14100 0, 14101 0, 14102 Field_sr_Slot_inst16b_get, 14103 Field_st_Slot_inst16b_get, 14104 0, 14105 Field_imm4_Slot_inst16b_get, 14106 0, 14107 Field_i_Slot_inst16b_get, 14108 Field_imm6lo_Slot_inst16b_get, 14109 Field_imm6hi_Slot_inst16b_get, 14110 Field_imm7lo_Slot_inst16b_get, 14111 Field_imm7hi_Slot_inst16b_get, 14112 Field_z_Slot_inst16b_get, 14113 Field_imm6_Slot_inst16b_get, 14114 Field_imm7_Slot_inst16b_get, 14115 0, 14116 0, 14117 0, 14118 0, 14119 0, 14120 0, 14121 0, 14122 0, 14123 0, 14124 0, 14125 0, 14126 Field_bitindex_Slot_inst16b_get, 14127 Field_s3to1_Slot_inst16b_get, 14128 Implicit_Field_ar0_get, 14129 Implicit_Field_ar4_get, 14130 Implicit_Field_ar8_get, 14131 Implicit_Field_ar12_get, 14132 Implicit_Field_mr0_get, 14133 Implicit_Field_mr1_get, 14134 Implicit_Field_mr2_get, 14135 Implicit_Field_mr3_get 14136}; 14137 14138static xtensa_set_field_fn 14139Slot_inst16b_set_field_fns[] = { 14140 Field_t_Slot_inst16b_set, 14141 0, 14142 0, 14143 0, 14144 0, 14145 Field_s_Slot_inst16b_set, 14146 0, 14147 0, 14148 0, 14149 0, 14150 0, 14151 Field_op0_Slot_inst16b_set, 14152 0, 14153 0, 14154 Field_r_Slot_inst16b_set, 14155 0, 14156 0, 14157 0, 14158 0, 14159 0, 14160 0, 14161 0, 14162 Field_sr_Slot_inst16b_set, 14163 Field_st_Slot_inst16b_set, 14164 0, 14165 Field_imm4_Slot_inst16b_set, 14166 0, 14167 Field_i_Slot_inst16b_set, 14168 Field_imm6lo_Slot_inst16b_set, 14169 Field_imm6hi_Slot_inst16b_set, 14170 Field_imm7lo_Slot_inst16b_set, 14171 Field_imm7hi_Slot_inst16b_set, 14172 Field_z_Slot_inst16b_set, 14173 Field_imm6_Slot_inst16b_set, 14174 Field_imm7_Slot_inst16b_set, 14175 0, 14176 0, 14177 0, 14178 0, 14179 0, 14180 0, 14181 0, 14182 0, 14183 0, 14184 0, 14185 0, 14186 Field_bitindex_Slot_inst16b_set, 14187 Field_s3to1_Slot_inst16b_set, 14188 Implicit_Field_set, 14189 Implicit_Field_set, 14190 Implicit_Field_set, 14191 Implicit_Field_set, 14192 Implicit_Field_set, 14193 Implicit_Field_set, 14194 Implicit_Field_set, 14195 Implicit_Field_set 14196}; 14197 14198static xtensa_slot_internal slots[] = { 14199 { "Inst", "x24", 0, 14200 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, 14201 Slot_inst_get_field_fns, Slot_inst_set_field_fns, 14202 Slot_inst_decode, "nop" }, 14203 { "Inst16a", "x16a", 0, 14204 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, 14205 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, 14206 Slot_inst16a_decode, "" }, 14207 { "Inst16b", "x16b", 0, 14208 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, 14209 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, 14210 Slot_inst16b_decode, "nop.n" } 14211}; 14212 14213 14214/* Instruction formats. */ 14215 14216static void 14217Format_x24_encode (xtensa_insnbuf insn) 14218{ 14219 insn[0] = 0; 14220} 14221 14222static void 14223Format_x16a_encode (xtensa_insnbuf insn) 14224{ 14225 insn[0] = 0x8; 14226} 14227 14228static void 14229Format_x16b_encode (xtensa_insnbuf insn) 14230{ 14231 insn[0] = 0xc; 14232} 14233 14234static int Format_x24_slots[] = { 0 }; 14235 14236static int Format_x16a_slots[] = { 1 }; 14237 14238static int Format_x16b_slots[] = { 2 }; 14239 14240static xtensa_format_internal formats[] = { 14241 { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, 14242 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, 14243 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots } 14244}; 14245 14246 14247static int 14248format_decoder (const xtensa_insnbuf insn) 14249{ 14250 if ((insn[0] & 0x8) == 0) 14251 return 0; /* x24 */ 14252 if ((insn[0] & 0xc) == 0x8) 14253 return 1; /* x16a */ 14254 if ((insn[0] & 0xe) == 0xc) 14255 return 2; /* x16b */ 14256 return -1; 14257} 14258 14259static int length_table[256] = { 14260 3, 14261 3, 14262 3, 14263 3, 14264 3, 14265 3, 14266 3, 14267 3, 14268 2, 14269 2, 14270 2, 14271 2, 14272 2, 14273 2, 14274 -1, 14275 -1, 14276 3, 14277 3, 14278 3, 14279 3, 14280 3, 14281 3, 14282 3, 14283 3, 14284 2, 14285 2, 14286 2, 14287 2, 14288 2, 14289 2, 14290 -1, 14291 -1, 14292 3, 14293 3, 14294 3, 14295 3, 14296 3, 14297 3, 14298 3, 14299 3, 14300 2, 14301 2, 14302 2, 14303 2, 14304 2, 14305 2, 14306 -1, 14307 -1, 14308 3, 14309 3, 14310 3, 14311 3, 14312 3, 14313 3, 14314 3, 14315 3, 14316 2, 14317 2, 14318 2, 14319 2, 14320 2, 14321 2, 14322 -1, 14323 -1, 14324 3, 14325 3, 14326 3, 14327 3, 14328 3, 14329 3, 14330 3, 14331 3, 14332 2, 14333 2, 14334 2, 14335 2, 14336 2, 14337 2, 14338 -1, 14339 -1, 14340 3, 14341 3, 14342 3, 14343 3, 14344 3, 14345 3, 14346 3, 14347 3, 14348 2, 14349 2, 14350 2, 14351 2, 14352 2, 14353 2, 14354 -1, 14355 -1, 14356 3, 14357 3, 14358 3, 14359 3, 14360 3, 14361 3, 14362 3, 14363 3, 14364 2, 14365 2, 14366 2, 14367 2, 14368 2, 14369 2, 14370 -1, 14371 -1, 14372 3, 14373 3, 14374 3, 14375 3, 14376 3, 14377 3, 14378 3, 14379 3, 14380 2, 14381 2, 14382 2, 14383 2, 14384 2, 14385 2, 14386 -1, 14387 -1, 14388 3, 14389 3, 14390 3, 14391 3, 14392 3, 14393 3, 14394 3, 14395 3, 14396 2, 14397 2, 14398 2, 14399 2, 14400 2, 14401 2, 14402 -1, 14403 -1, 14404 3, 14405 3, 14406 3, 14407 3, 14408 3, 14409 3, 14410 3, 14411 3, 14412 2, 14413 2, 14414 2, 14415 2, 14416 2, 14417 2, 14418 -1, 14419 -1, 14420 3, 14421 3, 14422 3, 14423 3, 14424 3, 14425 3, 14426 3, 14427 3, 14428 2, 14429 2, 14430 2, 14431 2, 14432 2, 14433 2, 14434 -1, 14435 -1, 14436 3, 14437 3, 14438 3, 14439 3, 14440 3, 14441 3, 14442 3, 14443 3, 14444 2, 14445 2, 14446 2, 14447 2, 14448 2, 14449 2, 14450 -1, 14451 -1, 14452 3, 14453 3, 14454 3, 14455 3, 14456 3, 14457 3, 14458 3, 14459 3, 14460 2, 14461 2, 14462 2, 14463 2, 14464 2, 14465 2, 14466 -1, 14467 -1, 14468 3, 14469 3, 14470 3, 14471 3, 14472 3, 14473 3, 14474 3, 14475 3, 14476 2, 14477 2, 14478 2, 14479 2, 14480 2, 14481 2, 14482 -1, 14483 -1, 14484 3, 14485 3, 14486 3, 14487 3, 14488 3, 14489 3, 14490 3, 14491 3, 14492 2, 14493 2, 14494 2, 14495 2, 14496 2, 14497 2, 14498 -1, 14499 -1, 14500 3, 14501 3, 14502 3, 14503 3, 14504 3, 14505 3, 14506 3, 14507 3, 14508 2, 14509 2, 14510 2, 14511 2, 14512 2, 14513 2, 14514 -1, 14515 -1 14516}; 14517 14518static int 14519length_decoder (const unsigned char *insn) 14520{ 14521 int l = insn[0]; 14522 return length_table[l]; 14523} 14524 14525 14526/* Top-level ISA structure. */ 14527 14528xtensa_isa_internal xtensa_modules = { 14529 0 /* little-endian */, 14530 3 /* insn_size */, 0, 14531 3, formats, format_decoder, length_decoder, 14532 3, slots, 14533 56 /* num_fields */, 14534 94, operands, 14535 313, iclasses, 14536 439, opcodes, 0, 14537 2, regfiles, 14538 NUM_STATES, states, 0, 14539 NUM_SYSREGS, sysregs, 0, 14540 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, 14541 6, interfaces, 0, 14542 0, funcUnits, 0 14543}; 14544