1 /* 2 * QEMU Xtensa CPU 3 * 4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * * Neither the name of the Open Source and Linux Lab nor the 16 * names of its contributors may be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qapi/error.h" 33 #include "cpu.h" 34 #include "qemu-common.h" 35 #include "migration/vmstate.h" 36 #include "exec/exec-all.h" 37 38 39 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) 40 { 41 XtensaCPU *cpu = XTENSA_CPU(cs); 42 43 cpu->env.pc = value; 44 } 45 46 static bool xtensa_cpu_has_work(CPUState *cs) 47 { 48 XtensaCPU *cpu = XTENSA_CPU(cs); 49 50 return cpu->env.pending_irq_level; 51 } 52 53 /* CPUClass::reset() */ 54 static void xtensa_cpu_reset(CPUState *s) 55 { 56 XtensaCPU *cpu = XTENSA_CPU(s); 57 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu); 58 CPUXtensaState *env = &cpu->env; 59 60 xcc->parent_reset(s); 61 62 env->exception_taken = 0; 63 env->pc = env->config->exception_vector[EXC_RESET]; 64 env->sregs[LITBASE] &= ~1; 65 env->sregs[PS] = xtensa_option_enabled(env->config, 66 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; 67 env->sregs[VECBASE] = env->config->vecbase; 68 env->sregs[IBREAKENABLE] = 0; 69 env->sregs[CACHEATTR] = 0x22222222; 70 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config, 71 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15; 72 env->sregs[CONFIGID0] = env->config->configid[0]; 73 env->sregs[CONFIGID1] = env->config->configid[1]; 74 75 env->pending_irq_level = 0; 76 reset_mmu(env); 77 } 78 79 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model) 80 { 81 ObjectClass *oc; 82 char *typename; 83 84 if (cpu_model == NULL) { 85 return NULL; 86 } 87 88 typename = g_strdup_printf("%s-" TYPE_XTENSA_CPU, cpu_model); 89 oc = object_class_by_name(typename); 90 g_free(typename); 91 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) || 92 object_class_is_abstract(oc)) { 93 return NULL; 94 } 95 return oc; 96 } 97 98 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp) 99 { 100 CPUState *cs = CPU(dev); 101 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev); 102 Error *local_err = NULL; 103 104 cpu_exec_realizefn(cs, &local_err); 105 if (local_err != NULL) { 106 error_propagate(errp, local_err); 107 return; 108 } 109 110 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs; 111 112 qemu_init_vcpu(cs); 113 114 xcc->parent_realize(dev, errp); 115 } 116 117 static void xtensa_cpu_initfn(Object *obj) 118 { 119 CPUState *cs = CPU(obj); 120 XtensaCPU *cpu = XTENSA_CPU(obj); 121 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); 122 CPUXtensaState *env = &cpu->env; 123 static bool tcg_inited; 124 125 cs->env_ptr = env; 126 env->config = xcc->config; 127 128 if (tcg_enabled() && !tcg_inited) { 129 tcg_inited = true; 130 xtensa_translate_init(); 131 } 132 } 133 134 static const VMStateDescription vmstate_xtensa_cpu = { 135 .name = "cpu", 136 .unmigratable = 1, 137 }; 138 139 static void xtensa_cpu_class_init(ObjectClass *oc, void *data) 140 { 141 DeviceClass *dc = DEVICE_CLASS(oc); 142 CPUClass *cc = CPU_CLASS(oc); 143 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc); 144 145 xcc->parent_realize = dc->realize; 146 dc->realize = xtensa_cpu_realizefn; 147 148 xcc->parent_reset = cc->reset; 149 cc->reset = xtensa_cpu_reset; 150 151 cc->class_by_name = xtensa_cpu_class_by_name; 152 cc->has_work = xtensa_cpu_has_work; 153 cc->do_interrupt = xtensa_cpu_do_interrupt; 154 cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt; 155 cc->dump_state = xtensa_cpu_dump_state; 156 cc->set_pc = xtensa_cpu_set_pc; 157 cc->gdb_read_register = xtensa_cpu_gdb_read_register; 158 cc->gdb_write_register = xtensa_cpu_gdb_write_register; 159 cc->gdb_stop_before_watchpoint = true; 160 #ifndef CONFIG_USER_ONLY 161 cc->do_unaligned_access = xtensa_cpu_do_unaligned_access; 162 cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; 163 cc->do_unassigned_access = xtensa_cpu_do_unassigned_access; 164 #endif 165 cc->debug_excp_handler = xtensa_breakpoint_handler; 166 dc->vmsd = &vmstate_xtensa_cpu; 167 } 168 169 static const TypeInfo xtensa_cpu_type_info = { 170 .name = TYPE_XTENSA_CPU, 171 .parent = TYPE_CPU, 172 .instance_size = sizeof(XtensaCPU), 173 .instance_init = xtensa_cpu_initfn, 174 .abstract = true, 175 .class_size = sizeof(XtensaCPUClass), 176 .class_init = xtensa_cpu_class_init, 177 }; 178 179 static void xtensa_cpu_register_types(void) 180 { 181 type_register_static(&xtensa_cpu_type_info); 182 } 183 184 type_init(xtensa_cpu_register_types) 185