xref: /qemu/target/xtensa/cpu.h (revision 33848cee) 
1 /*
2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *     * Redistributions of source code must retain the above copyright
8  *       notice, this list of conditions and the following disclaimer.
9  *     * Redistributions in binary form must reproduce the above copyright
10  *       notice, this list of conditions and the following disclaimer in the
11  *       documentation and/or other materials provided with the distribution.
12  *     * Neither the name of the Open Source and Linux Lab nor the
13  *       names of its contributors may be used to endorse or promote products
14  *       derived from this software without specific prior written permission.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  */
27 
28 #ifndef XTENSA_CPU_H
29 #define XTENSA_CPU_H
30 
31 #define ALIGNED_ONLY
32 #define TARGET_LONG_BITS 32
33 
34 #define CPUArchState struct CPUXtensaState
35 
36 #include "qemu-common.h"
37 #include "cpu-qom.h"
38 #include "exec/cpu-defs.h"
39 #include "fpu/softfloat.h"
40 
41 #define NB_MMU_MODES 4
42 
43 #define TARGET_PHYS_ADDR_SPACE_BITS 32
44 #define TARGET_VIRT_ADDR_SPACE_BITS 32
45 #define TARGET_PAGE_BITS 12
46 
47 enum {
48     /* Additional instructions */
49     XTENSA_OPTION_CODE_DENSITY,
50     XTENSA_OPTION_LOOP,
51     XTENSA_OPTION_EXTENDED_L32R,
52     XTENSA_OPTION_16_BIT_IMUL,
53     XTENSA_OPTION_32_BIT_IMUL,
54     XTENSA_OPTION_32_BIT_IMUL_HIGH,
55     XTENSA_OPTION_32_BIT_IDIV,
56     XTENSA_OPTION_MAC16,
57     XTENSA_OPTION_MISC_OP_NSA,
58     XTENSA_OPTION_MISC_OP_MINMAX,
59     XTENSA_OPTION_MISC_OP_SEXT,
60     XTENSA_OPTION_MISC_OP_CLAMPS,
61     XTENSA_OPTION_COPROCESSOR,
62     XTENSA_OPTION_BOOLEAN,
63     XTENSA_OPTION_FP_COPROCESSOR,
64     XTENSA_OPTION_MP_SYNCHRO,
65     XTENSA_OPTION_CONDITIONAL_STORE,
66     XTENSA_OPTION_ATOMCTL,
67     XTENSA_OPTION_DEPBITS,
68 
69     /* Interrupts and exceptions */
70     XTENSA_OPTION_EXCEPTION,
71     XTENSA_OPTION_RELOCATABLE_VECTOR,
72     XTENSA_OPTION_UNALIGNED_EXCEPTION,
73     XTENSA_OPTION_INTERRUPT,
74     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
75     XTENSA_OPTION_TIMER_INTERRUPT,
76 
77     /* Local memory */
78     XTENSA_OPTION_ICACHE,
79     XTENSA_OPTION_ICACHE_TEST,
80     XTENSA_OPTION_ICACHE_INDEX_LOCK,
81     XTENSA_OPTION_DCACHE,
82     XTENSA_OPTION_DCACHE_TEST,
83     XTENSA_OPTION_DCACHE_INDEX_LOCK,
84     XTENSA_OPTION_IRAM,
85     XTENSA_OPTION_IROM,
86     XTENSA_OPTION_DRAM,
87     XTENSA_OPTION_DROM,
88     XTENSA_OPTION_XLMI,
89     XTENSA_OPTION_HW_ALIGNMENT,
90     XTENSA_OPTION_MEMORY_ECC_PARITY,
91 
92     /* Memory protection and translation */
93     XTENSA_OPTION_REGION_PROTECTION,
94     XTENSA_OPTION_REGION_TRANSLATION,
95     XTENSA_OPTION_MMU,
96     XTENSA_OPTION_CACHEATTR,
97 
98     /* Other */
99     XTENSA_OPTION_WINDOWED_REGISTER,
100     XTENSA_OPTION_PROCESSOR_INTERFACE,
101     XTENSA_OPTION_MISC_SR,
102     XTENSA_OPTION_THREAD_POINTER,
103     XTENSA_OPTION_PROCESSOR_ID,
104     XTENSA_OPTION_DEBUG,
105     XTENSA_OPTION_TRACE_PORT,
106 };
107 
108 enum {
109     THREADPTR = 231,
110     FCR = 232,
111     FSR = 233,
112 };
113 
114 enum {
115     LBEG = 0,
116     LEND = 1,
117     LCOUNT = 2,
118     SAR = 3,
119     BR = 4,
120     LITBASE = 5,
121     SCOMPARE1 = 12,
122     ACCLO = 16,
123     ACCHI = 17,
124     MR = 32,
125     WINDOW_BASE = 72,
126     WINDOW_START = 73,
127     PTEVADDR = 83,
128     RASID = 90,
129     ITLBCFG = 91,
130     DTLBCFG = 92,
131     IBREAKENABLE = 96,
132     CACHEATTR = 98,
133     ATOMCTL = 99,
134     IBREAKA = 128,
135     DBREAKA = 144,
136     DBREAKC = 160,
137     CONFIGID0 = 176,
138     EPC1 = 177,
139     DEPC = 192,
140     EPS2 = 194,
141     CONFIGID1 = 208,
142     EXCSAVE1 = 209,
143     CPENABLE = 224,
144     INTSET = 226,
145     INTCLEAR = 227,
146     INTENABLE = 228,
147     PS = 230,
148     VECBASE = 231,
149     EXCCAUSE = 232,
150     DEBUGCAUSE = 233,
151     CCOUNT = 234,
152     PRID = 235,
153     ICOUNT = 236,
154     ICOUNTLEVEL = 237,
155     EXCVADDR = 238,
156     CCOMPARE = 240,
157     MISC = 244,
158 };
159 
160 #define PS_INTLEVEL 0xf
161 #define PS_INTLEVEL_SHIFT 0
162 
163 #define PS_EXCM 0x10
164 #define PS_UM 0x20
165 
166 #define PS_RING 0xc0
167 #define PS_RING_SHIFT 6
168 
169 #define PS_OWB 0xf00
170 #define PS_OWB_SHIFT 8
171 
172 #define PS_CALLINC 0x30000
173 #define PS_CALLINC_SHIFT 16
174 #define PS_CALLINC_LEN 2
175 
176 #define PS_WOE 0x40000
177 
178 #define DEBUGCAUSE_IC 0x1
179 #define DEBUGCAUSE_IB 0x2
180 #define DEBUGCAUSE_DB 0x4
181 #define DEBUGCAUSE_BI 0x8
182 #define DEBUGCAUSE_BN 0x10
183 #define DEBUGCAUSE_DI 0x20
184 #define DEBUGCAUSE_DBNUM 0xf00
185 #define DEBUGCAUSE_DBNUM_SHIFT 8
186 
187 #define DBREAKC_SB 0x80000000
188 #define DBREAKC_LB 0x40000000
189 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
190 #define DBREAKC_MASK 0x3f
191 
192 #define MAX_NAREG 64
193 #define MAX_NINTERRUPT 32
194 #define MAX_NLEVEL 6
195 #define MAX_NNMI 1
196 #define MAX_NCCOMPARE 3
197 #define MAX_TLB_WAY_SIZE 8
198 #define MAX_NDBREAK 2
199 
200 #define REGION_PAGE_MASK 0xe0000000
201 
202 #define PAGE_CACHE_MASK    0x700
203 #define PAGE_CACHE_SHIFT   8
204 #define PAGE_CACHE_INVALID 0x000
205 #define PAGE_CACHE_BYPASS  0x100
206 #define PAGE_CACHE_WT      0x200
207 #define PAGE_CACHE_WB      0x400
208 #define PAGE_CACHE_ISOLATE 0x600
209 
210 enum {
211     /* Static vectors */
212     EXC_RESET,
213     EXC_MEMORY_ERROR,
214 
215     /* Dynamic vectors */
216     EXC_WINDOW_OVERFLOW4,
217     EXC_WINDOW_UNDERFLOW4,
218     EXC_WINDOW_OVERFLOW8,
219     EXC_WINDOW_UNDERFLOW8,
220     EXC_WINDOW_OVERFLOW12,
221     EXC_WINDOW_UNDERFLOW12,
222     EXC_IRQ,
223     EXC_KERNEL,
224     EXC_USER,
225     EXC_DOUBLE,
226     EXC_DEBUG,
227     EXC_MAX
228 };
229 
230 enum {
231     ILLEGAL_INSTRUCTION_CAUSE = 0,
232     SYSCALL_CAUSE,
233     INSTRUCTION_FETCH_ERROR_CAUSE,
234     LOAD_STORE_ERROR_CAUSE,
235     LEVEL1_INTERRUPT_CAUSE,
236     ALLOCA_CAUSE,
237     INTEGER_DIVIDE_BY_ZERO_CAUSE,
238     PRIVILEGED_CAUSE = 8,
239     LOAD_STORE_ALIGNMENT_CAUSE,
240 
241     INSTR_PIF_DATA_ERROR_CAUSE = 12,
242     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
243     INSTR_PIF_ADDR_ERROR_CAUSE,
244     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
245 
246     INST_TLB_MISS_CAUSE,
247     INST_TLB_MULTI_HIT_CAUSE,
248     INST_FETCH_PRIVILEGE_CAUSE,
249     INST_FETCH_PROHIBITED_CAUSE = 20,
250     LOAD_STORE_TLB_MISS_CAUSE = 24,
251     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
252     LOAD_STORE_PRIVILEGE_CAUSE,
253     LOAD_PROHIBITED_CAUSE = 28,
254     STORE_PROHIBITED_CAUSE,
255 
256     COPROCESSOR0_DISABLED = 32,
257 };
258 
259 typedef enum {
260     INTTYPE_LEVEL,
261     INTTYPE_EDGE,
262     INTTYPE_NMI,
263     INTTYPE_SOFTWARE,
264     INTTYPE_TIMER,
265     INTTYPE_DEBUG,
266     INTTYPE_WRITE_ERR,
267     INTTYPE_PROFILING,
268     INTTYPE_MAX
269 } interrupt_type;
270 
271 typedef struct xtensa_tlb_entry {
272     uint32_t vaddr;
273     uint32_t paddr;
274     uint8_t asid;
275     uint8_t attr;
276     bool variable;
277 } xtensa_tlb_entry;
278 
279 typedef struct xtensa_tlb {
280     unsigned nways;
281     const unsigned way_size[10];
282     bool varway56;
283     unsigned nrefillentries;
284 } xtensa_tlb;
285 
286 typedef struct XtensaGdbReg {
287     int targno;
288     int type;
289     int group;
290     unsigned size;
291 } XtensaGdbReg;
292 
293 typedef struct XtensaGdbRegmap {
294     int num_regs;
295     int num_core_regs;
296     /* PC + a + ar + sr + ur */
297     XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
298 } XtensaGdbRegmap;
299 
300 struct XtensaConfig {
301     const char *name;
302     uint64_t options;
303     XtensaGdbRegmap gdb_regmap;
304     unsigned nareg;
305     int excm_level;
306     int ndepc;
307     uint32_t vecbase;
308     uint32_t exception_vector[EXC_MAX];
309     unsigned ninterrupt;
310     unsigned nlevel;
311     uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
312     uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
313     uint32_t inttype_mask[INTTYPE_MAX];
314     struct {
315         uint32_t level;
316         interrupt_type inttype;
317     } interrupt[MAX_NINTERRUPT];
318     unsigned nccompare;
319     uint32_t timerint[MAX_NCCOMPARE];
320     unsigned nextint;
321     unsigned extint[MAX_NINTERRUPT];
322 
323     unsigned debug_level;
324     unsigned nibreak;
325     unsigned ndbreak;
326 
327     uint32_t configid[2];
328 
329     uint32_t clock_freq_khz;
330 
331     xtensa_tlb itlb;
332     xtensa_tlb dtlb;
333 };
334 
335 typedef struct XtensaConfigList {
336     const XtensaConfig *config;
337     struct XtensaConfigList *next;
338 } XtensaConfigList;
339 
340 #ifdef HOST_WORDS_BIGENDIAN
341 enum {
342     FP_F32_HIGH,
343     FP_F32_LOW,
344 };
345 #else
346 enum {
347     FP_F32_LOW,
348     FP_F32_HIGH,
349 };
350 #endif
351 
352 typedef struct CPUXtensaState {
353     const XtensaConfig *config;
354     uint32_t regs[16];
355     uint32_t pc;
356     uint32_t sregs[256];
357     uint32_t uregs[256];
358     uint32_t phys_regs[MAX_NAREG];
359     union {
360         float32 f32[2];
361         float64 f64;
362     } fregs[16];
363     float_status fp_status;
364 
365     xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
366     xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
367     unsigned autorefill_idx;
368 
369     int pending_irq_level; /* level of last raised IRQ */
370     void **irq_inputs;
371     QEMUTimer *ccompare_timer;
372     uint32_t wake_ccount;
373     int64_t halt_clock;
374 
375     int exception_taken;
376 
377     /* Watchpoints for DBREAK registers */
378     struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
379 
380     CPU_COMMON
381 } CPUXtensaState;
382 
383 /**
384  * XtensaCPU:
385  * @env: #CPUXtensaState
386  *
387  * An Xtensa CPU.
388  */
389 struct XtensaCPU {
390     /*< private >*/
391     CPUState parent_obj;
392     /*< public >*/
393 
394     CPUXtensaState env;
395 };
396 
397 static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
398 {
399     return container_of(env, XtensaCPU, env);
400 }
401 
402 #define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e))
403 
404 #define ENV_OFFSET offsetof(XtensaCPU, env)
405 
406 void xtensa_cpu_do_interrupt(CPUState *cpu);
407 bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request);
408 void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr,
409                                      bool is_write, bool is_exec, int opaque,
410                                      unsigned size);
411 void xtensa_cpu_dump_state(CPUState *cpu, FILE *f,
412                            fprintf_function cpu_fprintf, int flags);
413 hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
414 int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
415 int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
416 void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
417                                     MMUAccessType access_type,
418                                     int mmu_idx, uintptr_t retaddr);
419 
420 #define cpu_signal_handler cpu_xtensa_signal_handler
421 #define cpu_list xtensa_cpu_list
422 
423 #ifdef TARGET_WORDS_BIGENDIAN
424 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
425 #else
426 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
427 #endif
428 
429 XtensaCPU *cpu_xtensa_init(const char *cpu_model);
430 
431 #define cpu_init(cpu_model) CPU(cpu_xtensa_init(cpu_model))
432 
433 void xtensa_translate_init(void);
434 void xtensa_breakpoint_handler(CPUState *cs);
435 void xtensa_finalize_config(XtensaConfig *config);
436 void xtensa_register_core(XtensaConfigList *node);
437 void check_interrupts(CPUXtensaState *s);
438 void xtensa_irq_init(CPUXtensaState *env);
439 void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
440 void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
441 void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
442 void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
443 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
444 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
445 void xtensa_sync_window_from_phys(CPUXtensaState *env);
446 void xtensa_sync_phys_from_window(CPUXtensaState *env);
447 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
448 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
449         uint32_t *vpn, uint32_t wi, uint32_t *ei);
450 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
451         uint32_t *pwi, uint32_t *pei, uint8_t *pring);
452 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
453         xtensa_tlb_entry *entry, bool dtlb,
454         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
455 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
456         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
457 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
458         uint32_t vaddr, int is_write, int mmu_idx,
459         uint32_t *paddr, uint32_t *page_size, unsigned *access);
460 void reset_mmu(CPUXtensaState *env);
461 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
462 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
463 
464 
465 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
466 #define XTENSA_OPTION_ALL (~(uint64_t)0)
467 
468 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
469         uint64_t opt)
470 {
471     return (config->options & opt) != 0;
472 }
473 
474 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
475 {
476     return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
477 }
478 
479 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
480 {
481     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
482     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
483         level = env->config->excm_level;
484     }
485     return level;
486 }
487 
488 static inline int xtensa_get_ring(const CPUXtensaState *env)
489 {
490     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
491         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
492     } else {
493         return 0;
494     }
495 }
496 
497 static inline int xtensa_get_cring(const CPUXtensaState *env)
498 {
499     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
500             (env->sregs[PS] & PS_EXCM) == 0) {
501         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
502     } else {
503         return 0;
504     }
505 }
506 
507 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
508         bool dtlb, unsigned wi, unsigned ei)
509 {
510     return dtlb ?
511         env->dtlb[wi] + ei :
512         env->itlb[wi] + ei;
513 }
514 
515 static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
516 {
517     return env->sregs[WINDOW_START] |
518         (env->sregs[WINDOW_START] << env->config->nareg / 4);
519 }
520 
521 /* MMU modes definitions */
522 #define MMU_MODE0_SUFFIX _ring0
523 #define MMU_MODE1_SUFFIX _ring1
524 #define MMU_MODE2_SUFFIX _ring2
525 #define MMU_MODE3_SUFFIX _ring3
526 
527 static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
528 {
529     return xtensa_get_cring(env);
530 }
531 
532 #define XTENSA_TBFLAG_RING_MASK 0x3
533 #define XTENSA_TBFLAG_EXCM 0x4
534 #define XTENSA_TBFLAG_LITBASE 0x8
535 #define XTENSA_TBFLAG_DEBUG 0x10
536 #define XTENSA_TBFLAG_ICOUNT 0x20
537 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
538 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
539 #define XTENSA_TBFLAG_EXCEPTION 0x4000
540 #define XTENSA_TBFLAG_WINDOW_MASK 0x18000
541 #define XTENSA_TBFLAG_WINDOW_SHIFT 15
542 
543 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
544         target_ulong *cs_base, uint32_t *flags)
545 {
546     CPUState *cs = CPU(xtensa_env_get_cpu(env));
547 
548     *pc = env->pc;
549     *cs_base = 0;
550     *flags = 0;
551     *flags |= xtensa_get_ring(env);
552     if (env->sregs[PS] & PS_EXCM) {
553         *flags |= XTENSA_TBFLAG_EXCM;
554     }
555     if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
556             (env->sregs[LITBASE] & 1)) {
557         *flags |= XTENSA_TBFLAG_LITBASE;
558     }
559     if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
560         if (xtensa_get_cintlevel(env) < env->config->debug_level) {
561             *flags |= XTENSA_TBFLAG_DEBUG;
562         }
563         if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
564             *flags |= XTENSA_TBFLAG_ICOUNT;
565         }
566     }
567     if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
568         *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
569     }
570     if (cs->singlestep_enabled && env->exception_taken) {
571         *flags |= XTENSA_TBFLAG_EXCEPTION;
572     }
573     if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
574         (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
575         uint32_t windowstart = xtensa_replicate_windowstart(env) >>
576             (env->sregs[WINDOW_BASE] + 1);
577         uint32_t w = ctz32(windowstart | 0x8);
578 
579         *flags |= w << XTENSA_TBFLAG_WINDOW_SHIFT;
580     } else {
581         *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
582     }
583 }
584 
585 #include "exec/cpu-all.h"
586 
587 #endif
588