1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef I386_TCG_TARGET_H 26 #define I386_TCG_TARGET_H 27 28 #define TCG_TARGET_INSN_UNIT_SIZE 1 29 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 31 30 31 #ifdef __x86_64__ 32 # define TCG_TARGET_REG_BITS 64 33 # define TCG_TARGET_NB_REGS 16 34 #else 35 # define TCG_TARGET_REG_BITS 32 36 # define TCG_TARGET_NB_REGS 8 37 #endif 38 39 typedef enum { 40 TCG_REG_EAX = 0, 41 TCG_REG_ECX, 42 TCG_REG_EDX, 43 TCG_REG_EBX, 44 TCG_REG_ESP, 45 TCG_REG_EBP, 46 TCG_REG_ESI, 47 TCG_REG_EDI, 48 49 /* 64-bit registers; always define the symbols to avoid 50 too much if-deffing. */ 51 TCG_REG_R8, 52 TCG_REG_R9, 53 TCG_REG_R10, 54 TCG_REG_R11, 55 TCG_REG_R12, 56 TCG_REG_R13, 57 TCG_REG_R14, 58 TCG_REG_R15, 59 TCG_REG_RAX = TCG_REG_EAX, 60 TCG_REG_RCX = TCG_REG_ECX, 61 TCG_REG_RDX = TCG_REG_EDX, 62 TCG_REG_RBX = TCG_REG_EBX, 63 TCG_REG_RSP = TCG_REG_ESP, 64 TCG_REG_RBP = TCG_REG_EBP, 65 TCG_REG_RSI = TCG_REG_ESI, 66 TCG_REG_RDI = TCG_REG_EDI, 67 } TCGReg; 68 69 /* used for function call generation */ 70 #define TCG_REG_CALL_STACK TCG_REG_ESP 71 #define TCG_TARGET_STACK_ALIGN 16 72 #if defined(_WIN64) 73 #define TCG_TARGET_CALL_STACK_OFFSET 32 74 #else 75 #define TCG_TARGET_CALL_STACK_OFFSET 0 76 #endif 77 78 extern bool have_bmi1; 79 80 /* optional instructions */ 81 #define TCG_TARGET_HAS_div2_i32 1 82 #define TCG_TARGET_HAS_rot_i32 1 83 #define TCG_TARGET_HAS_ext8s_i32 1 84 #define TCG_TARGET_HAS_ext16s_i32 1 85 #define TCG_TARGET_HAS_ext8u_i32 1 86 #define TCG_TARGET_HAS_ext16u_i32 1 87 #define TCG_TARGET_HAS_bswap16_i32 1 88 #define TCG_TARGET_HAS_bswap32_i32 1 89 #define TCG_TARGET_HAS_neg_i32 1 90 #define TCG_TARGET_HAS_not_i32 1 91 #define TCG_TARGET_HAS_andc_i32 have_bmi1 92 #define TCG_TARGET_HAS_orc_i32 0 93 #define TCG_TARGET_HAS_eqv_i32 0 94 #define TCG_TARGET_HAS_nand_i32 0 95 #define TCG_TARGET_HAS_nor_i32 0 96 #define TCG_TARGET_HAS_deposit_i32 1 97 #define TCG_TARGET_HAS_movcond_i32 1 98 #define TCG_TARGET_HAS_add2_i32 1 99 #define TCG_TARGET_HAS_sub2_i32 1 100 #define TCG_TARGET_HAS_mulu2_i32 1 101 #define TCG_TARGET_HAS_muls2_i32 1 102 #define TCG_TARGET_HAS_muluh_i32 0 103 #define TCG_TARGET_HAS_mulsh_i32 0 104 105 #if TCG_TARGET_REG_BITS == 64 106 #define TCG_TARGET_HAS_extrl_i64_i32 0 107 #define TCG_TARGET_HAS_extrh_i64_i32 0 108 #define TCG_TARGET_HAS_div2_i64 1 109 #define TCG_TARGET_HAS_rot_i64 1 110 #define TCG_TARGET_HAS_ext8s_i64 1 111 #define TCG_TARGET_HAS_ext16s_i64 1 112 #define TCG_TARGET_HAS_ext32s_i64 1 113 #define TCG_TARGET_HAS_ext8u_i64 1 114 #define TCG_TARGET_HAS_ext16u_i64 1 115 #define TCG_TARGET_HAS_ext32u_i64 1 116 #define TCG_TARGET_HAS_bswap16_i64 1 117 #define TCG_TARGET_HAS_bswap32_i64 1 118 #define TCG_TARGET_HAS_bswap64_i64 1 119 #define TCG_TARGET_HAS_neg_i64 1 120 #define TCG_TARGET_HAS_not_i64 1 121 #define TCG_TARGET_HAS_andc_i64 have_bmi1 122 #define TCG_TARGET_HAS_orc_i64 0 123 #define TCG_TARGET_HAS_eqv_i64 0 124 #define TCG_TARGET_HAS_nand_i64 0 125 #define TCG_TARGET_HAS_nor_i64 0 126 #define TCG_TARGET_HAS_deposit_i64 1 127 #define TCG_TARGET_HAS_movcond_i64 1 128 #define TCG_TARGET_HAS_add2_i64 1 129 #define TCG_TARGET_HAS_sub2_i64 1 130 #define TCG_TARGET_HAS_mulu2_i64 1 131 #define TCG_TARGET_HAS_muls2_i64 1 132 #define TCG_TARGET_HAS_muluh_i64 0 133 #define TCG_TARGET_HAS_mulsh_i64 0 134 #endif 135 136 #define TCG_TARGET_deposit_i32_valid(ofs, len) \ 137 (((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \ 138 ((ofs) == 0 && (len) == 16)) 139 #define TCG_TARGET_deposit_i64_valid TCG_TARGET_deposit_i32_valid 140 141 #if TCG_TARGET_REG_BITS == 64 142 # define TCG_AREG0 TCG_REG_R14 143 #else 144 # define TCG_AREG0 TCG_REG_EBP 145 #endif 146 147 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) 148 { 149 } 150 151 #endif 152