1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.c.inc 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 11 * Copyright (c) 2008 Fabrice Bellard 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a copy 14 * of this software and associated documentation files (the "Software"), to deal 15 * in the Software without restriction, including without limitation the rights 16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 * copies of the Software, and to permit persons to whom the Software is 18 * furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 * THE SOFTWARE. 30 */ 31 32#include "../tcg-ldst.c.inc" 33 34#ifdef CONFIG_DEBUG_TCG 35static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 36 "zero", 37 "ra", 38 "tp", 39 "sp", 40 "a0", 41 "a1", 42 "a2", 43 "a3", 44 "a4", 45 "a5", 46 "a6", 47 "a7", 48 "t0", 49 "t1", 50 "t2", 51 "t3", 52 "t4", 53 "t5", 54 "t6", 55 "t7", 56 "t8", 57 "r21", /* reserved in the LP64* ABI, hence no ABI name */ 58 "s9", 59 "s0", 60 "s1", 61 "s2", 62 "s3", 63 "s4", 64 "s5", 65 "s6", 66 "s7", 67 "s8" 68}; 69#endif 70 71static const int tcg_target_reg_alloc_order[] = { 72 /* Registers preserved across calls */ 73 /* TCG_REG_S0 reserved for TCG_AREG0 */ 74 TCG_REG_S1, 75 TCG_REG_S2, 76 TCG_REG_S3, 77 TCG_REG_S4, 78 TCG_REG_S5, 79 TCG_REG_S6, 80 TCG_REG_S7, 81 TCG_REG_S8, 82 TCG_REG_S9, 83 84 /* Registers (potentially) clobbered across calls */ 85 TCG_REG_T0, 86 TCG_REG_T1, 87 TCG_REG_T2, 88 TCG_REG_T3, 89 TCG_REG_T4, 90 TCG_REG_T5, 91 TCG_REG_T6, 92 TCG_REG_T7, 93 TCG_REG_T8, 94 95 /* Argument registers, opposite order of allocation. */ 96 TCG_REG_A7, 97 TCG_REG_A6, 98 TCG_REG_A5, 99 TCG_REG_A4, 100 TCG_REG_A3, 101 TCG_REG_A2, 102 TCG_REG_A1, 103 TCG_REG_A0, 104}; 105 106static const int tcg_target_call_iarg_regs[] = { 107 TCG_REG_A0, 108 TCG_REG_A1, 109 TCG_REG_A2, 110 TCG_REG_A3, 111 TCG_REG_A4, 112 TCG_REG_A5, 113 TCG_REG_A6, 114 TCG_REG_A7, 115}; 116 117static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 118{ 119 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 120 tcg_debug_assert(slot >= 0 && slot <= 1); 121 return TCG_REG_A0 + slot; 122} 123 124#ifndef CONFIG_SOFTMMU 125#define USE_GUEST_BASE (guest_base != 0) 126#define TCG_GUEST_BASE_REG TCG_REG_S1 127#endif 128 129#define TCG_CT_CONST_ZERO 0x100 130#define TCG_CT_CONST_S12 0x200 131#define TCG_CT_CONST_S32 0x400 132#define TCG_CT_CONST_U12 0x800 133#define TCG_CT_CONST_C12 0x1000 134#define TCG_CT_CONST_WSZ 0x2000 135 136#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 137/* 138 * For softmmu, we need to avoid conflicts with the first 5 139 * argument registers to call the helper. Some of these are 140 * also used for the tlb lookup. 141 */ 142#ifdef CONFIG_SOFTMMU 143#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) 144#else 145#define SOFTMMU_RESERVE_REGS 0 146#endif 147 148 149static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 150{ 151 return sextract64(val, pos, len); 152} 153 154/* test if a constant matches the constraint */ 155static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 156{ 157 if (ct & TCG_CT_CONST) { 158 return true; 159 } 160 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 161 return true; 162 } 163 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { 164 return true; 165 } 166 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 167 return true; 168 } 169 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { 170 return true; 171 } 172 if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) { 173 return true; 174 } 175 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 176 return true; 177 } 178 return false; 179} 180 181/* 182 * Relocations 183 */ 184 185/* 186 * Relocation records defined in LoongArch ELF psABI v1.00 is way too 187 * complicated; a whopping stack machine is needed to stuff the fields, at 188 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are 189 * needed. 190 * 191 * Hence, define our own simpler relocation types. Numbers are chosen as to 192 * not collide with potential future additions to the true ELF relocation 193 * type enum. 194 */ 195 196/* Field Sk16, shifted right by 2; suitable for conditional jumps */ 197#define R_LOONGARCH_BR_SK16 256 198/* Field Sd10k16, shifted right by 2; suitable for B and BL */ 199#define R_LOONGARCH_BR_SD10K16 257 200 201static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 202{ 203 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 204 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 205 206 tcg_debug_assert((offset & 3) == 0); 207 offset >>= 2; 208 if (offset == sextreg(offset, 0, 16)) { 209 *src_rw = deposit64(*src_rw, 10, 16, offset); 210 return true; 211 } 212 213 return false; 214} 215 216static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, 217 const tcg_insn_unit *target) 218{ 219 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 220 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 221 222 tcg_debug_assert((offset & 3) == 0); 223 offset >>= 2; 224 if (offset == sextreg(offset, 0, 26)) { 225 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ 226 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ 227 return true; 228 } 229 230 return false; 231} 232 233static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 234 intptr_t value, intptr_t addend) 235{ 236 tcg_debug_assert(addend == 0); 237 switch (type) { 238 case R_LOONGARCH_BR_SK16: 239 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); 240 case R_LOONGARCH_BR_SD10K16: 241 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); 242 default: 243 g_assert_not_reached(); 244 } 245} 246 247#include "tcg-insn-defs.c.inc" 248 249/* 250 * TCG intrinsics 251 */ 252 253static void tcg_out_mb(TCGContext *s, TCGArg a0) 254{ 255 /* Baseline LoongArch only has the full barrier, unfortunately. */ 256 tcg_out_opc_dbar(s, 0); 257} 258 259static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 260{ 261 if (ret == arg) { 262 return true; 263 } 264 switch (type) { 265 case TCG_TYPE_I32: 266 case TCG_TYPE_I64: 267 /* 268 * Conventional register-register move used in LoongArch is 269 * `or dst, src, zero`. 270 */ 271 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); 272 break; 273 default: 274 g_assert_not_reached(); 275 } 276 return true; 277} 278 279/* Loads a 32-bit immediate into rd, sign-extended. */ 280static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) 281{ 282 tcg_target_long lo = sextreg(val, 0, 12); 283 tcg_target_long hi12 = sextreg(val, 12, 20); 284 285 /* Single-instruction cases. */ 286 if (hi12 == 0) { 287 /* val fits in uimm12: ori rd, zero, val */ 288 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); 289 return; 290 } 291 if (hi12 == sextreg(lo, 12, 20)) { 292 /* val fits in simm12: addi.w rd, zero, val */ 293 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); 294 return; 295 } 296 297 /* High bits must be set; load with lu12i.w + optional ori. */ 298 tcg_out_opc_lu12i_w(s, rd, hi12); 299 if (lo != 0) { 300 tcg_out_opc_ori(s, rd, rd, lo & 0xfff); 301 } 302} 303 304static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 305 tcg_target_long val) 306{ 307 /* 308 * LoongArch conventionally loads 64-bit immediates in at most 4 steps, 309 * with dedicated instructions for filling the respective bitfields 310 * below: 311 * 312 * 6 5 4 3 313 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 314 * +-----------------------+---------------------------------------+... 315 * | hi52 | hi32 | 316 * +-----------------------+---------------------------------------+... 317 * 3 2 1 318 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 319 * ...+-------------------------------------+-------------------------+ 320 * | hi12 | lo | 321 * ...+-------------------------------------+-------------------------+ 322 * 323 * Check if val belong to one of the several fast cases, before falling 324 * back to the slow path. 325 */ 326 327 intptr_t pc_offset; 328 tcg_target_long val_lo, val_hi, pc_hi, offset_hi; 329 tcg_target_long hi12, hi32, hi52; 330 331 /* Value fits in signed i32. */ 332 if (type == TCG_TYPE_I32 || val == (int32_t)val) { 333 tcg_out_movi_i32(s, rd, val); 334 return; 335 } 336 337 /* PC-relative cases. */ 338 pc_offset = tcg_pcrel_diff(s, (void *)val); 339 if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) { 340 /* Single pcaddu2i. */ 341 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); 342 return; 343 } 344 345 if (pc_offset == (int32_t)pc_offset) { 346 /* Offset within 32 bits; load with pcalau12i + ori. */ 347 val_lo = sextreg(val, 0, 12); 348 val_hi = val >> 12; 349 pc_hi = (val - pc_offset) >> 12; 350 offset_hi = val_hi - pc_hi; 351 352 tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20)); 353 tcg_out_opc_pcalau12i(s, rd, offset_hi); 354 if (val_lo != 0) { 355 tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff); 356 } 357 return; 358 } 359 360 hi12 = sextreg(val, 12, 20); 361 hi32 = sextreg(val, 32, 20); 362 hi52 = sextreg(val, 52, 12); 363 364 /* Single cu52i.d case. */ 365 if ((hi52 != 0) && (ctz64(val) >= 52)) { 366 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); 367 return; 368 } 369 370 /* Slow path. Initialize the low 32 bits, then concat high bits. */ 371 tcg_out_movi_i32(s, rd, val); 372 373 /* Load hi32 and hi52 explicitly when they are unexpected values. */ 374 if (hi32 != sextreg(hi12, 20, 20)) { 375 tcg_out_opc_cu32i_d(s, rd, hi32); 376 } 377 378 if (hi52 != sextreg(hi32, 20, 12)) { 379 tcg_out_opc_cu52i_d(s, rd, rd, hi52); 380 } 381} 382 383static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd, 384 TCGReg rs, tcg_target_long imm) 385{ 386 tcg_target_long lo12 = sextreg(imm, 0, 12); 387 tcg_target_long hi16 = sextreg(imm - lo12, 16, 16); 388 389 /* 390 * Note that there's a hole in between hi16 and lo12: 391 * 392 * 3 2 1 0 393 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 394 * ...+-------------------------------+-------+-----------------------+ 395 * | hi16 | | lo12 | 396 * ...+-------------------------------+-------+-----------------------+ 397 * 398 * For bits within that hole, it's more efficient to use LU12I and ADD. 399 */ 400 if (imm == (hi16 << 16) + lo12) { 401 if (hi16) { 402 tcg_out_opc_addu16i_d(s, rd, rs, hi16); 403 rs = rd; 404 } 405 if (type == TCG_TYPE_I32) { 406 tcg_out_opc_addi_w(s, rd, rs, lo12); 407 } else if (lo12) { 408 tcg_out_opc_addi_d(s, rd, rs, lo12); 409 } else { 410 tcg_out_mov(s, type, rd, rs); 411 } 412 } else { 413 tcg_out_movi(s, type, TCG_REG_TMP0, imm); 414 if (type == TCG_TYPE_I32) { 415 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0); 416 } else { 417 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0); 418 } 419 } 420} 421 422static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 423{ 424 return false; 425} 426 427static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 428 tcg_target_long imm) 429{ 430 /* This function is only used for passing structs by reference. */ 431 g_assert_not_reached(); 432} 433 434static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 435{ 436 tcg_out_opc_andi(s, ret, arg, 0xff); 437} 438 439static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 440{ 441 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); 442} 443 444static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 445{ 446 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); 447} 448 449static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 450{ 451 tcg_out_opc_sext_b(s, ret, arg); 452} 453 454static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 455{ 456 tcg_out_opc_sext_h(s, ret, arg); 457} 458 459static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 460{ 461 tcg_out_opc_addi_w(s, ret, arg, 0); 462} 463 464static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 465{ 466 if (ret != arg) { 467 tcg_out_ext32s(s, ret, arg); 468 } 469} 470 471static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 472{ 473 tcg_out_ext32u(s, ret, arg); 474} 475 476static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 477{ 478 tcg_out_ext32s(s, ret, arg); 479} 480 481static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, 482 TCGReg a0, TCGReg a1, TCGReg a2, 483 bool c2, bool is_32bit) 484{ 485 if (c2) { 486 /* 487 * Fast path: semantics already satisfied due to constraint and 488 * insn behavior, single instruction is enough. 489 */ 490 tcg_debug_assert(a2 == (is_32bit ? 32 : 64)); 491 /* all clz/ctz insns belong to DJ-format */ 492 tcg_out32(s, encode_dj_insn(opc, a0, a1)); 493 return; 494 } 495 496 tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1)); 497 /* a0 = a1 ? REG_TMP0 : a2 */ 498 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 499 tcg_out_opc_masknez(s, a0, a2, a1); 500 tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); 501} 502 503#define SETCOND_INV TCG_TARGET_NB_REGS 504#define SETCOND_NEZ (SETCOND_INV << 1) 505#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 506 507static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 508 TCGReg arg1, tcg_target_long arg2, bool c2) 509{ 510 int flags = 0; 511 512 switch (cond) { 513 case TCG_COND_EQ: /* -> NE */ 514 case TCG_COND_GE: /* -> LT */ 515 case TCG_COND_GEU: /* -> LTU */ 516 case TCG_COND_GT: /* -> LE */ 517 case TCG_COND_GTU: /* -> LEU */ 518 cond = tcg_invert_cond(cond); 519 flags ^= SETCOND_INV; 520 break; 521 default: 522 break; 523 } 524 525 switch (cond) { 526 case TCG_COND_LE: 527 case TCG_COND_LEU: 528 /* 529 * If we have a constant input, the most efficient way to implement 530 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 531 * We don't need to care for this for LE because the constant input 532 * is still constrained to int32_t, and INT32_MAX+1 is representable 533 * in the 64-bit temporary register. 534 */ 535 if (c2) { 536 if (cond == TCG_COND_LEU) { 537 /* unsigned <= -1 is true */ 538 if (arg2 == -1) { 539 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 540 return ret; 541 } 542 cond = TCG_COND_LTU; 543 } else { 544 cond = TCG_COND_LT; 545 } 546 arg2 += 1; 547 } else { 548 TCGReg tmp = arg2; 549 arg2 = arg1; 550 arg1 = tmp; 551 cond = tcg_swap_cond(cond); /* LE -> GE */ 552 cond = tcg_invert_cond(cond); /* GE -> LT */ 553 flags ^= SETCOND_INV; 554 } 555 break; 556 default: 557 break; 558 } 559 560 switch (cond) { 561 case TCG_COND_NE: 562 flags |= SETCOND_NEZ; 563 if (!c2) { 564 tcg_out_opc_xor(s, ret, arg1, arg2); 565 } else if (arg2 == 0) { 566 ret = arg1; 567 } else if (arg2 >= 0 && arg2 <= 0xfff) { 568 tcg_out_opc_xori(s, ret, arg1, arg2); 569 } else { 570 tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2); 571 } 572 break; 573 574 case TCG_COND_LT: 575 case TCG_COND_LTU: 576 if (c2) { 577 if (arg2 >= -0x800 && arg2 <= 0x7ff) { 578 if (cond == TCG_COND_LT) { 579 tcg_out_opc_slti(s, ret, arg1, arg2); 580 } else { 581 tcg_out_opc_sltui(s, ret, arg1, arg2); 582 } 583 break; 584 } 585 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 586 arg2 = TCG_REG_TMP0; 587 } 588 if (cond == TCG_COND_LT) { 589 tcg_out_opc_slt(s, ret, arg1, arg2); 590 } else { 591 tcg_out_opc_sltu(s, ret, arg1, arg2); 592 } 593 break; 594 595 default: 596 g_assert_not_reached(); 597 break; 598 } 599 600 return ret | flags; 601} 602 603static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 604 TCGReg arg1, tcg_target_long arg2, bool c2) 605{ 606 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 607 608 if (tmpflags != ret) { 609 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 610 611 switch (tmpflags & SETCOND_FLAGS) { 612 case SETCOND_INV: 613 /* Intermediate result is boolean: simply invert. */ 614 tcg_out_opc_xori(s, ret, tmp, 1); 615 break; 616 case SETCOND_NEZ: 617 /* Intermediate result is zero/non-zero: test != 0. */ 618 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 619 break; 620 case SETCOND_NEZ | SETCOND_INV: 621 /* Intermediate result is zero/non-zero: test == 0. */ 622 tcg_out_opc_sltui(s, ret, tmp, 1); 623 break; 624 default: 625 g_assert_not_reached(); 626 } 627 } 628} 629 630static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 631 TCGReg c1, tcg_target_long c2, bool const2, 632 TCGReg v1, TCGReg v2) 633{ 634 int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const2); 635 TCGReg t; 636 637 /* Standardize the test below to t != 0. */ 638 if (tmpflags & SETCOND_INV) { 639 t = v1, v1 = v2, v2 = t; 640 } 641 642 t = tmpflags & ~SETCOND_FLAGS; 643 if (v1 == TCG_REG_ZERO) { 644 tcg_out_opc_masknez(s, ret, v2, t); 645 } else if (v2 == TCG_REG_ZERO) { 646 tcg_out_opc_maskeqz(s, ret, v1, t); 647 } else { 648 tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */ 649 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */ 650 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2); 651 } 652} 653 654/* 655 * Branch helpers 656 */ 657 658static const struct { 659 LoongArchInsn op; 660 bool swap; 661} tcg_brcond_to_loongarch[] = { 662 [TCG_COND_EQ] = { OPC_BEQ, false }, 663 [TCG_COND_NE] = { OPC_BNE, false }, 664 [TCG_COND_LT] = { OPC_BGT, true }, 665 [TCG_COND_GE] = { OPC_BLE, true }, 666 [TCG_COND_LE] = { OPC_BLE, false }, 667 [TCG_COND_GT] = { OPC_BGT, false }, 668 [TCG_COND_LTU] = { OPC_BGTU, true }, 669 [TCG_COND_GEU] = { OPC_BLEU, true }, 670 [TCG_COND_LEU] = { OPC_BLEU, false }, 671 [TCG_COND_GTU] = { OPC_BGTU, false } 672}; 673 674static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 675 TCGReg arg2, TCGLabel *l) 676{ 677 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; 678 679 tcg_debug_assert(op != 0); 680 681 if (tcg_brcond_to_loongarch[cond].swap) { 682 TCGReg t = arg1; 683 arg1 = arg2; 684 arg2 = t; 685 } 686 687 /* all conditional branch insns belong to DJSk16-format */ 688 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); 689 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); 690} 691 692static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 693{ 694 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 695 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 696 697 tcg_debug_assert((offset & 3) == 0); 698 if (offset == sextreg(offset, 0, 28)) { 699 /* short jump: +/- 256MiB */ 700 if (tail) { 701 tcg_out_opc_b(s, offset >> 2); 702 } else { 703 tcg_out_opc_bl(s, offset >> 2); 704 } 705 } else if (offset == sextreg(offset, 0, 38)) { 706 /* long jump: +/- 256GiB */ 707 tcg_target_long lo = sextreg(offset, 0, 18); 708 tcg_target_long hi = offset - lo; 709 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); 710 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 711 } else { 712 /* far jump: 64-bit */ 713 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18); 714 tcg_target_long hi = (tcg_target_long)arg - lo; 715 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); 716 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 717 } 718} 719 720static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 721 const TCGHelperInfo *info) 722{ 723 tcg_out_call_int(s, arg, false); 724} 725 726/* 727 * Load/store helpers 728 */ 729 730static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, 731 TCGReg addr, intptr_t offset) 732{ 733 intptr_t imm12 = sextreg(offset, 0, 12); 734 735 if (offset != imm12) { 736 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 737 738 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 739 imm12 = sextreg(diff, 0, 12); 740 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); 741 } else { 742 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 743 if (addr != TCG_REG_ZERO) { 744 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); 745 } 746 } 747 addr = TCG_REG_TMP2; 748 } 749 750 switch (opc) { 751 case OPC_LD_B: 752 case OPC_LD_BU: 753 case OPC_LD_H: 754 case OPC_LD_HU: 755 case OPC_LD_W: 756 case OPC_LD_WU: 757 case OPC_LD_D: 758 case OPC_ST_B: 759 case OPC_ST_H: 760 case OPC_ST_W: 761 case OPC_ST_D: 762 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); 763 break; 764 default: 765 g_assert_not_reached(); 766 } 767} 768 769static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 770 TCGReg arg1, intptr_t arg2) 771{ 772 bool is_32bit = type == TCG_TYPE_I32; 773 tcg_out_ldst(s, is_32bit ? OPC_LD_W : OPC_LD_D, arg, arg1, arg2); 774} 775 776static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 777 TCGReg arg1, intptr_t arg2) 778{ 779 bool is_32bit = type == TCG_TYPE_I32; 780 tcg_out_ldst(s, is_32bit ? OPC_ST_W : OPC_ST_D, arg, arg1, arg2); 781} 782 783static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 784 TCGReg base, intptr_t ofs) 785{ 786 if (val == 0) { 787 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 788 return true; 789 } 790 return false; 791} 792 793/* 794 * Load/store helpers for SoftMMU, and qemu_ld/st implementations 795 */ 796 797#if defined(CONFIG_SOFTMMU) 798/* 799 * helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, 800 * MemOpIdx oi, uintptr_t ra) 801 */ 802static void * const qemu_ld_helpers[4] = { 803 [MO_8] = helper_ret_ldub_mmu, 804 [MO_16] = helper_le_lduw_mmu, 805 [MO_32] = helper_le_ldul_mmu, 806 [MO_64] = helper_le_ldq_mmu, 807}; 808 809/* 810 * helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, 811 * uintxx_t val, MemOpIdx oi, 812 * uintptr_t ra) 813 */ 814static void * const qemu_st_helpers[4] = { 815 [MO_8] = helper_ret_stb_mmu, 816 [MO_16] = helper_le_stw_mmu, 817 [MO_32] = helper_le_stl_mmu, 818 [MO_64] = helper_le_stq_mmu, 819}; 820 821/* We expect to use a 12-bit negative offset from ENV. */ 822QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 823QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); 824 825static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 826{ 827 tcg_out_opc_b(s, 0); 828 return reloc_br_sd10k16(s->code_ptr - 1, target); 829} 830 831/* 832 * Emits common code for TLB addend lookup, that eventually loads the 833 * addend in TCG_REG_TMP2. 834 */ 835static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, MemOpIdx oi, 836 tcg_insn_unit **label_ptr, bool is_load) 837{ 838 MemOp opc = get_memop(oi); 839 unsigned s_bits = opc & MO_SIZE; 840 unsigned a_bits = get_alignment_bits(opc); 841 tcg_target_long compare_mask; 842 int mem_index = get_mmuidx(oi); 843 int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); 844 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 845 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 846 847 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 848 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 849 850 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addrl, 851 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 852 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 853 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 854 855 /* Load the tlb comparator and the addend. */ 856 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, 857 is_load ? offsetof(CPUTLBEntry, addr_read) 858 : offsetof(CPUTLBEntry, addr_write)); 859 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 860 offsetof(CPUTLBEntry, addend)); 861 862 /* We don't support unaligned accesses. */ 863 if (a_bits < s_bits) { 864 a_bits = s_bits; 865 } 866 /* Clear the non-page, non-alignment bits from the address. */ 867 compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1); 868 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); 869 tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addrl); 870 871 /* Compare masked address with the TLB entry. */ 872 label_ptr[0] = s->code_ptr; 873 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); 874 875 /* TLB Hit - addend in TCG_REG_TMP2, ready for use. */ 876} 877 878static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, 879 TCGType type, 880 TCGReg datalo, TCGReg addrlo, 881 void *raddr, tcg_insn_unit **label_ptr) 882{ 883 TCGLabelQemuLdst *label = new_ldst_label(s); 884 885 label->is_ld = is_ld; 886 label->oi = oi; 887 label->type = type; 888 label->datalo_reg = datalo; 889 label->datahi_reg = 0; /* unused */ 890 label->addrlo_reg = addrlo; 891 label->addrhi_reg = 0; /* unused */ 892 label->raddr = tcg_splitwx_to_rx(raddr); 893 label->label_ptr[0] = label_ptr[0]; 894} 895 896static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 897{ 898 MemOpIdx oi = l->oi; 899 MemOp opc = get_memop(oi); 900 MemOp size = opc & MO_SIZE; 901 902 /* resolve label address */ 903 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 904 return false; 905 } 906 907 /* call load helper */ 908 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); 909 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); 910 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A2, oi); 911 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (tcg_target_long)l->raddr); 912 913 tcg_out_call_int(s, qemu_ld_helpers[size], false); 914 915 tcg_out_movext(s, l->type, l->datalo_reg, 916 TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_A0); 917 return tcg_out_goto(s, l->raddr); 918} 919 920static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 921{ 922 MemOpIdx oi = l->oi; 923 MemOp opc = get_memop(oi); 924 MemOp size = opc & MO_SIZE; 925 926 /* resolve label address */ 927 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 928 return false; 929 } 930 931 /* call store helper */ 932 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); 933 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); 934 tcg_out_movext(s, size == MO_64 ? TCG_TYPE_I32 : TCG_TYPE_I32, TCG_REG_A2, 935 l->type, size, l->datalo_reg); 936 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi); 937 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr); 938 939 tcg_out_call_int(s, qemu_st_helpers[size], false); 940 941 return tcg_out_goto(s, l->raddr); 942} 943#else 944 945/* 946 * Alignment helpers for user-mode emulation 947 */ 948 949static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg, 950 unsigned a_bits) 951{ 952 TCGLabelQemuLdst *l = new_ldst_label(s); 953 954 l->is_ld = is_ld; 955 l->addrlo_reg = addr_reg; 956 957 /* 958 * Without micro-architecture details, we don't know which of bstrpick or 959 * andi is faster, so use bstrpick as it's not constrained by imm field 960 * width. (Not to say alignments >= 2^12 are going to happen any time 961 * soon, though) 962 */ 963 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); 964 965 l->label_ptr[0] = s->code_ptr; 966 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); 967 968 l->raddr = tcg_splitwx_to_rx(s->code_ptr); 969} 970 971static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 972{ 973 /* resolve label address */ 974 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 975 return false; 976 } 977 978 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); 979 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); 980 981 /* tail call, with the return address back inline. */ 982 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr); 983 tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld 984 : helper_unaligned_st), true); 985 return true; 986} 987 988static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 989{ 990 return tcg_out_fail_alignment(s, l); 991} 992 993static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 994{ 995 return tcg_out_fail_alignment(s, l); 996} 997 998#endif /* CONFIG_SOFTMMU */ 999 1000/* 1001 * `ext32u` the address register into the temp register given, 1002 * if target is 32-bit, no-op otherwise. 1003 * 1004 * Returns the address register ready for use with TLB addend. 1005 */ 1006static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s, 1007 TCGReg addr, TCGReg tmp) 1008{ 1009 if (TARGET_LONG_BITS == 32) { 1010 tcg_out_ext32u(s, tmp, addr); 1011 return tmp; 1012 } 1013 return addr; 1014} 1015 1016static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj, 1017 TCGReg rk, MemOp opc, TCGType type) 1018{ 1019 /* Byte swapping is left to middle-end expansion. */ 1020 tcg_debug_assert((opc & MO_BSWAP) == 0); 1021 1022 switch (opc & MO_SSIZE) { 1023 case MO_UB: 1024 tcg_out_opc_ldx_bu(s, rd, rj, rk); 1025 break; 1026 case MO_SB: 1027 tcg_out_opc_ldx_b(s, rd, rj, rk); 1028 break; 1029 case MO_UW: 1030 tcg_out_opc_ldx_hu(s, rd, rj, rk); 1031 break; 1032 case MO_SW: 1033 tcg_out_opc_ldx_h(s, rd, rj, rk); 1034 break; 1035 case MO_UL: 1036 if (type == TCG_TYPE_I64) { 1037 tcg_out_opc_ldx_wu(s, rd, rj, rk); 1038 break; 1039 } 1040 /* fallthrough */ 1041 case MO_SL: 1042 tcg_out_opc_ldx_w(s, rd, rj, rk); 1043 break; 1044 case MO_UQ: 1045 tcg_out_opc_ldx_d(s, rd, rj, rk); 1046 break; 1047 default: 1048 g_assert_not_reached(); 1049 } 1050} 1051 1052static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type) 1053{ 1054 TCGReg addr_regl; 1055 TCGReg data_regl; 1056 MemOpIdx oi; 1057 MemOp opc; 1058#if defined(CONFIG_SOFTMMU) 1059 tcg_insn_unit *label_ptr[1]; 1060#else 1061 unsigned a_bits; 1062#endif 1063 TCGReg base; 1064 1065 data_regl = *args++; 1066 addr_regl = *args++; 1067 oi = *args++; 1068 opc = get_memop(oi); 1069 1070#if defined(CONFIG_SOFTMMU) 1071 tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1); 1072 base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); 1073 tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type); 1074 add_qemu_ldst_label(s, 1, oi, type, 1075 data_regl, addr_regl, 1076 s->code_ptr, label_ptr); 1077#else 1078 a_bits = get_alignment_bits(opc); 1079 if (a_bits) { 1080 tcg_out_test_alignment(s, true, addr_regl, a_bits); 1081 } 1082 base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); 1083 TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 1084 tcg_out_qemu_ld_indexed(s, data_regl, base, guest_base_reg, opc, type); 1085#endif 1086} 1087 1088static void tcg_out_qemu_st_indexed(TCGContext *s, TCGReg data, 1089 TCGReg rj, TCGReg rk, MemOp opc) 1090{ 1091 /* Byte swapping is left to middle-end expansion. */ 1092 tcg_debug_assert((opc & MO_BSWAP) == 0); 1093 1094 switch (opc & MO_SIZE) { 1095 case MO_8: 1096 tcg_out_opc_stx_b(s, data, rj, rk); 1097 break; 1098 case MO_16: 1099 tcg_out_opc_stx_h(s, data, rj, rk); 1100 break; 1101 case MO_32: 1102 tcg_out_opc_stx_w(s, data, rj, rk); 1103 break; 1104 case MO_64: 1105 tcg_out_opc_stx_d(s, data, rj, rk); 1106 break; 1107 default: 1108 g_assert_not_reached(); 1109 } 1110} 1111 1112static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType type) 1113{ 1114 TCGReg addr_regl; 1115 TCGReg data_regl; 1116 MemOpIdx oi; 1117 MemOp opc; 1118#if defined(CONFIG_SOFTMMU) 1119 tcg_insn_unit *label_ptr[1]; 1120#else 1121 unsigned a_bits; 1122#endif 1123 TCGReg base; 1124 1125 data_regl = *args++; 1126 addr_regl = *args++; 1127 oi = *args++; 1128 opc = get_memop(oi); 1129 1130#if defined(CONFIG_SOFTMMU) 1131 tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0); 1132 base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); 1133 tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc); 1134 add_qemu_ldst_label(s, 0, oi, type, 1135 data_regl, addr_regl, 1136 s->code_ptr, label_ptr); 1137#else 1138 a_bits = get_alignment_bits(opc); 1139 if (a_bits) { 1140 tcg_out_test_alignment(s, false, addr_regl, a_bits); 1141 } 1142 base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); 1143 TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 1144 tcg_out_qemu_st_indexed(s, data_regl, base, guest_base_reg, opc); 1145#endif 1146} 1147 1148/* 1149 * Entry-points 1150 */ 1151 1152static const tcg_insn_unit *tb_ret_addr; 1153 1154static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1155{ 1156 /* Reuse the zeroing that exists for goto_ptr. */ 1157 if (a0 == 0) { 1158 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1159 } else { 1160 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1161 tcg_out_call_int(s, tb_ret_addr, true); 1162 } 1163} 1164 1165static void tcg_out_goto_tb(TCGContext *s, int which) 1166{ 1167 /* 1168 * Direct branch, or load indirect address, to be patched 1169 * by tb_target_set_jmp_target. Check indirect load offset 1170 * in range early, regardless of direct branch distance, 1171 * via assert within tcg_out_opc_pcaddu2i. 1172 */ 1173 uintptr_t i_addr = get_jmp_target_addr(s, which); 1174 intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr); 1175 1176 set_jmp_insn_offset(s, which); 1177 tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2); 1178 1179 /* Finish the load and indirect branch. */ 1180 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0); 1181 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1182 set_jmp_reset_offset(s, which); 1183} 1184 1185void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1186 uintptr_t jmp_rx, uintptr_t jmp_rw) 1187{ 1188 uintptr_t d_addr = tb->jmp_target_addr[n]; 1189 ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2; 1190 tcg_insn_unit insn; 1191 1192 /* Either directly branch, or load slot address for indirect branch. */ 1193 if (d_disp == sextreg(d_disp, 0, 26)) { 1194 insn = encode_sd10k16_insn(OPC_B, d_disp); 1195 } else { 1196 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n]; 1197 intptr_t i_disp = i_addr - jmp_rx; 1198 insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2); 1199 } 1200 1201 qatomic_set((tcg_insn_unit *)jmp_rw, insn); 1202 flush_idcache_range(jmp_rx, jmp_rw, 4); 1203} 1204 1205static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1206 const TCGArg args[TCG_MAX_OP_ARGS], 1207 const int const_args[TCG_MAX_OP_ARGS]) 1208{ 1209 TCGArg a0 = args[0]; 1210 TCGArg a1 = args[1]; 1211 TCGArg a2 = args[2]; 1212 int c2 = const_args[2]; 1213 1214 switch (opc) { 1215 case INDEX_op_mb: 1216 tcg_out_mb(s, a0); 1217 break; 1218 1219 case INDEX_op_goto_ptr: 1220 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); 1221 break; 1222 1223 case INDEX_op_br: 1224 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0), 1225 0); 1226 tcg_out_opc_b(s, 0); 1227 break; 1228 1229 case INDEX_op_brcond_i32: 1230 case INDEX_op_brcond_i64: 1231 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1232 break; 1233 1234 case INDEX_op_extrh_i64_i32: 1235 tcg_out_opc_srai_d(s, a0, a1, 32); 1236 break; 1237 1238 case INDEX_op_not_i32: 1239 case INDEX_op_not_i64: 1240 tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO); 1241 break; 1242 1243 case INDEX_op_nor_i32: 1244 case INDEX_op_nor_i64: 1245 if (c2) { 1246 tcg_out_opc_ori(s, a0, a1, a2); 1247 tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO); 1248 } else { 1249 tcg_out_opc_nor(s, a0, a1, a2); 1250 } 1251 break; 1252 1253 case INDEX_op_andc_i32: 1254 case INDEX_op_andc_i64: 1255 if (c2) { 1256 /* guaranteed to fit due to constraint */ 1257 tcg_out_opc_andi(s, a0, a1, ~a2); 1258 } else { 1259 tcg_out_opc_andn(s, a0, a1, a2); 1260 } 1261 break; 1262 1263 case INDEX_op_orc_i32: 1264 case INDEX_op_orc_i64: 1265 if (c2) { 1266 /* guaranteed to fit due to constraint */ 1267 tcg_out_opc_ori(s, a0, a1, ~a2); 1268 } else { 1269 tcg_out_opc_orn(s, a0, a1, a2); 1270 } 1271 break; 1272 1273 case INDEX_op_and_i32: 1274 case INDEX_op_and_i64: 1275 if (c2) { 1276 tcg_out_opc_andi(s, a0, a1, a2); 1277 } else { 1278 tcg_out_opc_and(s, a0, a1, a2); 1279 } 1280 break; 1281 1282 case INDEX_op_or_i32: 1283 case INDEX_op_or_i64: 1284 if (c2) { 1285 tcg_out_opc_ori(s, a0, a1, a2); 1286 } else { 1287 tcg_out_opc_or(s, a0, a1, a2); 1288 } 1289 break; 1290 1291 case INDEX_op_xor_i32: 1292 case INDEX_op_xor_i64: 1293 if (c2) { 1294 tcg_out_opc_xori(s, a0, a1, a2); 1295 } else { 1296 tcg_out_opc_xor(s, a0, a1, a2); 1297 } 1298 break; 1299 1300 case INDEX_op_extract_i32: 1301 tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); 1302 break; 1303 case INDEX_op_extract_i64: 1304 tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); 1305 break; 1306 1307 case INDEX_op_deposit_i32: 1308 tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); 1309 break; 1310 case INDEX_op_deposit_i64: 1311 tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); 1312 break; 1313 1314 case INDEX_op_bswap16_i32: 1315 case INDEX_op_bswap16_i64: 1316 tcg_out_opc_revb_2h(s, a0, a1); 1317 if (a2 & TCG_BSWAP_OS) { 1318 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0); 1319 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1320 tcg_out_ext16u(s, a0, a0); 1321 } 1322 break; 1323 1324 case INDEX_op_bswap32_i32: 1325 /* All 32-bit values are computed sign-extended in the register. */ 1326 a2 = TCG_BSWAP_OS; 1327 /* fallthrough */ 1328 case INDEX_op_bswap32_i64: 1329 tcg_out_opc_revb_2w(s, a0, a1); 1330 if (a2 & TCG_BSWAP_OS) { 1331 tcg_out_ext32s(s, a0, a0); 1332 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1333 tcg_out_ext32u(s, a0, a0); 1334 } 1335 break; 1336 1337 case INDEX_op_bswap64_i64: 1338 tcg_out_opc_revb_d(s, a0, a1); 1339 break; 1340 1341 case INDEX_op_clz_i32: 1342 tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true); 1343 break; 1344 case INDEX_op_clz_i64: 1345 tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false); 1346 break; 1347 1348 case INDEX_op_ctz_i32: 1349 tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true); 1350 break; 1351 case INDEX_op_ctz_i64: 1352 tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false); 1353 break; 1354 1355 case INDEX_op_shl_i32: 1356 if (c2) { 1357 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); 1358 } else { 1359 tcg_out_opc_sll_w(s, a0, a1, a2); 1360 } 1361 break; 1362 case INDEX_op_shl_i64: 1363 if (c2) { 1364 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); 1365 } else { 1366 tcg_out_opc_sll_d(s, a0, a1, a2); 1367 } 1368 break; 1369 1370 case INDEX_op_shr_i32: 1371 if (c2) { 1372 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); 1373 } else { 1374 tcg_out_opc_srl_w(s, a0, a1, a2); 1375 } 1376 break; 1377 case INDEX_op_shr_i64: 1378 if (c2) { 1379 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); 1380 } else { 1381 tcg_out_opc_srl_d(s, a0, a1, a2); 1382 } 1383 break; 1384 1385 case INDEX_op_sar_i32: 1386 if (c2) { 1387 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); 1388 } else { 1389 tcg_out_opc_sra_w(s, a0, a1, a2); 1390 } 1391 break; 1392 case INDEX_op_sar_i64: 1393 if (c2) { 1394 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); 1395 } else { 1396 tcg_out_opc_sra_d(s, a0, a1, a2); 1397 } 1398 break; 1399 1400 case INDEX_op_rotl_i32: 1401 /* transform into equivalent rotr/rotri */ 1402 if (c2) { 1403 tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f); 1404 } else { 1405 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1406 tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0); 1407 } 1408 break; 1409 case INDEX_op_rotl_i64: 1410 /* transform into equivalent rotr/rotri */ 1411 if (c2) { 1412 tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f); 1413 } else { 1414 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1415 tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0); 1416 } 1417 break; 1418 1419 case INDEX_op_rotr_i32: 1420 if (c2) { 1421 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); 1422 } else { 1423 tcg_out_opc_rotr_w(s, a0, a1, a2); 1424 } 1425 break; 1426 case INDEX_op_rotr_i64: 1427 if (c2) { 1428 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); 1429 } else { 1430 tcg_out_opc_rotr_d(s, a0, a1, a2); 1431 } 1432 break; 1433 1434 case INDEX_op_add_i32: 1435 if (c2) { 1436 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2); 1437 } else { 1438 tcg_out_opc_add_w(s, a0, a1, a2); 1439 } 1440 break; 1441 case INDEX_op_add_i64: 1442 if (c2) { 1443 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2); 1444 } else { 1445 tcg_out_opc_add_d(s, a0, a1, a2); 1446 } 1447 break; 1448 1449 case INDEX_op_sub_i32: 1450 if (c2) { 1451 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2); 1452 } else { 1453 tcg_out_opc_sub_w(s, a0, a1, a2); 1454 } 1455 break; 1456 case INDEX_op_sub_i64: 1457 if (c2) { 1458 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2); 1459 } else { 1460 tcg_out_opc_sub_d(s, a0, a1, a2); 1461 } 1462 break; 1463 1464 case INDEX_op_mul_i32: 1465 tcg_out_opc_mul_w(s, a0, a1, a2); 1466 break; 1467 case INDEX_op_mul_i64: 1468 tcg_out_opc_mul_d(s, a0, a1, a2); 1469 break; 1470 1471 case INDEX_op_mulsh_i32: 1472 tcg_out_opc_mulh_w(s, a0, a1, a2); 1473 break; 1474 case INDEX_op_mulsh_i64: 1475 tcg_out_opc_mulh_d(s, a0, a1, a2); 1476 break; 1477 1478 case INDEX_op_muluh_i32: 1479 tcg_out_opc_mulh_wu(s, a0, a1, a2); 1480 break; 1481 case INDEX_op_muluh_i64: 1482 tcg_out_opc_mulh_du(s, a0, a1, a2); 1483 break; 1484 1485 case INDEX_op_div_i32: 1486 tcg_out_opc_div_w(s, a0, a1, a2); 1487 break; 1488 case INDEX_op_div_i64: 1489 tcg_out_opc_div_d(s, a0, a1, a2); 1490 break; 1491 1492 case INDEX_op_divu_i32: 1493 tcg_out_opc_div_wu(s, a0, a1, a2); 1494 break; 1495 case INDEX_op_divu_i64: 1496 tcg_out_opc_div_du(s, a0, a1, a2); 1497 break; 1498 1499 case INDEX_op_rem_i32: 1500 tcg_out_opc_mod_w(s, a0, a1, a2); 1501 break; 1502 case INDEX_op_rem_i64: 1503 tcg_out_opc_mod_d(s, a0, a1, a2); 1504 break; 1505 1506 case INDEX_op_remu_i32: 1507 tcg_out_opc_mod_wu(s, a0, a1, a2); 1508 break; 1509 case INDEX_op_remu_i64: 1510 tcg_out_opc_mod_du(s, a0, a1, a2); 1511 break; 1512 1513 case INDEX_op_setcond_i32: 1514 case INDEX_op_setcond_i64: 1515 tcg_out_setcond(s, args[3], a0, a1, a2, c2); 1516 break; 1517 1518 case INDEX_op_movcond_i32: 1519 case INDEX_op_movcond_i64: 1520 tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]); 1521 break; 1522 1523 case INDEX_op_ld8s_i32: 1524 case INDEX_op_ld8s_i64: 1525 tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); 1526 break; 1527 case INDEX_op_ld8u_i32: 1528 case INDEX_op_ld8u_i64: 1529 tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2); 1530 break; 1531 case INDEX_op_ld16s_i32: 1532 case INDEX_op_ld16s_i64: 1533 tcg_out_ldst(s, OPC_LD_H, a0, a1, a2); 1534 break; 1535 case INDEX_op_ld16u_i32: 1536 case INDEX_op_ld16u_i64: 1537 tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2); 1538 break; 1539 case INDEX_op_ld_i32: 1540 case INDEX_op_ld32s_i64: 1541 tcg_out_ldst(s, OPC_LD_W, a0, a1, a2); 1542 break; 1543 case INDEX_op_ld32u_i64: 1544 tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2); 1545 break; 1546 case INDEX_op_ld_i64: 1547 tcg_out_ldst(s, OPC_LD_D, a0, a1, a2); 1548 break; 1549 1550 case INDEX_op_st8_i32: 1551 case INDEX_op_st8_i64: 1552 tcg_out_ldst(s, OPC_ST_B, a0, a1, a2); 1553 break; 1554 case INDEX_op_st16_i32: 1555 case INDEX_op_st16_i64: 1556 tcg_out_ldst(s, OPC_ST_H, a0, a1, a2); 1557 break; 1558 case INDEX_op_st_i32: 1559 case INDEX_op_st32_i64: 1560 tcg_out_ldst(s, OPC_ST_W, a0, a1, a2); 1561 break; 1562 case INDEX_op_st_i64: 1563 tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); 1564 break; 1565 1566 case INDEX_op_qemu_ld_i32: 1567 tcg_out_qemu_ld(s, args, TCG_TYPE_I32); 1568 break; 1569 case INDEX_op_qemu_ld_i64: 1570 tcg_out_qemu_ld(s, args, TCG_TYPE_I64); 1571 break; 1572 case INDEX_op_qemu_st_i32: 1573 tcg_out_qemu_st(s, args, TCG_TYPE_I32); 1574 break; 1575 case INDEX_op_qemu_st_i64: 1576 tcg_out_qemu_st(s, args, TCG_TYPE_I64); 1577 break; 1578 1579 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1580 case INDEX_op_mov_i64: 1581 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1582 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1583 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1584 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 1585 case INDEX_op_ext8s_i64: 1586 case INDEX_op_ext8u_i32: 1587 case INDEX_op_ext8u_i64: 1588 case INDEX_op_ext16s_i32: 1589 case INDEX_op_ext16s_i64: 1590 case INDEX_op_ext16u_i32: 1591 case INDEX_op_ext16u_i64: 1592 case INDEX_op_ext32s_i64: 1593 case INDEX_op_ext32u_i64: 1594 case INDEX_op_ext_i32_i64: 1595 case INDEX_op_extu_i32_i64: 1596 case INDEX_op_extrl_i64_i32: 1597 default: 1598 g_assert_not_reached(); 1599 } 1600} 1601 1602static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 1603{ 1604 switch (op) { 1605 case INDEX_op_goto_ptr: 1606 return C_O0_I1(r); 1607 1608 case INDEX_op_st8_i32: 1609 case INDEX_op_st8_i64: 1610 case INDEX_op_st16_i32: 1611 case INDEX_op_st16_i64: 1612 case INDEX_op_st32_i64: 1613 case INDEX_op_st_i32: 1614 case INDEX_op_st_i64: 1615 return C_O0_I2(rZ, r); 1616 1617 case INDEX_op_brcond_i32: 1618 case INDEX_op_brcond_i64: 1619 return C_O0_I2(rZ, rZ); 1620 1621 case INDEX_op_qemu_st_i32: 1622 case INDEX_op_qemu_st_i64: 1623 return C_O0_I2(LZ, L); 1624 1625 case INDEX_op_ext8s_i32: 1626 case INDEX_op_ext8s_i64: 1627 case INDEX_op_ext8u_i32: 1628 case INDEX_op_ext8u_i64: 1629 case INDEX_op_ext16s_i32: 1630 case INDEX_op_ext16s_i64: 1631 case INDEX_op_ext16u_i32: 1632 case INDEX_op_ext16u_i64: 1633 case INDEX_op_ext32s_i64: 1634 case INDEX_op_ext32u_i64: 1635 case INDEX_op_extu_i32_i64: 1636 case INDEX_op_extrl_i64_i32: 1637 case INDEX_op_extrh_i64_i32: 1638 case INDEX_op_ext_i32_i64: 1639 case INDEX_op_not_i32: 1640 case INDEX_op_not_i64: 1641 case INDEX_op_extract_i32: 1642 case INDEX_op_extract_i64: 1643 case INDEX_op_bswap16_i32: 1644 case INDEX_op_bswap16_i64: 1645 case INDEX_op_bswap32_i32: 1646 case INDEX_op_bswap32_i64: 1647 case INDEX_op_bswap64_i64: 1648 case INDEX_op_ld8s_i32: 1649 case INDEX_op_ld8s_i64: 1650 case INDEX_op_ld8u_i32: 1651 case INDEX_op_ld8u_i64: 1652 case INDEX_op_ld16s_i32: 1653 case INDEX_op_ld16s_i64: 1654 case INDEX_op_ld16u_i32: 1655 case INDEX_op_ld16u_i64: 1656 case INDEX_op_ld32s_i64: 1657 case INDEX_op_ld32u_i64: 1658 case INDEX_op_ld_i32: 1659 case INDEX_op_ld_i64: 1660 return C_O1_I1(r, r); 1661 1662 case INDEX_op_qemu_ld_i32: 1663 case INDEX_op_qemu_ld_i64: 1664 return C_O1_I1(r, L); 1665 1666 case INDEX_op_andc_i32: 1667 case INDEX_op_andc_i64: 1668 case INDEX_op_orc_i32: 1669 case INDEX_op_orc_i64: 1670 /* 1671 * LoongArch insns for these ops don't have reg-imm forms, but we 1672 * can express using andi/ori if ~constant satisfies 1673 * TCG_CT_CONST_U12. 1674 */ 1675 return C_O1_I2(r, r, rC); 1676 1677 case INDEX_op_shl_i32: 1678 case INDEX_op_shl_i64: 1679 case INDEX_op_shr_i32: 1680 case INDEX_op_shr_i64: 1681 case INDEX_op_sar_i32: 1682 case INDEX_op_sar_i64: 1683 case INDEX_op_rotl_i32: 1684 case INDEX_op_rotl_i64: 1685 case INDEX_op_rotr_i32: 1686 case INDEX_op_rotr_i64: 1687 return C_O1_I2(r, r, ri); 1688 1689 case INDEX_op_add_i32: 1690 return C_O1_I2(r, r, ri); 1691 case INDEX_op_add_i64: 1692 return C_O1_I2(r, r, rJ); 1693 1694 case INDEX_op_and_i32: 1695 case INDEX_op_and_i64: 1696 case INDEX_op_nor_i32: 1697 case INDEX_op_nor_i64: 1698 case INDEX_op_or_i32: 1699 case INDEX_op_or_i64: 1700 case INDEX_op_xor_i32: 1701 case INDEX_op_xor_i64: 1702 /* LoongArch reg-imm bitops have their imms ZERO-extended */ 1703 return C_O1_I2(r, r, rU); 1704 1705 case INDEX_op_clz_i32: 1706 case INDEX_op_clz_i64: 1707 case INDEX_op_ctz_i32: 1708 case INDEX_op_ctz_i64: 1709 return C_O1_I2(r, r, rW); 1710 1711 case INDEX_op_deposit_i32: 1712 case INDEX_op_deposit_i64: 1713 /* Must deposit into the same register as input */ 1714 return C_O1_I2(r, 0, rZ); 1715 1716 case INDEX_op_sub_i32: 1717 case INDEX_op_setcond_i32: 1718 return C_O1_I2(r, rZ, ri); 1719 case INDEX_op_sub_i64: 1720 case INDEX_op_setcond_i64: 1721 return C_O1_I2(r, rZ, rJ); 1722 1723 case INDEX_op_mul_i32: 1724 case INDEX_op_mul_i64: 1725 case INDEX_op_mulsh_i32: 1726 case INDEX_op_mulsh_i64: 1727 case INDEX_op_muluh_i32: 1728 case INDEX_op_muluh_i64: 1729 case INDEX_op_div_i32: 1730 case INDEX_op_div_i64: 1731 case INDEX_op_divu_i32: 1732 case INDEX_op_divu_i64: 1733 case INDEX_op_rem_i32: 1734 case INDEX_op_rem_i64: 1735 case INDEX_op_remu_i32: 1736 case INDEX_op_remu_i64: 1737 return C_O1_I2(r, rZ, rZ); 1738 1739 case INDEX_op_movcond_i32: 1740 case INDEX_op_movcond_i64: 1741 return C_O1_I4(r, rZ, rJ, rZ, rZ); 1742 1743 default: 1744 g_assert_not_reached(); 1745 } 1746} 1747 1748static const int tcg_target_callee_save_regs[] = { 1749 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 1750 TCG_REG_S1, 1751 TCG_REG_S2, 1752 TCG_REG_S3, 1753 TCG_REG_S4, 1754 TCG_REG_S5, 1755 TCG_REG_S6, 1756 TCG_REG_S7, 1757 TCG_REG_S8, 1758 TCG_REG_S9, 1759 TCG_REG_RA, /* should be last for ABI compliance */ 1760}; 1761 1762/* Stack frame parameters. */ 1763#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 1764#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 1765#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 1766#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 1767 + TCG_TARGET_STACK_ALIGN - 1) \ 1768 & -TCG_TARGET_STACK_ALIGN) 1769#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 1770 1771/* We're expecting to be able to use an immediate for frame allocation. */ 1772QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 1773 1774/* Generate global QEMU prologue and epilogue code */ 1775static void tcg_target_qemu_prologue(TCGContext *s) 1776{ 1777 int i; 1778 1779 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 1780 1781 /* TB prologue */ 1782 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 1783 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 1784 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 1785 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 1786 } 1787 1788#if !defined(CONFIG_SOFTMMU) 1789 if (USE_GUEST_BASE) { 1790 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 1791 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 1792 } 1793#endif 1794 1795 /* Call generated code */ 1796 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 1797 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 1798 1799 /* Return path for goto_ptr. Set return value to 0 */ 1800 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 1801 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 1802 1803 /* TB epilogue */ 1804 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 1805 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 1806 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 1807 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 1808 } 1809 1810 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 1811 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); 1812} 1813 1814static void tcg_target_init(TCGContext *s) 1815{ 1816 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 1817 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 1818 1819 tcg_target_call_clobber_regs = ALL_GENERAL_REGS; 1820 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 1821 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 1822 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 1823 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 1824 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 1825 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 1826 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 1827 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 1828 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 1829 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 1830 1831 s->reserved_regs = 0; 1832 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 1833 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 1834 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 1835 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 1836 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 1837 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 1838 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); 1839} 1840 1841typedef struct { 1842 DebugFrameHeader h; 1843 uint8_t fde_def_cfa[4]; 1844 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 1845} DebugFrame; 1846 1847#define ELF_HOST_MACHINE EM_LOONGARCH 1848 1849static const DebugFrame debug_frame = { 1850 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 1851 .h.cie.id = -1, 1852 .h.cie.version = 1, 1853 .h.cie.code_align = 1, 1854 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 1855 .h.cie.return_column = TCG_REG_RA, 1856 1857 /* Total FDE size does not include the "len" member. */ 1858 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 1859 1860 .fde_def_cfa = { 1861 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 1862 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 1863 (FRAME_SIZE >> 7) 1864 }, 1865 .fde_reg_ofs = { 1866 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ 1867 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ 1868 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ 1869 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ 1870 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ 1871 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ 1872 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ 1873 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ 1874 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ 1875 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ 1876 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 1877 } 1878}; 1879 1880void tcg_register_jit(const void *buf, size_t buf_size) 1881{ 1882 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 1883} 1884