1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.c.inc 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 11 * Copyright (c) 2008 Fabrice Bellard 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a copy 14 * of this software and associated documentation files (the "Software"), to deal 15 * in the Software without restriction, including without limitation the rights 16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 * copies of the Software, and to permit persons to whom the Software is 18 * furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 * THE SOFTWARE. 30 */ 31 32#include "../tcg-ldst.c.inc" 33 34#ifdef CONFIG_DEBUG_TCG 35static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 36 "zero", 37 "ra", 38 "tp", 39 "sp", 40 "a0", 41 "a1", 42 "a2", 43 "a3", 44 "a4", 45 "a5", 46 "a6", 47 "a7", 48 "t0", 49 "t1", 50 "t2", 51 "t3", 52 "t4", 53 "t5", 54 "t6", 55 "t7", 56 "t8", 57 "r21", /* reserved in the LP64* ABI, hence no ABI name */ 58 "s9", 59 "s0", 60 "s1", 61 "s2", 62 "s3", 63 "s4", 64 "s5", 65 "s6", 66 "s7", 67 "s8" 68}; 69#endif 70 71static const int tcg_target_reg_alloc_order[] = { 72 /* Registers preserved across calls */ 73 /* TCG_REG_S0 reserved for TCG_AREG0 */ 74 TCG_REG_S1, 75 TCG_REG_S2, 76 TCG_REG_S3, 77 TCG_REG_S4, 78 TCG_REG_S5, 79 TCG_REG_S6, 80 TCG_REG_S7, 81 TCG_REG_S8, 82 TCG_REG_S9, 83 84 /* Registers (potentially) clobbered across calls */ 85 TCG_REG_T0, 86 TCG_REG_T1, 87 TCG_REG_T2, 88 TCG_REG_T3, 89 TCG_REG_T4, 90 TCG_REG_T5, 91 TCG_REG_T6, 92 TCG_REG_T7, 93 TCG_REG_T8, 94 95 /* Argument registers, opposite order of allocation. */ 96 TCG_REG_A7, 97 TCG_REG_A6, 98 TCG_REG_A5, 99 TCG_REG_A4, 100 TCG_REG_A3, 101 TCG_REG_A2, 102 TCG_REG_A1, 103 TCG_REG_A0, 104}; 105 106static const int tcg_target_call_iarg_regs[] = { 107 TCG_REG_A0, 108 TCG_REG_A1, 109 TCG_REG_A2, 110 TCG_REG_A3, 111 TCG_REG_A4, 112 TCG_REG_A5, 113 TCG_REG_A6, 114 TCG_REG_A7, 115}; 116 117static const int tcg_target_call_oarg_regs[] = { 118 TCG_REG_A0, 119 TCG_REG_A1, 120}; 121 122#ifndef CONFIG_SOFTMMU 123#define USE_GUEST_BASE (guest_base != 0) 124#define TCG_GUEST_BASE_REG TCG_REG_S1 125#endif 126 127#define TCG_CT_CONST_ZERO 0x100 128#define TCG_CT_CONST_S12 0x200 129#define TCG_CT_CONST_N12 0x400 130#define TCG_CT_CONST_U12 0x800 131#define TCG_CT_CONST_C12 0x1000 132#define TCG_CT_CONST_WSZ 0x2000 133 134#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 135/* 136 * For softmmu, we need to avoid conflicts with the first 5 137 * argument registers to call the helper. Some of these are 138 * also used for the tlb lookup. 139 */ 140#ifdef CONFIG_SOFTMMU 141#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) 142#else 143#define SOFTMMU_RESERVE_REGS 0 144#endif 145 146 147static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 148{ 149 return sextract64(val, pos, len); 150} 151 152/* test if a constant matches the constraint */ 153static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 154{ 155 if (ct & TCG_CT_CONST) { 156 return true; 157 } 158 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 159 return true; 160 } 161 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { 162 return true; 163 } 164 if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) { 165 return true; 166 } 167 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { 168 return true; 169 } 170 if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) { 171 return true; 172 } 173 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 174 return true; 175 } 176 return false; 177} 178 179/* 180 * Relocations 181 */ 182 183/* 184 * Relocation records defined in LoongArch ELF psABI v1.00 is way too 185 * complicated; a whopping stack machine is needed to stuff the fields, at 186 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are 187 * needed. 188 * 189 * Hence, define our own simpler relocation types. Numbers are chosen as to 190 * not collide with potential future additions to the true ELF relocation 191 * type enum. 192 */ 193 194/* Field Sk16, shifted right by 2; suitable for conditional jumps */ 195#define R_LOONGARCH_BR_SK16 256 196/* Field Sd10k16, shifted right by 2; suitable for B and BL */ 197#define R_LOONGARCH_BR_SD10K16 257 198 199static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 200{ 201 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 202 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 203 204 tcg_debug_assert((offset & 3) == 0); 205 offset >>= 2; 206 if (offset == sextreg(offset, 0, 16)) { 207 *src_rw = deposit64(*src_rw, 10, 16, offset); 208 return true; 209 } 210 211 return false; 212} 213 214static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, 215 const tcg_insn_unit *target) 216{ 217 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 218 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 219 220 tcg_debug_assert((offset & 3) == 0); 221 offset >>= 2; 222 if (offset == sextreg(offset, 0, 26)) { 223 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ 224 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ 225 return true; 226 } 227 228 return false; 229} 230 231static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 232 intptr_t value, intptr_t addend) 233{ 234 tcg_debug_assert(addend == 0); 235 switch (type) { 236 case R_LOONGARCH_BR_SK16: 237 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); 238 case R_LOONGARCH_BR_SD10K16: 239 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); 240 default: 241 g_assert_not_reached(); 242 } 243} 244 245#include "tcg-insn-defs.c.inc" 246 247/* 248 * TCG intrinsics 249 */ 250 251static void tcg_out_mb(TCGContext *s, TCGArg a0) 252{ 253 /* Baseline LoongArch only has the full barrier, unfortunately. */ 254 tcg_out_opc_dbar(s, 0); 255} 256 257static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 258{ 259 if (ret == arg) { 260 return true; 261 } 262 switch (type) { 263 case TCG_TYPE_I32: 264 case TCG_TYPE_I64: 265 /* 266 * Conventional register-register move used in LoongArch is 267 * `or dst, src, zero`. 268 */ 269 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); 270 break; 271 default: 272 g_assert_not_reached(); 273 } 274 return true; 275} 276 277static bool imm_part_needs_loading(bool high_bits_are_ones, 278 tcg_target_long part) 279{ 280 if (high_bits_are_ones) { 281 return part != -1; 282 } else { 283 return part != 0; 284 } 285} 286 287/* Loads a 32-bit immediate into rd, sign-extended. */ 288static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) 289{ 290 tcg_target_long lo = sextreg(val, 0, 12); 291 tcg_target_long hi12 = sextreg(val, 12, 20); 292 293 /* Single-instruction cases. */ 294 if (lo == val) { 295 /* val fits in simm12: addi.w rd, zero, val */ 296 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); 297 return; 298 } 299 if (0x800 <= val && val <= 0xfff) { 300 /* val fits in uimm12: ori rd, zero, val */ 301 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); 302 return; 303 } 304 305 /* High bits must be set; load with lu12i.w + optional ori. */ 306 tcg_out_opc_lu12i_w(s, rd, hi12); 307 if (lo != 0) { 308 tcg_out_opc_ori(s, rd, rd, lo & 0xfff); 309 } 310} 311 312static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 313 tcg_target_long val) 314{ 315 /* 316 * LoongArch conventionally loads 64-bit immediates in at most 4 steps, 317 * with dedicated instructions for filling the respective bitfields 318 * below: 319 * 320 * 6 5 4 3 321 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 322 * +-----------------------+---------------------------------------+... 323 * | hi52 | hi32 | 324 * +-----------------------+---------------------------------------+... 325 * 3 2 1 326 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 327 * ...+-------------------------------------+-------------------------+ 328 * | hi12 | lo | 329 * ...+-------------------------------------+-------------------------+ 330 * 331 * Check if val belong to one of the several fast cases, before falling 332 * back to the slow path. 333 */ 334 335 intptr_t pc_offset; 336 tcg_target_long val_lo, val_hi, pc_hi, offset_hi; 337 tcg_target_long hi32, hi52; 338 bool rd_high_bits_are_ones; 339 340 /* Value fits in signed i32. */ 341 if (type == TCG_TYPE_I32 || val == (int32_t)val) { 342 tcg_out_movi_i32(s, rd, val); 343 return; 344 } 345 346 /* PC-relative cases. */ 347 pc_offset = tcg_pcrel_diff(s, (void *)val); 348 if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) { 349 /* Single pcaddu2i. */ 350 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); 351 return; 352 } 353 354 if (pc_offset == (int32_t)pc_offset) { 355 /* Offset within 32 bits; load with pcalau12i + ori. */ 356 val_lo = sextreg(val, 0, 12); 357 val_hi = val >> 12; 358 pc_hi = (val - pc_offset) >> 12; 359 offset_hi = val_hi - pc_hi; 360 361 tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20)); 362 tcg_out_opc_pcalau12i(s, rd, offset_hi); 363 if (val_lo != 0) { 364 tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff); 365 } 366 return; 367 } 368 369 hi32 = sextreg(val, 32, 20); 370 hi52 = sextreg(val, 52, 12); 371 372 /* Single cu52i.d case. */ 373 if (ctz64(val) >= 52) { 374 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); 375 return; 376 } 377 378 /* Slow path. Initialize the low 32 bits, then concat high bits. */ 379 tcg_out_movi_i32(s, rd, val); 380 rd_high_bits_are_ones = (int32_t)val < 0; 381 382 if (imm_part_needs_loading(rd_high_bits_are_ones, hi32)) { 383 tcg_out_opc_cu32i_d(s, rd, hi32); 384 rd_high_bits_are_ones = hi32 < 0; 385 } 386 387 if (imm_part_needs_loading(rd_high_bits_are_ones, hi52)) { 388 tcg_out_opc_cu52i_d(s, rd, rd, hi52); 389 } 390} 391 392static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 393{ 394 tcg_out_opc_andi(s, ret, arg, 0xff); 395} 396 397static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 398{ 399 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); 400} 401 402static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 403{ 404 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); 405} 406 407static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) 408{ 409 tcg_out_opc_sext_b(s, ret, arg); 410} 411 412static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) 413{ 414 tcg_out_opc_sext_h(s, ret, arg); 415} 416 417static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 418{ 419 tcg_out_opc_addi_w(s, ret, arg, 0); 420} 421 422static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, 423 TCGReg a0, TCGReg a1, TCGReg a2, 424 bool c2, bool is_32bit) 425{ 426 if (c2) { 427 /* 428 * Fast path: semantics already satisfied due to constraint and 429 * insn behavior, single instruction is enough. 430 */ 431 tcg_debug_assert(a2 == (is_32bit ? 32 : 64)); 432 /* all clz/ctz insns belong to DJ-format */ 433 tcg_out32(s, encode_dj_insn(opc, a0, a1)); 434 return; 435 } 436 437 tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1)); 438 /* a0 = a1 ? REG_TMP0 : a2 */ 439 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 440 tcg_out_opc_masknez(s, a0, a2, a1); 441 tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); 442} 443 444static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 445 TCGReg arg1, TCGReg arg2, bool c2) 446{ 447 TCGReg tmp; 448 449 if (c2) { 450 tcg_debug_assert(arg2 == 0); 451 } 452 453 switch (cond) { 454 case TCG_COND_EQ: 455 if (c2) { 456 tmp = arg1; 457 } else { 458 tcg_out_opc_sub_d(s, ret, arg1, arg2); 459 tmp = ret; 460 } 461 tcg_out_opc_sltui(s, ret, tmp, 1); 462 break; 463 case TCG_COND_NE: 464 if (c2) { 465 tmp = arg1; 466 } else { 467 tcg_out_opc_sub_d(s, ret, arg1, arg2); 468 tmp = ret; 469 } 470 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 471 break; 472 case TCG_COND_LT: 473 tcg_out_opc_slt(s, ret, arg1, arg2); 474 break; 475 case TCG_COND_GE: 476 tcg_out_opc_slt(s, ret, arg1, arg2); 477 tcg_out_opc_xori(s, ret, ret, 1); 478 break; 479 case TCG_COND_LE: 480 tcg_out_setcond(s, TCG_COND_GE, ret, arg2, arg1, false); 481 break; 482 case TCG_COND_GT: 483 tcg_out_setcond(s, TCG_COND_LT, ret, arg2, arg1, false); 484 break; 485 case TCG_COND_LTU: 486 tcg_out_opc_sltu(s, ret, arg1, arg2); 487 break; 488 case TCG_COND_GEU: 489 tcg_out_opc_sltu(s, ret, arg1, arg2); 490 tcg_out_opc_xori(s, ret, ret, 1); 491 break; 492 case TCG_COND_LEU: 493 tcg_out_setcond(s, TCG_COND_GEU, ret, arg2, arg1, false); 494 break; 495 case TCG_COND_GTU: 496 tcg_out_setcond(s, TCG_COND_LTU, ret, arg2, arg1, false); 497 break; 498 default: 499 g_assert_not_reached(); 500 break; 501 } 502} 503 504/* 505 * Branch helpers 506 */ 507 508static const struct { 509 LoongArchInsn op; 510 bool swap; 511} tcg_brcond_to_loongarch[] = { 512 [TCG_COND_EQ] = { OPC_BEQ, false }, 513 [TCG_COND_NE] = { OPC_BNE, false }, 514 [TCG_COND_LT] = { OPC_BGT, true }, 515 [TCG_COND_GE] = { OPC_BLE, true }, 516 [TCG_COND_LE] = { OPC_BLE, false }, 517 [TCG_COND_GT] = { OPC_BGT, false }, 518 [TCG_COND_LTU] = { OPC_BGTU, true }, 519 [TCG_COND_GEU] = { OPC_BLEU, true }, 520 [TCG_COND_LEU] = { OPC_BLEU, false }, 521 [TCG_COND_GTU] = { OPC_BGTU, false } 522}; 523 524static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 525 TCGReg arg2, TCGLabel *l) 526{ 527 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; 528 529 tcg_debug_assert(op != 0); 530 531 if (tcg_brcond_to_loongarch[cond].swap) { 532 TCGReg t = arg1; 533 arg1 = arg2; 534 arg2 = t; 535 } 536 537 /* all conditional branch insns belong to DJSk16-format */ 538 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); 539 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); 540} 541 542static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 543{ 544 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 545 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 546 547 tcg_debug_assert((offset & 3) == 0); 548 if (offset == sextreg(offset, 0, 28)) { 549 /* short jump: +/- 256MiB */ 550 if (tail) { 551 tcg_out_opc_b(s, offset >> 2); 552 } else { 553 tcg_out_opc_bl(s, offset >> 2); 554 } 555 } else if (offset == sextreg(offset, 0, 38)) { 556 /* long jump: +/- 256GiB */ 557 tcg_target_long lo = sextreg(offset, 0, 18); 558 tcg_target_long hi = offset - lo; 559 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); 560 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 561 } else { 562 /* far jump: 64-bit */ 563 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18); 564 tcg_target_long hi = (tcg_target_long)arg - lo; 565 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); 566 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 567 } 568} 569 570static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 571 const TCGHelperInfo *info) 572{ 573 tcg_out_call_int(s, arg, false); 574} 575 576/* 577 * Load/store helpers 578 */ 579 580static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, 581 TCGReg addr, intptr_t offset) 582{ 583 intptr_t imm12 = sextreg(offset, 0, 12); 584 585 if (offset != imm12) { 586 intptr_t diff = offset - (uintptr_t)s->code_ptr; 587 588 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 589 imm12 = sextreg(diff, 0, 12); 590 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); 591 } else { 592 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 593 if (addr != TCG_REG_ZERO) { 594 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); 595 } 596 } 597 addr = TCG_REG_TMP2; 598 } 599 600 switch (opc) { 601 case OPC_LD_B: 602 case OPC_LD_BU: 603 case OPC_LD_H: 604 case OPC_LD_HU: 605 case OPC_LD_W: 606 case OPC_LD_WU: 607 case OPC_LD_D: 608 case OPC_ST_B: 609 case OPC_ST_H: 610 case OPC_ST_W: 611 case OPC_ST_D: 612 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); 613 break; 614 default: 615 g_assert_not_reached(); 616 } 617} 618 619static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 620 TCGReg arg1, intptr_t arg2) 621{ 622 bool is_32bit = type == TCG_TYPE_I32; 623 tcg_out_ldst(s, is_32bit ? OPC_LD_W : OPC_LD_D, arg, arg1, arg2); 624} 625 626static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 627 TCGReg arg1, intptr_t arg2) 628{ 629 bool is_32bit = type == TCG_TYPE_I32; 630 tcg_out_ldst(s, is_32bit ? OPC_ST_W : OPC_ST_D, arg, arg1, arg2); 631} 632 633static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 634 TCGReg base, intptr_t ofs) 635{ 636 if (val == 0) { 637 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 638 return true; 639 } 640 return false; 641} 642 643/* 644 * Load/store helpers for SoftMMU, and qemu_ld/st implementations 645 */ 646 647#if defined(CONFIG_SOFTMMU) 648/* 649 * helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, 650 * MemOpIdx oi, uintptr_t ra) 651 */ 652static void * const qemu_ld_helpers[4] = { 653 [MO_8] = helper_ret_ldub_mmu, 654 [MO_16] = helper_le_lduw_mmu, 655 [MO_32] = helper_le_ldul_mmu, 656 [MO_64] = helper_le_ldq_mmu, 657}; 658 659/* 660 * helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, 661 * uintxx_t val, MemOpIdx oi, 662 * uintptr_t ra) 663 */ 664static void * const qemu_st_helpers[4] = { 665 [MO_8] = helper_ret_stb_mmu, 666 [MO_16] = helper_le_stw_mmu, 667 [MO_32] = helper_le_stl_mmu, 668 [MO_64] = helper_le_stq_mmu, 669}; 670 671/* We expect to use a 12-bit negative offset from ENV. */ 672QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 673QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); 674 675static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 676{ 677 tcg_out_opc_b(s, 0); 678 return reloc_br_sd10k16(s->code_ptr - 1, target); 679} 680 681/* 682 * Emits common code for TLB addend lookup, that eventually loads the 683 * addend in TCG_REG_TMP2. 684 */ 685static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, MemOpIdx oi, 686 tcg_insn_unit **label_ptr, bool is_load) 687{ 688 MemOp opc = get_memop(oi); 689 unsigned s_bits = opc & MO_SIZE; 690 unsigned a_bits = get_alignment_bits(opc); 691 tcg_target_long compare_mask; 692 int mem_index = get_mmuidx(oi); 693 int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); 694 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 695 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 696 697 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 698 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 699 700 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addrl, 701 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 702 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 703 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 704 705 /* Load the tlb comparator and the addend. */ 706 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, 707 is_load ? offsetof(CPUTLBEntry, addr_read) 708 : offsetof(CPUTLBEntry, addr_write)); 709 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 710 offsetof(CPUTLBEntry, addend)); 711 712 /* We don't support unaligned accesses. */ 713 if (a_bits < s_bits) { 714 a_bits = s_bits; 715 } 716 /* Clear the non-page, non-alignment bits from the address. */ 717 compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1); 718 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); 719 tcg_out_opc_and(s, TCG_REG_TMP1, TCG_REG_TMP1, addrl); 720 721 /* Compare masked address with the TLB entry. */ 722 label_ptr[0] = s->code_ptr; 723 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); 724 725 /* TLB Hit - addend in TCG_REG_TMP2, ready for use. */ 726} 727 728static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, 729 TCGType type, 730 TCGReg datalo, TCGReg addrlo, 731 void *raddr, tcg_insn_unit **label_ptr) 732{ 733 TCGLabelQemuLdst *label = new_ldst_label(s); 734 735 label->is_ld = is_ld; 736 label->oi = oi; 737 label->type = type; 738 label->datalo_reg = datalo; 739 label->datahi_reg = 0; /* unused */ 740 label->addrlo_reg = addrlo; 741 label->addrhi_reg = 0; /* unused */ 742 label->raddr = tcg_splitwx_to_rx(raddr); 743 label->label_ptr[0] = label_ptr[0]; 744} 745 746static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 747{ 748 MemOpIdx oi = l->oi; 749 MemOp opc = get_memop(oi); 750 MemOp size = opc & MO_SIZE; 751 TCGType type = l->type; 752 753 /* resolve label address */ 754 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 755 return false; 756 } 757 758 /* call load helper */ 759 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); 760 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); 761 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A2, oi); 762 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, (tcg_target_long)l->raddr); 763 764 tcg_out_call_int(s, qemu_ld_helpers[size], false); 765 766 switch (opc & MO_SSIZE) { 767 case MO_SB: 768 tcg_out_ext8s(s, l->datalo_reg, TCG_REG_A0); 769 break; 770 case MO_SW: 771 tcg_out_ext16s(s, l->datalo_reg, TCG_REG_A0); 772 break; 773 case MO_SL: 774 tcg_out_ext32s(s, l->datalo_reg, TCG_REG_A0); 775 break; 776 case MO_UL: 777 if (type == TCG_TYPE_I32) { 778 /* MO_UL loads of i32 should be sign-extended too */ 779 tcg_out_ext32s(s, l->datalo_reg, TCG_REG_A0); 780 break; 781 } 782 /* fallthrough */ 783 default: 784 tcg_out_mov(s, type, l->datalo_reg, TCG_REG_A0); 785 break; 786 } 787 788 return tcg_out_goto(s, l->raddr); 789} 790 791static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 792{ 793 MemOpIdx oi = l->oi; 794 MemOp opc = get_memop(oi); 795 MemOp size = opc & MO_SIZE; 796 797 /* resolve label address */ 798 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 799 return false; 800 } 801 802 /* call store helper */ 803 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); 804 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A1, l->addrlo_reg); 805 switch (size) { 806 case MO_8: 807 tcg_out_ext8u(s, TCG_REG_A2, l->datalo_reg); 808 break; 809 case MO_16: 810 tcg_out_ext16u(s, TCG_REG_A2, l->datalo_reg); 811 break; 812 case MO_32: 813 tcg_out_ext32u(s, TCG_REG_A2, l->datalo_reg); 814 break; 815 case MO_64: 816 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_A2, l->datalo_reg); 817 break; 818 default: 819 g_assert_not_reached(); 820 break; 821 } 822 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A3, oi); 823 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A4, (tcg_target_long)l->raddr); 824 825 tcg_out_call_int(s, qemu_st_helpers[size], false); 826 827 return tcg_out_goto(s, l->raddr); 828} 829#else 830 831/* 832 * Alignment helpers for user-mode emulation 833 */ 834 835static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg, 836 unsigned a_bits) 837{ 838 TCGLabelQemuLdst *l = new_ldst_label(s); 839 840 l->is_ld = is_ld; 841 l->addrlo_reg = addr_reg; 842 843 /* 844 * Without micro-architecture details, we don't know which of bstrpick or 845 * andi is faster, so use bstrpick as it's not constrained by imm field 846 * width. (Not to say alignments >= 2^12 are going to happen any time 847 * soon, though) 848 */ 849 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); 850 851 l->label_ptr[0] = s->code_ptr; 852 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); 853 854 l->raddr = tcg_splitwx_to_rx(s->code_ptr); 855} 856 857static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 858{ 859 /* resolve label address */ 860 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 861 return false; 862 } 863 864 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); 865 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); 866 867 /* tail call, with the return address back inline. */ 868 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr); 869 tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld 870 : helper_unaligned_st), true); 871 return true; 872} 873 874static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 875{ 876 return tcg_out_fail_alignment(s, l); 877} 878 879static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 880{ 881 return tcg_out_fail_alignment(s, l); 882} 883 884#endif /* CONFIG_SOFTMMU */ 885 886/* 887 * `ext32u` the address register into the temp register given, 888 * if target is 32-bit, no-op otherwise. 889 * 890 * Returns the address register ready for use with TLB addend. 891 */ 892static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s, 893 TCGReg addr, TCGReg tmp) 894{ 895 if (TARGET_LONG_BITS == 32) { 896 tcg_out_ext32u(s, tmp, addr); 897 return tmp; 898 } 899 return addr; 900} 901 902static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj, 903 TCGReg rk, MemOp opc, TCGType type) 904{ 905 /* Byte swapping is left to middle-end expansion. */ 906 tcg_debug_assert((opc & MO_BSWAP) == 0); 907 908 switch (opc & MO_SSIZE) { 909 case MO_UB: 910 tcg_out_opc_ldx_bu(s, rd, rj, rk); 911 break; 912 case MO_SB: 913 tcg_out_opc_ldx_b(s, rd, rj, rk); 914 break; 915 case MO_UW: 916 tcg_out_opc_ldx_hu(s, rd, rj, rk); 917 break; 918 case MO_SW: 919 tcg_out_opc_ldx_h(s, rd, rj, rk); 920 break; 921 case MO_UL: 922 if (type == TCG_TYPE_I64) { 923 tcg_out_opc_ldx_wu(s, rd, rj, rk); 924 break; 925 } 926 /* fallthrough */ 927 case MO_SL: 928 tcg_out_opc_ldx_w(s, rd, rj, rk); 929 break; 930 case MO_UQ: 931 tcg_out_opc_ldx_d(s, rd, rj, rk); 932 break; 933 default: 934 g_assert_not_reached(); 935 } 936} 937 938static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type) 939{ 940 TCGReg addr_regl; 941 TCGReg data_regl; 942 MemOpIdx oi; 943 MemOp opc; 944#if defined(CONFIG_SOFTMMU) 945 tcg_insn_unit *label_ptr[1]; 946#else 947 unsigned a_bits; 948#endif 949 TCGReg base; 950 951 data_regl = *args++; 952 addr_regl = *args++; 953 oi = *args++; 954 opc = get_memop(oi); 955 956#if defined(CONFIG_SOFTMMU) 957 tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1); 958 base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); 959 tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type); 960 add_qemu_ldst_label(s, 1, oi, type, 961 data_regl, addr_regl, 962 s->code_ptr, label_ptr); 963#else 964 a_bits = get_alignment_bits(opc); 965 if (a_bits) { 966 tcg_out_test_alignment(s, true, addr_regl, a_bits); 967 } 968 base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); 969 TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 970 tcg_out_qemu_ld_indexed(s, data_regl, base, guest_base_reg, opc, type); 971#endif 972} 973 974static void tcg_out_qemu_st_indexed(TCGContext *s, TCGReg data, 975 TCGReg rj, TCGReg rk, MemOp opc) 976{ 977 /* Byte swapping is left to middle-end expansion. */ 978 tcg_debug_assert((opc & MO_BSWAP) == 0); 979 980 switch (opc & MO_SIZE) { 981 case MO_8: 982 tcg_out_opc_stx_b(s, data, rj, rk); 983 break; 984 case MO_16: 985 tcg_out_opc_stx_h(s, data, rj, rk); 986 break; 987 case MO_32: 988 tcg_out_opc_stx_w(s, data, rj, rk); 989 break; 990 case MO_64: 991 tcg_out_opc_stx_d(s, data, rj, rk); 992 break; 993 default: 994 g_assert_not_reached(); 995 } 996} 997 998static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args) 999{ 1000 TCGReg addr_regl; 1001 TCGReg data_regl; 1002 MemOpIdx oi; 1003 MemOp opc; 1004#if defined(CONFIG_SOFTMMU) 1005 tcg_insn_unit *label_ptr[1]; 1006#else 1007 unsigned a_bits; 1008#endif 1009 TCGReg base; 1010 1011 data_regl = *args++; 1012 addr_regl = *args++; 1013 oi = *args++; 1014 opc = get_memop(oi); 1015 1016#if defined(CONFIG_SOFTMMU) 1017 tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0); 1018 base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); 1019 tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc); 1020 add_qemu_ldst_label(s, 0, oi, 1021 0, /* type param is unused for stores */ 1022 data_regl, addr_regl, 1023 s->code_ptr, label_ptr); 1024#else 1025 a_bits = get_alignment_bits(opc); 1026 if (a_bits) { 1027 tcg_out_test_alignment(s, false, addr_regl, a_bits); 1028 } 1029 base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); 1030 TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 1031 tcg_out_qemu_st_indexed(s, data_regl, base, guest_base_reg, opc); 1032#endif 1033} 1034 1035/* LoongArch uses `andi zero, zero, 0` as NOP. */ 1036#define NOP OPC_ANDI 1037static void tcg_out_nop(TCGContext *s) 1038{ 1039 tcg_out32(s, NOP); 1040} 1041 1042void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, 1043 uintptr_t jmp_rw, uintptr_t addr) 1044{ 1045 tcg_insn_unit i1, i2; 1046 ptrdiff_t upper, lower; 1047 ptrdiff_t offset = (ptrdiff_t)(addr - jmp_rx) >> 2; 1048 1049 if (offset == sextreg(offset, 0, 26)) { 1050 i1 = encode_sd10k16_insn(OPC_B, offset); 1051 i2 = NOP; 1052 } else { 1053 tcg_debug_assert(offset == sextreg(offset, 0, 36)); 1054 lower = (int16_t)offset; 1055 upper = (offset - lower) >> 16; 1056 1057 i1 = encode_dsj20_insn(OPC_PCADDU18I, TCG_REG_TMP0, upper); 1058 i2 = encode_djsk16_insn(OPC_JIRL, TCG_REG_ZERO, TCG_REG_TMP0, lower); 1059 } 1060 uint64_t pair = ((uint64_t)i2 << 32) | i1; 1061 qatomic_set((uint64_t *)jmp_rw, pair); 1062 flush_idcache_range(jmp_rx, jmp_rw, 8); 1063} 1064 1065/* 1066 * Entry-points 1067 */ 1068 1069static const tcg_insn_unit *tb_ret_addr; 1070 1071static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1072 const TCGArg args[TCG_MAX_OP_ARGS], 1073 const int const_args[TCG_MAX_OP_ARGS]) 1074{ 1075 TCGArg a0 = args[0]; 1076 TCGArg a1 = args[1]; 1077 TCGArg a2 = args[2]; 1078 int c2 = const_args[2]; 1079 1080 switch (opc) { 1081 case INDEX_op_exit_tb: 1082 /* Reuse the zeroing that exists for goto_ptr. */ 1083 if (a0 == 0) { 1084 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1085 } else { 1086 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1087 tcg_out_call_int(s, tb_ret_addr, true); 1088 } 1089 break; 1090 1091 case INDEX_op_goto_tb: 1092 tcg_debug_assert(s->tb_jmp_insn_offset != NULL); 1093 /* 1094 * Ensure that patch area is 8-byte aligned so that an 1095 * atomic write can be used to patch the target address. 1096 */ 1097 if ((uintptr_t)s->code_ptr & 7) { 1098 tcg_out_nop(s); 1099 } 1100 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); 1101 /* 1102 * actual branch destination will be patched by 1103 * tb_target_set_jmp_target later 1104 */ 1105 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, 0); 1106 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1107 set_jmp_reset_offset(s, a0); 1108 break; 1109 1110 case INDEX_op_mb: 1111 tcg_out_mb(s, a0); 1112 break; 1113 1114 case INDEX_op_goto_ptr: 1115 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); 1116 break; 1117 1118 case INDEX_op_br: 1119 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0), 1120 0); 1121 tcg_out_opc_b(s, 0); 1122 break; 1123 1124 case INDEX_op_brcond_i32: 1125 case INDEX_op_brcond_i64: 1126 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1127 break; 1128 1129 case INDEX_op_ext8s_i32: 1130 case INDEX_op_ext8s_i64: 1131 tcg_out_ext8s(s, a0, a1); 1132 break; 1133 1134 case INDEX_op_ext8u_i32: 1135 case INDEX_op_ext8u_i64: 1136 tcg_out_ext8u(s, a0, a1); 1137 break; 1138 1139 case INDEX_op_ext16s_i32: 1140 case INDEX_op_ext16s_i64: 1141 tcg_out_ext16s(s, a0, a1); 1142 break; 1143 1144 case INDEX_op_ext16u_i32: 1145 case INDEX_op_ext16u_i64: 1146 tcg_out_ext16u(s, a0, a1); 1147 break; 1148 1149 case INDEX_op_ext32u_i64: 1150 case INDEX_op_extu_i32_i64: 1151 tcg_out_ext32u(s, a0, a1); 1152 break; 1153 1154 case INDEX_op_ext32s_i64: 1155 case INDEX_op_extrl_i64_i32: 1156 case INDEX_op_ext_i32_i64: 1157 tcg_out_ext32s(s, a0, a1); 1158 break; 1159 1160 case INDEX_op_extrh_i64_i32: 1161 tcg_out_opc_srai_d(s, a0, a1, 32); 1162 break; 1163 1164 case INDEX_op_not_i32: 1165 case INDEX_op_not_i64: 1166 tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO); 1167 break; 1168 1169 case INDEX_op_nor_i32: 1170 case INDEX_op_nor_i64: 1171 if (c2) { 1172 tcg_out_opc_ori(s, a0, a1, a2); 1173 tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO); 1174 } else { 1175 tcg_out_opc_nor(s, a0, a1, a2); 1176 } 1177 break; 1178 1179 case INDEX_op_andc_i32: 1180 case INDEX_op_andc_i64: 1181 if (c2) { 1182 /* guaranteed to fit due to constraint */ 1183 tcg_out_opc_andi(s, a0, a1, ~a2); 1184 } else { 1185 tcg_out_opc_andn(s, a0, a1, a2); 1186 } 1187 break; 1188 1189 case INDEX_op_orc_i32: 1190 case INDEX_op_orc_i64: 1191 if (c2) { 1192 /* guaranteed to fit due to constraint */ 1193 tcg_out_opc_ori(s, a0, a1, ~a2); 1194 } else { 1195 tcg_out_opc_orn(s, a0, a1, a2); 1196 } 1197 break; 1198 1199 case INDEX_op_and_i32: 1200 case INDEX_op_and_i64: 1201 if (c2) { 1202 tcg_out_opc_andi(s, a0, a1, a2); 1203 } else { 1204 tcg_out_opc_and(s, a0, a1, a2); 1205 } 1206 break; 1207 1208 case INDEX_op_or_i32: 1209 case INDEX_op_or_i64: 1210 if (c2) { 1211 tcg_out_opc_ori(s, a0, a1, a2); 1212 } else { 1213 tcg_out_opc_or(s, a0, a1, a2); 1214 } 1215 break; 1216 1217 case INDEX_op_xor_i32: 1218 case INDEX_op_xor_i64: 1219 if (c2) { 1220 tcg_out_opc_xori(s, a0, a1, a2); 1221 } else { 1222 tcg_out_opc_xor(s, a0, a1, a2); 1223 } 1224 break; 1225 1226 case INDEX_op_extract_i32: 1227 tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); 1228 break; 1229 case INDEX_op_extract_i64: 1230 tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); 1231 break; 1232 1233 case INDEX_op_deposit_i32: 1234 tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); 1235 break; 1236 case INDEX_op_deposit_i64: 1237 tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); 1238 break; 1239 1240 case INDEX_op_bswap16_i32: 1241 case INDEX_op_bswap16_i64: 1242 tcg_out_opc_revb_2h(s, a0, a1); 1243 if (a2 & TCG_BSWAP_OS) { 1244 tcg_out_ext16s(s, a0, a0); 1245 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1246 tcg_out_ext16u(s, a0, a0); 1247 } 1248 break; 1249 1250 case INDEX_op_bswap32_i32: 1251 /* All 32-bit values are computed sign-extended in the register. */ 1252 a2 = TCG_BSWAP_OS; 1253 /* fallthrough */ 1254 case INDEX_op_bswap32_i64: 1255 tcg_out_opc_revb_2w(s, a0, a1); 1256 if (a2 & TCG_BSWAP_OS) { 1257 tcg_out_ext32s(s, a0, a0); 1258 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1259 tcg_out_ext32u(s, a0, a0); 1260 } 1261 break; 1262 1263 case INDEX_op_bswap64_i64: 1264 tcg_out_opc_revb_d(s, a0, a1); 1265 break; 1266 1267 case INDEX_op_clz_i32: 1268 tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true); 1269 break; 1270 case INDEX_op_clz_i64: 1271 tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false); 1272 break; 1273 1274 case INDEX_op_ctz_i32: 1275 tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true); 1276 break; 1277 case INDEX_op_ctz_i64: 1278 tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false); 1279 break; 1280 1281 case INDEX_op_shl_i32: 1282 if (c2) { 1283 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); 1284 } else { 1285 tcg_out_opc_sll_w(s, a0, a1, a2); 1286 } 1287 break; 1288 case INDEX_op_shl_i64: 1289 if (c2) { 1290 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); 1291 } else { 1292 tcg_out_opc_sll_d(s, a0, a1, a2); 1293 } 1294 break; 1295 1296 case INDEX_op_shr_i32: 1297 if (c2) { 1298 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); 1299 } else { 1300 tcg_out_opc_srl_w(s, a0, a1, a2); 1301 } 1302 break; 1303 case INDEX_op_shr_i64: 1304 if (c2) { 1305 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); 1306 } else { 1307 tcg_out_opc_srl_d(s, a0, a1, a2); 1308 } 1309 break; 1310 1311 case INDEX_op_sar_i32: 1312 if (c2) { 1313 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); 1314 } else { 1315 tcg_out_opc_sra_w(s, a0, a1, a2); 1316 } 1317 break; 1318 case INDEX_op_sar_i64: 1319 if (c2) { 1320 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); 1321 } else { 1322 tcg_out_opc_sra_d(s, a0, a1, a2); 1323 } 1324 break; 1325 1326 case INDEX_op_rotl_i32: 1327 /* transform into equivalent rotr/rotri */ 1328 if (c2) { 1329 tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f); 1330 } else { 1331 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1332 tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0); 1333 } 1334 break; 1335 case INDEX_op_rotl_i64: 1336 /* transform into equivalent rotr/rotri */ 1337 if (c2) { 1338 tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f); 1339 } else { 1340 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1341 tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0); 1342 } 1343 break; 1344 1345 case INDEX_op_rotr_i32: 1346 if (c2) { 1347 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); 1348 } else { 1349 tcg_out_opc_rotr_w(s, a0, a1, a2); 1350 } 1351 break; 1352 case INDEX_op_rotr_i64: 1353 if (c2) { 1354 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); 1355 } else { 1356 tcg_out_opc_rotr_d(s, a0, a1, a2); 1357 } 1358 break; 1359 1360 case INDEX_op_add_i32: 1361 if (c2) { 1362 tcg_out_opc_addi_w(s, a0, a1, a2); 1363 } else { 1364 tcg_out_opc_add_w(s, a0, a1, a2); 1365 } 1366 break; 1367 case INDEX_op_add_i64: 1368 if (c2) { 1369 tcg_out_opc_addi_d(s, a0, a1, a2); 1370 } else { 1371 tcg_out_opc_add_d(s, a0, a1, a2); 1372 } 1373 break; 1374 1375 case INDEX_op_sub_i32: 1376 if (c2) { 1377 tcg_out_opc_addi_w(s, a0, a1, -a2); 1378 } else { 1379 tcg_out_opc_sub_w(s, a0, a1, a2); 1380 } 1381 break; 1382 case INDEX_op_sub_i64: 1383 if (c2) { 1384 tcg_out_opc_addi_d(s, a0, a1, -a2); 1385 } else { 1386 tcg_out_opc_sub_d(s, a0, a1, a2); 1387 } 1388 break; 1389 1390 case INDEX_op_mul_i32: 1391 tcg_out_opc_mul_w(s, a0, a1, a2); 1392 break; 1393 case INDEX_op_mul_i64: 1394 tcg_out_opc_mul_d(s, a0, a1, a2); 1395 break; 1396 1397 case INDEX_op_mulsh_i32: 1398 tcg_out_opc_mulh_w(s, a0, a1, a2); 1399 break; 1400 case INDEX_op_mulsh_i64: 1401 tcg_out_opc_mulh_d(s, a0, a1, a2); 1402 break; 1403 1404 case INDEX_op_muluh_i32: 1405 tcg_out_opc_mulh_wu(s, a0, a1, a2); 1406 break; 1407 case INDEX_op_muluh_i64: 1408 tcg_out_opc_mulh_du(s, a0, a1, a2); 1409 break; 1410 1411 case INDEX_op_div_i32: 1412 tcg_out_opc_div_w(s, a0, a1, a2); 1413 break; 1414 case INDEX_op_div_i64: 1415 tcg_out_opc_div_d(s, a0, a1, a2); 1416 break; 1417 1418 case INDEX_op_divu_i32: 1419 tcg_out_opc_div_wu(s, a0, a1, a2); 1420 break; 1421 case INDEX_op_divu_i64: 1422 tcg_out_opc_div_du(s, a0, a1, a2); 1423 break; 1424 1425 case INDEX_op_rem_i32: 1426 tcg_out_opc_mod_w(s, a0, a1, a2); 1427 break; 1428 case INDEX_op_rem_i64: 1429 tcg_out_opc_mod_d(s, a0, a1, a2); 1430 break; 1431 1432 case INDEX_op_remu_i32: 1433 tcg_out_opc_mod_wu(s, a0, a1, a2); 1434 break; 1435 case INDEX_op_remu_i64: 1436 tcg_out_opc_mod_du(s, a0, a1, a2); 1437 break; 1438 1439 case INDEX_op_setcond_i32: 1440 case INDEX_op_setcond_i64: 1441 tcg_out_setcond(s, args[3], a0, a1, a2, c2); 1442 break; 1443 1444 case INDEX_op_ld8s_i32: 1445 case INDEX_op_ld8s_i64: 1446 tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); 1447 break; 1448 case INDEX_op_ld8u_i32: 1449 case INDEX_op_ld8u_i64: 1450 tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2); 1451 break; 1452 case INDEX_op_ld16s_i32: 1453 case INDEX_op_ld16s_i64: 1454 tcg_out_ldst(s, OPC_LD_H, a0, a1, a2); 1455 break; 1456 case INDEX_op_ld16u_i32: 1457 case INDEX_op_ld16u_i64: 1458 tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2); 1459 break; 1460 case INDEX_op_ld_i32: 1461 case INDEX_op_ld32s_i64: 1462 tcg_out_ldst(s, OPC_LD_W, a0, a1, a2); 1463 break; 1464 case INDEX_op_ld32u_i64: 1465 tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2); 1466 break; 1467 case INDEX_op_ld_i64: 1468 tcg_out_ldst(s, OPC_LD_D, a0, a1, a2); 1469 break; 1470 1471 case INDEX_op_st8_i32: 1472 case INDEX_op_st8_i64: 1473 tcg_out_ldst(s, OPC_ST_B, a0, a1, a2); 1474 break; 1475 case INDEX_op_st16_i32: 1476 case INDEX_op_st16_i64: 1477 tcg_out_ldst(s, OPC_ST_H, a0, a1, a2); 1478 break; 1479 case INDEX_op_st_i32: 1480 case INDEX_op_st32_i64: 1481 tcg_out_ldst(s, OPC_ST_W, a0, a1, a2); 1482 break; 1483 case INDEX_op_st_i64: 1484 tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); 1485 break; 1486 1487 case INDEX_op_qemu_ld_i32: 1488 tcg_out_qemu_ld(s, args, TCG_TYPE_I32); 1489 break; 1490 case INDEX_op_qemu_ld_i64: 1491 tcg_out_qemu_ld(s, args, TCG_TYPE_I64); 1492 break; 1493 case INDEX_op_qemu_st_i32: 1494 tcg_out_qemu_st(s, args); 1495 break; 1496 case INDEX_op_qemu_st_i64: 1497 tcg_out_qemu_st(s, args); 1498 break; 1499 1500 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1501 case INDEX_op_mov_i64: 1502 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1503 default: 1504 g_assert_not_reached(); 1505 } 1506} 1507 1508static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 1509{ 1510 switch (op) { 1511 case INDEX_op_goto_ptr: 1512 return C_O0_I1(r); 1513 1514 case INDEX_op_st8_i32: 1515 case INDEX_op_st8_i64: 1516 case INDEX_op_st16_i32: 1517 case INDEX_op_st16_i64: 1518 case INDEX_op_st32_i64: 1519 case INDEX_op_st_i32: 1520 case INDEX_op_st_i64: 1521 return C_O0_I2(rZ, r); 1522 1523 case INDEX_op_brcond_i32: 1524 case INDEX_op_brcond_i64: 1525 return C_O0_I2(rZ, rZ); 1526 1527 case INDEX_op_qemu_st_i32: 1528 case INDEX_op_qemu_st_i64: 1529 return C_O0_I2(LZ, L); 1530 1531 case INDEX_op_ext8s_i32: 1532 case INDEX_op_ext8s_i64: 1533 case INDEX_op_ext8u_i32: 1534 case INDEX_op_ext8u_i64: 1535 case INDEX_op_ext16s_i32: 1536 case INDEX_op_ext16s_i64: 1537 case INDEX_op_ext16u_i32: 1538 case INDEX_op_ext16u_i64: 1539 case INDEX_op_ext32s_i64: 1540 case INDEX_op_ext32u_i64: 1541 case INDEX_op_extu_i32_i64: 1542 case INDEX_op_extrl_i64_i32: 1543 case INDEX_op_extrh_i64_i32: 1544 case INDEX_op_ext_i32_i64: 1545 case INDEX_op_not_i32: 1546 case INDEX_op_not_i64: 1547 case INDEX_op_extract_i32: 1548 case INDEX_op_extract_i64: 1549 case INDEX_op_bswap16_i32: 1550 case INDEX_op_bswap16_i64: 1551 case INDEX_op_bswap32_i32: 1552 case INDEX_op_bswap32_i64: 1553 case INDEX_op_bswap64_i64: 1554 case INDEX_op_ld8s_i32: 1555 case INDEX_op_ld8s_i64: 1556 case INDEX_op_ld8u_i32: 1557 case INDEX_op_ld8u_i64: 1558 case INDEX_op_ld16s_i32: 1559 case INDEX_op_ld16s_i64: 1560 case INDEX_op_ld16u_i32: 1561 case INDEX_op_ld16u_i64: 1562 case INDEX_op_ld32s_i64: 1563 case INDEX_op_ld32u_i64: 1564 case INDEX_op_ld_i32: 1565 case INDEX_op_ld_i64: 1566 return C_O1_I1(r, r); 1567 1568 case INDEX_op_qemu_ld_i32: 1569 case INDEX_op_qemu_ld_i64: 1570 return C_O1_I1(r, L); 1571 1572 case INDEX_op_andc_i32: 1573 case INDEX_op_andc_i64: 1574 case INDEX_op_orc_i32: 1575 case INDEX_op_orc_i64: 1576 /* 1577 * LoongArch insns for these ops don't have reg-imm forms, but we 1578 * can express using andi/ori if ~constant satisfies 1579 * TCG_CT_CONST_U12. 1580 */ 1581 return C_O1_I2(r, r, rC); 1582 1583 case INDEX_op_shl_i32: 1584 case INDEX_op_shl_i64: 1585 case INDEX_op_shr_i32: 1586 case INDEX_op_shr_i64: 1587 case INDEX_op_sar_i32: 1588 case INDEX_op_sar_i64: 1589 case INDEX_op_rotl_i32: 1590 case INDEX_op_rotl_i64: 1591 case INDEX_op_rotr_i32: 1592 case INDEX_op_rotr_i64: 1593 return C_O1_I2(r, r, ri); 1594 1595 case INDEX_op_add_i32: 1596 case INDEX_op_add_i64: 1597 return C_O1_I2(r, r, rI); 1598 1599 case INDEX_op_and_i32: 1600 case INDEX_op_and_i64: 1601 case INDEX_op_nor_i32: 1602 case INDEX_op_nor_i64: 1603 case INDEX_op_or_i32: 1604 case INDEX_op_or_i64: 1605 case INDEX_op_xor_i32: 1606 case INDEX_op_xor_i64: 1607 /* LoongArch reg-imm bitops have their imms ZERO-extended */ 1608 return C_O1_I2(r, r, rU); 1609 1610 case INDEX_op_clz_i32: 1611 case INDEX_op_clz_i64: 1612 case INDEX_op_ctz_i32: 1613 case INDEX_op_ctz_i64: 1614 return C_O1_I2(r, r, rW); 1615 1616 case INDEX_op_setcond_i32: 1617 case INDEX_op_setcond_i64: 1618 return C_O1_I2(r, r, rZ); 1619 1620 case INDEX_op_deposit_i32: 1621 case INDEX_op_deposit_i64: 1622 /* Must deposit into the same register as input */ 1623 return C_O1_I2(r, 0, rZ); 1624 1625 case INDEX_op_sub_i32: 1626 case INDEX_op_sub_i64: 1627 return C_O1_I2(r, rZ, rN); 1628 1629 case INDEX_op_mul_i32: 1630 case INDEX_op_mul_i64: 1631 case INDEX_op_mulsh_i32: 1632 case INDEX_op_mulsh_i64: 1633 case INDEX_op_muluh_i32: 1634 case INDEX_op_muluh_i64: 1635 case INDEX_op_div_i32: 1636 case INDEX_op_div_i64: 1637 case INDEX_op_divu_i32: 1638 case INDEX_op_divu_i64: 1639 case INDEX_op_rem_i32: 1640 case INDEX_op_rem_i64: 1641 case INDEX_op_remu_i32: 1642 case INDEX_op_remu_i64: 1643 return C_O1_I2(r, rZ, rZ); 1644 1645 default: 1646 g_assert_not_reached(); 1647 } 1648} 1649 1650static const int tcg_target_callee_save_regs[] = { 1651 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 1652 TCG_REG_S1, 1653 TCG_REG_S2, 1654 TCG_REG_S3, 1655 TCG_REG_S4, 1656 TCG_REG_S5, 1657 TCG_REG_S6, 1658 TCG_REG_S7, 1659 TCG_REG_S8, 1660 TCG_REG_S9, 1661 TCG_REG_RA, /* should be last for ABI compliance */ 1662}; 1663 1664/* Stack frame parameters. */ 1665#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 1666#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 1667#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 1668#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 1669 + TCG_TARGET_STACK_ALIGN - 1) \ 1670 & -TCG_TARGET_STACK_ALIGN) 1671#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 1672 1673/* We're expecting to be able to use an immediate for frame allocation. */ 1674QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 1675 1676/* Generate global QEMU prologue and epilogue code */ 1677static void tcg_target_qemu_prologue(TCGContext *s) 1678{ 1679 int i; 1680 1681 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 1682 1683 /* TB prologue */ 1684 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 1685 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 1686 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 1687 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 1688 } 1689 1690#if !defined(CONFIG_SOFTMMU) 1691 if (USE_GUEST_BASE) { 1692 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 1693 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 1694 } 1695#endif 1696 1697 /* Call generated code */ 1698 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 1699 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 1700 1701 /* Return path for goto_ptr. Set return value to 0 */ 1702 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 1703 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 1704 1705 /* TB epilogue */ 1706 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 1707 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 1708 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 1709 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 1710 } 1711 1712 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 1713 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); 1714} 1715 1716static void tcg_target_init(TCGContext *s) 1717{ 1718 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 1719 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 1720 1721 tcg_target_call_clobber_regs = ALL_GENERAL_REGS; 1722 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 1723 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 1724 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 1725 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 1726 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 1727 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 1728 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 1729 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 1730 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 1731 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 1732 1733 s->reserved_regs = 0; 1734 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 1735 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 1736 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 1737 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 1738 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 1739 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 1740 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); 1741} 1742 1743typedef struct { 1744 DebugFrameHeader h; 1745 uint8_t fde_def_cfa[4]; 1746 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 1747} DebugFrame; 1748 1749#define ELF_HOST_MACHINE EM_LOONGARCH 1750 1751static const DebugFrame debug_frame = { 1752 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 1753 .h.cie.id = -1, 1754 .h.cie.version = 1, 1755 .h.cie.code_align = 1, 1756 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 1757 .h.cie.return_column = TCG_REG_RA, 1758 1759 /* Total FDE size does not include the "len" member. */ 1760 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 1761 1762 .fde_def_cfa = { 1763 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 1764 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 1765 (FRAME_SIZE >> 7) 1766 }, 1767 .fde_reg_ofs = { 1768 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ 1769 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ 1770 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ 1771 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ 1772 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ 1773 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ 1774 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ 1775 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ 1776 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ 1777 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ 1778 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 1779 } 1780}; 1781 1782void tcg_register_jit(const void *buf, size_t buf_size) 1783{ 1784 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 1785} 1786