1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#ifdef HOST_WORDS_BIGENDIAN 28# define MIPS_BE 1 29#else 30# define MIPS_BE 0 31#endif 32 33#if TCG_TARGET_REG_BITS == 32 34# define LO_OFF (MIPS_BE * 4) 35# define HI_OFF (4 - LO_OFF) 36#else 37/* To assert at compile-time that these values are never used 38 for TCG_TARGET_REG_BITS == 64. */ 39int link_error(void); 40# define LO_OFF link_error() 41# define HI_OFF link_error() 42#endif 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "zero", 47 "at", 48 "v0", 49 "v1", 50 "a0", 51 "a1", 52 "a2", 53 "a3", 54 "t0", 55 "t1", 56 "t2", 57 "t3", 58 "t4", 59 "t5", 60 "t6", 61 "t7", 62 "s0", 63 "s1", 64 "s2", 65 "s3", 66 "s4", 67 "s5", 68 "s6", 69 "s7", 70 "t8", 71 "t9", 72 "k0", 73 "k1", 74 "gp", 75 "sp", 76 "s8", 77 "ra", 78}; 79#endif 80 81#define TCG_TMP0 TCG_REG_AT 82#define TCG_TMP1 TCG_REG_T9 83#define TCG_TMP2 TCG_REG_T8 84#define TCG_TMP3 TCG_REG_T7 85 86#ifndef CONFIG_SOFTMMU 87#define TCG_GUEST_BASE_REG TCG_REG_S1 88#endif 89 90/* check if we really need so many registers :P */ 91static const int tcg_target_reg_alloc_order[] = { 92 /* Call saved registers. */ 93 TCG_REG_S0, 94 TCG_REG_S1, 95 TCG_REG_S2, 96 TCG_REG_S3, 97 TCG_REG_S4, 98 TCG_REG_S5, 99 TCG_REG_S6, 100 TCG_REG_S7, 101 TCG_REG_S8, 102 103 /* Call clobbered registers. */ 104 TCG_REG_T4, 105 TCG_REG_T5, 106 TCG_REG_T6, 107 TCG_REG_T7, 108 TCG_REG_T8, 109 TCG_REG_T9, 110 TCG_REG_V1, 111 TCG_REG_V0, 112 113 /* Argument registers, opposite order of allocation. */ 114 TCG_REG_T3, 115 TCG_REG_T2, 116 TCG_REG_T1, 117 TCG_REG_T0, 118 TCG_REG_A3, 119 TCG_REG_A2, 120 TCG_REG_A1, 121 TCG_REG_A0, 122}; 123 124static const TCGReg tcg_target_call_iarg_regs[] = { 125 TCG_REG_A0, 126 TCG_REG_A1, 127 TCG_REG_A2, 128 TCG_REG_A3, 129#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 130 TCG_REG_T0, 131 TCG_REG_T1, 132 TCG_REG_T2, 133 TCG_REG_T3, 134#endif 135}; 136 137static const TCGReg tcg_target_call_oarg_regs[2] = { 138 TCG_REG_V0, 139 TCG_REG_V1 140}; 141 142static const tcg_insn_unit *tb_ret_addr; 143static const tcg_insn_unit *bswap32_addr; 144static const tcg_insn_unit *bswap32u_addr; 145static const tcg_insn_unit *bswap64_addr; 146 147static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 148{ 149 /* Let the compiler perform the right-shift as part of the arithmetic. */ 150 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 151 ptrdiff_t disp = target - (src_rx + 1); 152 if (disp == (int16_t)disp) { 153 *src_rw = deposit32(*src_rw, 0, 16, disp); 154 return true; 155 } 156 return false; 157} 158 159static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 160 intptr_t value, intptr_t addend) 161{ 162 tcg_debug_assert(type == R_MIPS_PC16); 163 tcg_debug_assert(addend == 0); 164 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 165} 166 167#define TCG_CT_CONST_ZERO 0x100 168#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 169#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 170#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 171#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 172#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 173 174static inline bool is_p2m1(tcg_target_long val) 175{ 176 return val && ((val + 1) & val) == 0; 177} 178 179/* parse target specific constraints */ 180static const char *target_parse_constraint(TCGArgConstraint *ct, 181 const char *ct_str, TCGType type) 182{ 183 switch(*ct_str++) { 184 case 'r': 185 ct->regs = 0xffffffff; 186 break; 187 case 'L': /* qemu_ld input arg constraint */ 188 ct->regs = 0xffffffff; 189 tcg_regset_reset_reg(ct->regs, TCG_REG_A0); 190#if defined(CONFIG_SOFTMMU) 191 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 192 tcg_regset_reset_reg(ct->regs, TCG_REG_A2); 193 } 194#endif 195 break; 196 case 'S': /* qemu_st constraint */ 197 ct->regs = 0xffffffff; 198 tcg_regset_reset_reg(ct->regs, TCG_REG_A0); 199#if defined(CONFIG_SOFTMMU) 200 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 201 tcg_regset_reset_reg(ct->regs, TCG_REG_A2); 202 tcg_regset_reset_reg(ct->regs, TCG_REG_A3); 203 } else { 204 tcg_regset_reset_reg(ct->regs, TCG_REG_A1); 205 } 206#endif 207 break; 208 case 'I': 209 ct->ct |= TCG_CT_CONST_U16; 210 break; 211 case 'J': 212 ct->ct |= TCG_CT_CONST_S16; 213 break; 214 case 'K': 215 ct->ct |= TCG_CT_CONST_P2M1; 216 break; 217 case 'N': 218 ct->ct |= TCG_CT_CONST_N16; 219 break; 220 case 'W': 221 ct->ct |= TCG_CT_CONST_WSZ; 222 break; 223 case 'Z': 224 /* We are cheating a bit here, using the fact that the register 225 ZERO is also the register number 0. Hence there is no need 226 to check for const_args in each instruction. */ 227 ct->ct |= TCG_CT_CONST_ZERO; 228 break; 229 default: 230 return NULL; 231 } 232 return ct_str; 233} 234 235/* test if a constant matches the constraint */ 236static inline int tcg_target_const_match(tcg_target_long val, TCGType type, 237 const TCGArgConstraint *arg_ct) 238{ 239 int ct; 240 ct = arg_ct->ct; 241 if (ct & TCG_CT_CONST) { 242 return 1; 243 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 244 return 1; 245 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 246 return 1; 247 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 248 return 1; 249 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 250 return 1; 251 } else if ((ct & TCG_CT_CONST_P2M1) 252 && use_mips32r2_instructions && is_p2m1(val)) { 253 return 1; 254 } else if ((ct & TCG_CT_CONST_WSZ) 255 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 256 return 1; 257 } 258 return 0; 259} 260 261/* instruction opcodes */ 262typedef enum { 263 OPC_J = 002 << 26, 264 OPC_JAL = 003 << 26, 265 OPC_BEQ = 004 << 26, 266 OPC_BNE = 005 << 26, 267 OPC_BLEZ = 006 << 26, 268 OPC_BGTZ = 007 << 26, 269 OPC_ADDIU = 011 << 26, 270 OPC_SLTI = 012 << 26, 271 OPC_SLTIU = 013 << 26, 272 OPC_ANDI = 014 << 26, 273 OPC_ORI = 015 << 26, 274 OPC_XORI = 016 << 26, 275 OPC_LUI = 017 << 26, 276 OPC_DADDIU = 031 << 26, 277 OPC_LB = 040 << 26, 278 OPC_LH = 041 << 26, 279 OPC_LW = 043 << 26, 280 OPC_LBU = 044 << 26, 281 OPC_LHU = 045 << 26, 282 OPC_LWU = 047 << 26, 283 OPC_SB = 050 << 26, 284 OPC_SH = 051 << 26, 285 OPC_SW = 053 << 26, 286 OPC_LD = 067 << 26, 287 OPC_SD = 077 << 26, 288 289 OPC_SPECIAL = 000 << 26, 290 OPC_SLL = OPC_SPECIAL | 000, 291 OPC_SRL = OPC_SPECIAL | 002, 292 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 293 OPC_SRA = OPC_SPECIAL | 003, 294 OPC_SLLV = OPC_SPECIAL | 004, 295 OPC_SRLV = OPC_SPECIAL | 006, 296 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 297 OPC_SRAV = OPC_SPECIAL | 007, 298 OPC_JR_R5 = OPC_SPECIAL | 010, 299 OPC_JALR = OPC_SPECIAL | 011, 300 OPC_MOVZ = OPC_SPECIAL | 012, 301 OPC_MOVN = OPC_SPECIAL | 013, 302 OPC_SYNC = OPC_SPECIAL | 017, 303 OPC_MFHI = OPC_SPECIAL | 020, 304 OPC_MFLO = OPC_SPECIAL | 022, 305 OPC_DSLLV = OPC_SPECIAL | 024, 306 OPC_DSRLV = OPC_SPECIAL | 026, 307 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 308 OPC_DSRAV = OPC_SPECIAL | 027, 309 OPC_MULT = OPC_SPECIAL | 030, 310 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 311 OPC_MUH = OPC_SPECIAL | 030 | 0300, 312 OPC_MULTU = OPC_SPECIAL | 031, 313 OPC_MULU = OPC_SPECIAL | 031 | 0200, 314 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 315 OPC_DIV = OPC_SPECIAL | 032, 316 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 317 OPC_MOD = OPC_SPECIAL | 032 | 0300, 318 OPC_DIVU = OPC_SPECIAL | 033, 319 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 320 OPC_MODU = OPC_SPECIAL | 033 | 0300, 321 OPC_DMULT = OPC_SPECIAL | 034, 322 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 323 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 324 OPC_DMULTU = OPC_SPECIAL | 035, 325 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 326 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 327 OPC_DDIV = OPC_SPECIAL | 036, 328 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 329 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 330 OPC_DDIVU = OPC_SPECIAL | 037, 331 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 332 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 333 OPC_ADDU = OPC_SPECIAL | 041, 334 OPC_SUBU = OPC_SPECIAL | 043, 335 OPC_AND = OPC_SPECIAL | 044, 336 OPC_OR = OPC_SPECIAL | 045, 337 OPC_XOR = OPC_SPECIAL | 046, 338 OPC_NOR = OPC_SPECIAL | 047, 339 OPC_SLT = OPC_SPECIAL | 052, 340 OPC_SLTU = OPC_SPECIAL | 053, 341 OPC_DADDU = OPC_SPECIAL | 055, 342 OPC_DSUBU = OPC_SPECIAL | 057, 343 OPC_SELEQZ = OPC_SPECIAL | 065, 344 OPC_SELNEZ = OPC_SPECIAL | 067, 345 OPC_DSLL = OPC_SPECIAL | 070, 346 OPC_DSRL = OPC_SPECIAL | 072, 347 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 348 OPC_DSRA = OPC_SPECIAL | 073, 349 OPC_DSLL32 = OPC_SPECIAL | 074, 350 OPC_DSRL32 = OPC_SPECIAL | 076, 351 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 352 OPC_DSRA32 = OPC_SPECIAL | 077, 353 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 354 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 355 356 OPC_REGIMM = 001 << 26, 357 OPC_BLTZ = OPC_REGIMM | (000 << 16), 358 OPC_BGEZ = OPC_REGIMM | (001 << 16), 359 360 OPC_SPECIAL2 = 034 << 26, 361 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 362 OPC_CLZ = OPC_SPECIAL2 | 040, 363 OPC_DCLZ = OPC_SPECIAL2 | 044, 364 365 OPC_SPECIAL3 = 037 << 26, 366 OPC_EXT = OPC_SPECIAL3 | 000, 367 OPC_DEXTM = OPC_SPECIAL3 | 001, 368 OPC_DEXTU = OPC_SPECIAL3 | 002, 369 OPC_DEXT = OPC_SPECIAL3 | 003, 370 OPC_INS = OPC_SPECIAL3 | 004, 371 OPC_DINSM = OPC_SPECIAL3 | 005, 372 OPC_DINSU = OPC_SPECIAL3 | 006, 373 OPC_DINS = OPC_SPECIAL3 | 007, 374 OPC_WSBH = OPC_SPECIAL3 | 00240, 375 OPC_DSBH = OPC_SPECIAL3 | 00244, 376 OPC_DSHD = OPC_SPECIAL3 | 00544, 377 OPC_SEB = OPC_SPECIAL3 | 02040, 378 OPC_SEH = OPC_SPECIAL3 | 03040, 379 380 /* MIPS r6 doesn't have JR, JALR should be used instead */ 381 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 382 383 /* 384 * MIPS r6 replaces MUL with an alternative encoding which is 385 * backwards-compatible at the assembly level. 386 */ 387 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 388 389 /* MIPS r6 introduced names for weaker variants of SYNC. These are 390 backward compatible to previous architecture revisions. */ 391 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 392 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 393 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 394 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 395 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 396 397 /* Aliases for convenience. */ 398 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 399 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 400 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 401 ? OPC_SRL : OPC_DSRL, 402} MIPSInsn; 403 404/* 405 * Type reg 406 */ 407static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 408 TCGReg rd, TCGReg rs, TCGReg rt) 409{ 410 int32_t inst; 411 412 inst = opc; 413 inst |= (rs & 0x1F) << 21; 414 inst |= (rt & 0x1F) << 16; 415 inst |= (rd & 0x1F) << 11; 416 tcg_out32(s, inst); 417} 418 419/* 420 * Type immediate 421 */ 422static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 423 TCGReg rt, TCGReg rs, TCGArg imm) 424{ 425 int32_t inst; 426 427 inst = opc; 428 inst |= (rs & 0x1F) << 21; 429 inst |= (rt & 0x1F) << 16; 430 inst |= (imm & 0xffff); 431 tcg_out32(s, inst); 432} 433 434/* 435 * Type bitfield 436 */ 437static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 438 TCGReg rs, int msb, int lsb) 439{ 440 int32_t inst; 441 442 inst = opc; 443 inst |= (rs & 0x1F) << 21; 444 inst |= (rt & 0x1F) << 16; 445 inst |= (msb & 0x1F) << 11; 446 inst |= (lsb & 0x1F) << 6; 447 tcg_out32(s, inst); 448} 449 450static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 451 MIPSInsn oph, TCGReg rt, TCGReg rs, 452 int msb, int lsb) 453{ 454 if (lsb >= 32) { 455 opc = oph; 456 msb -= 32; 457 lsb -= 32; 458 } else if (msb >= 32) { 459 opc = opm; 460 msb -= 32; 461 } 462 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 463} 464 465/* 466 * Type branch 467 */ 468static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, 469 TCGReg rt, TCGReg rs) 470{ 471 tcg_out_opc_imm(s, opc, rt, rs, 0); 472} 473 474/* 475 * Type sa 476 */ 477static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 478 TCGReg rd, TCGReg rt, TCGArg sa) 479{ 480 int32_t inst; 481 482 inst = opc; 483 inst |= (rt & 0x1F) << 16; 484 inst |= (rd & 0x1F) << 11; 485 inst |= (sa & 0x1F) << 6; 486 tcg_out32(s, inst); 487 488} 489 490static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 491 TCGReg rd, TCGReg rt, TCGArg sa) 492{ 493 int32_t inst; 494 495 inst = (sa & 32 ? opc2 : opc1); 496 inst |= (rt & 0x1F) << 16; 497 inst |= (rd & 0x1F) << 11; 498 inst |= (sa & 0x1F) << 6; 499 tcg_out32(s, inst); 500} 501 502/* 503 * Type jump. 504 * Returns true if the branch was in range and the insn was emitted. 505 */ 506static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 507{ 508 uintptr_t dest = (uintptr_t)target; 509 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 510 int32_t inst; 511 512 /* The pc-region branch happens within the 256MB region of 513 the delay slot (thus the +4). */ 514 if ((from ^ dest) & -(1 << 28)) { 515 return false; 516 } 517 tcg_debug_assert((dest & 3) == 0); 518 519 inst = opc; 520 inst |= (dest >> 2) & 0x3ffffff; 521 tcg_out32(s, inst); 522 return true; 523} 524 525static inline void tcg_out_nop(TCGContext *s) 526{ 527 tcg_out32(s, 0); 528} 529 530static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 531{ 532 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 533} 534 535static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 536{ 537 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 538} 539 540static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 541{ 542 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 543} 544 545static inline bool tcg_out_mov(TCGContext *s, TCGType type, 546 TCGReg ret, TCGReg arg) 547{ 548 /* Simple reg-reg move, optimising out the 'do nothing' case */ 549 if (ret != arg) { 550 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 551 } 552 return true; 553} 554 555static void tcg_out_movi(TCGContext *s, TCGType type, 556 TCGReg ret, tcg_target_long arg) 557{ 558 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 559 arg = (int32_t)arg; 560 } 561 if (arg == (int16_t)arg) { 562 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 563 return; 564 } 565 if (arg == (uint16_t)arg) { 566 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 567 return; 568 } 569 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 570 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 571 } else { 572 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); 573 if (arg & 0xffff0000ull) { 574 tcg_out_dsll(s, ret, ret, 16); 575 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); 576 tcg_out_dsll(s, ret, ret, 16); 577 } else { 578 tcg_out_dsll(s, ret, ret, 32); 579 } 580 } 581 if (arg & 0xffff) { 582 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 583 } 584} 585 586static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) 587{ 588 if (use_mips32r2_instructions) { 589 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 590 } else { 591 /* ret and arg can't be register at */ 592 if (ret == TCG_TMP0 || arg == TCG_TMP0) { 593 tcg_abort(); 594 } 595 596 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); 597 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); 598 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); 599 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); 600 } 601} 602 603static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) 604{ 605 if (use_mips32r2_instructions) { 606 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 607 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); 608 } else { 609 /* ret and arg can't be register at */ 610 if (ret == TCG_TMP0 || arg == TCG_TMP0) { 611 tcg_abort(); 612 } 613 614 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); 615 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); 616 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); 617 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); 618 } 619} 620 621static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 622{ 623 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); 624 tcg_debug_assert(ok); 625} 626 627static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) 628{ 629 if (use_mips32r2_instructions) { 630 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 631 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 632 } else { 633 tcg_out_bswap_subr(s, bswap32_addr); 634 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 635 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 636 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 637 } 638} 639 640static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg) 641{ 642 if (use_mips32r2_instructions) { 643 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 644 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 645 tcg_out_dsrl(s, ret, ret, 32); 646 } else { 647 tcg_out_bswap_subr(s, bswap32u_addr); 648 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 649 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 650 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 651 } 652} 653 654static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 655{ 656 if (use_mips32r2_instructions) { 657 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 658 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 659 } else { 660 tcg_out_bswap_subr(s, bswap64_addr); 661 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 662 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 663 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 664 } 665} 666 667static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) 668{ 669 if (use_mips32r2_instructions) { 670 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); 671 } else { 672 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); 673 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); 674 } 675} 676 677static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) 678{ 679 if (use_mips32r2_instructions) { 680 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); 681 } else { 682 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); 683 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); 684 } 685} 686 687static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 688{ 689 if (use_mips32r2_instructions) { 690 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 691 } else { 692 tcg_out_dsll(s, ret, arg, 32); 693 tcg_out_dsrl(s, ret, ret, 32); 694 } 695} 696 697static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 698 TCGReg addr, intptr_t ofs) 699{ 700 int16_t lo = ofs; 701 if (ofs != lo) { 702 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 703 if (addr != TCG_REG_ZERO) { 704 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 705 } 706 addr = TCG_TMP0; 707 } 708 tcg_out_opc_imm(s, opc, data, addr, lo); 709} 710 711static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 712 TCGReg arg1, intptr_t arg2) 713{ 714 MIPSInsn opc = OPC_LD; 715 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 716 opc = OPC_LW; 717 } 718 tcg_out_ldst(s, opc, arg, arg1, arg2); 719} 720 721static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 722 TCGReg arg1, intptr_t arg2) 723{ 724 MIPSInsn opc = OPC_SD; 725 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 726 opc = OPC_SW; 727 } 728 tcg_out_ldst(s, opc, arg, arg1, arg2); 729} 730 731static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 732 TCGReg base, intptr_t ofs) 733{ 734 if (val == 0) { 735 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 736 return true; 737 } 738 return false; 739} 740 741static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 742 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 743 bool cbh, bool is_sub) 744{ 745 TCGReg th = TCG_TMP1; 746 747 /* If we have a negative constant such that negating it would 748 make the high part zero, we can (usually) eliminate one insn. */ 749 if (cbl && cbh && bh == -1 && bl != 0) { 750 bl = -bl; 751 bh = 0; 752 is_sub = !is_sub; 753 } 754 755 /* By operating on the high part first, we get to use the final 756 carry operation to move back from the temporary. */ 757 if (!cbh) { 758 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 759 } else if (bh != 0 || ah == rl) { 760 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 761 } else { 762 th = ah; 763 } 764 765 /* Note that tcg optimization should eliminate the bl == 0 case. */ 766 if (is_sub) { 767 if (cbl) { 768 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 769 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 770 } else { 771 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 772 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 773 } 774 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 775 } else { 776 if (cbl) { 777 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 778 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 779 } else if (rl == al && rl == bl) { 780 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 781 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 782 } else { 783 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 784 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 785 } 786 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 787 } 788} 789 790/* Bit 0 set if inversion required; bit 1 set if swapping required. */ 791#define MIPS_CMP_INV 1 792#define MIPS_CMP_SWAP 2 793 794static const uint8_t mips_cmp_map[16] = { 795 [TCG_COND_LT] = 0, 796 [TCG_COND_LTU] = 0, 797 [TCG_COND_GE] = MIPS_CMP_INV, 798 [TCG_COND_GEU] = MIPS_CMP_INV, 799 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 800 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 801 [TCG_COND_GT] = MIPS_CMP_SWAP, 802 [TCG_COND_GTU] = MIPS_CMP_SWAP, 803}; 804 805static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 806 TCGReg arg1, TCGReg arg2) 807{ 808 MIPSInsn s_opc = OPC_SLTU; 809 int cmp_map; 810 811 switch (cond) { 812 case TCG_COND_EQ: 813 if (arg2 != 0) { 814 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 815 arg1 = ret; 816 } 817 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 818 break; 819 820 case TCG_COND_NE: 821 if (arg2 != 0) { 822 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 823 arg1 = ret; 824 } 825 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 826 break; 827 828 case TCG_COND_LT: 829 case TCG_COND_GE: 830 case TCG_COND_LE: 831 case TCG_COND_GT: 832 s_opc = OPC_SLT; 833 /* FALLTHRU */ 834 835 case TCG_COND_LTU: 836 case TCG_COND_GEU: 837 case TCG_COND_LEU: 838 case TCG_COND_GTU: 839 cmp_map = mips_cmp_map[cond]; 840 if (cmp_map & MIPS_CMP_SWAP) { 841 TCGReg t = arg1; 842 arg1 = arg2; 843 arg2 = t; 844 } 845 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 846 if (cmp_map & MIPS_CMP_INV) { 847 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 848 } 849 break; 850 851 default: 852 tcg_abort(); 853 break; 854 } 855} 856 857static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 858 TCGReg arg2, TCGLabel *l) 859{ 860 static const MIPSInsn b_zero[16] = { 861 [TCG_COND_LT] = OPC_BLTZ, 862 [TCG_COND_GT] = OPC_BGTZ, 863 [TCG_COND_LE] = OPC_BLEZ, 864 [TCG_COND_GE] = OPC_BGEZ, 865 }; 866 867 MIPSInsn s_opc = OPC_SLTU; 868 MIPSInsn b_opc; 869 int cmp_map; 870 871 switch (cond) { 872 case TCG_COND_EQ: 873 b_opc = OPC_BEQ; 874 break; 875 case TCG_COND_NE: 876 b_opc = OPC_BNE; 877 break; 878 879 case TCG_COND_LT: 880 case TCG_COND_GT: 881 case TCG_COND_LE: 882 case TCG_COND_GE: 883 if (arg2 == 0) { 884 b_opc = b_zero[cond]; 885 arg2 = arg1; 886 arg1 = 0; 887 break; 888 } 889 s_opc = OPC_SLT; 890 /* FALLTHRU */ 891 892 case TCG_COND_LTU: 893 case TCG_COND_GTU: 894 case TCG_COND_LEU: 895 case TCG_COND_GEU: 896 cmp_map = mips_cmp_map[cond]; 897 if (cmp_map & MIPS_CMP_SWAP) { 898 TCGReg t = arg1; 899 arg1 = arg2; 900 arg2 = t; 901 } 902 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 903 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 904 arg1 = TCG_TMP0; 905 arg2 = TCG_REG_ZERO; 906 break; 907 908 default: 909 tcg_abort(); 910 break; 911 } 912 913 tcg_out_opc_br(s, b_opc, arg1, arg2); 914 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 915 tcg_out_nop(s); 916} 917 918static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 919 TCGReg al, TCGReg ah, 920 TCGReg bl, TCGReg bh) 921{ 922 /* Merge highpart comparison into AH. */ 923 if (bh != 0) { 924 if (ah != 0) { 925 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 926 ah = tmp0; 927 } else { 928 ah = bh; 929 } 930 } 931 /* Merge lowpart comparison into AL. */ 932 if (bl != 0) { 933 if (al != 0) { 934 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 935 al = tmp1; 936 } else { 937 al = bl; 938 } 939 } 940 /* Merge high and low part comparisons into AL. */ 941 if (ah != 0) { 942 if (al != 0) { 943 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 944 al = tmp0; 945 } else { 946 al = ah; 947 } 948 } 949 return al; 950} 951 952static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 953 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 954{ 955 TCGReg tmp0 = TCG_TMP0; 956 TCGReg tmp1 = ret; 957 958 tcg_debug_assert(ret != TCG_TMP0); 959 if (ret == ah || ret == bh) { 960 tcg_debug_assert(ret != TCG_TMP1); 961 tmp1 = TCG_TMP1; 962 } 963 964 switch (cond) { 965 case TCG_COND_EQ: 966 case TCG_COND_NE: 967 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 968 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 969 break; 970 971 default: 972 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 973 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 974 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 975 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 976 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 977 break; 978 } 979} 980 981static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 982 TCGReg bl, TCGReg bh, TCGLabel *l) 983{ 984 TCGCond b_cond = TCG_COND_NE; 985 TCGReg tmp = TCG_TMP1; 986 987 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 988 With setcond, we emit between 3 and 10 insns and only 1 branch, 989 which ought to get better branch prediction. */ 990 switch (cond) { 991 case TCG_COND_EQ: 992 case TCG_COND_NE: 993 b_cond = cond; 994 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 995 break; 996 997 default: 998 /* Minimize code size by preferring a compare not requiring INV. */ 999 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1000 cond = tcg_invert_cond(cond); 1001 b_cond = TCG_COND_EQ; 1002 } 1003 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 1004 break; 1005 } 1006 1007 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 1008} 1009 1010static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1011 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1012{ 1013 bool eqz = false; 1014 1015 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1016 if (use_mips32r6_instructions && v1 == 0) { 1017 v1 = v2; 1018 v2 = 0; 1019 cond = tcg_invert_cond(cond); 1020 } 1021 1022 switch (cond) { 1023 case TCG_COND_EQ: 1024 eqz = true; 1025 /* FALLTHRU */ 1026 case TCG_COND_NE: 1027 if (c2 != 0) { 1028 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 1029 c1 = TCG_TMP0; 1030 } 1031 break; 1032 1033 default: 1034 /* Minimize code size by preferring a compare not requiring INV. */ 1035 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1036 cond = tcg_invert_cond(cond); 1037 eqz = true; 1038 } 1039 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 1040 c1 = TCG_TMP0; 1041 break; 1042 } 1043 1044 if (use_mips32r6_instructions) { 1045 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1046 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1047 1048 if (v2 != 0) { 1049 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1050 } 1051 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1052 if (v2 != 0) { 1053 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1054 } 1055 } else { 1056 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1057 1058 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1059 1060 /* This should be guaranteed via constraints */ 1061 tcg_debug_assert(v2 == ret); 1062 } 1063} 1064 1065static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1066{ 1067 /* Note that the ABI requires the called function's address to be 1068 loaded into T9, even if a direct branch is in range. */ 1069 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1070 1071 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1072 if (tail) { 1073 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1074 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1075 } 1076 } else { 1077 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1078 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1079 } 1080 } 1081} 1082 1083static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) 1084{ 1085 tcg_out_call_int(s, arg, false); 1086 tcg_out_nop(s); 1087} 1088 1089#if defined(CONFIG_SOFTMMU) 1090#include "../tcg-ldst.c.inc" 1091 1092static void * const qemu_ld_helpers[16] = { 1093 [MO_UB] = helper_ret_ldub_mmu, 1094 [MO_SB] = helper_ret_ldsb_mmu, 1095 [MO_LEUW] = helper_le_lduw_mmu, 1096 [MO_LESW] = helper_le_ldsw_mmu, 1097 [MO_LEUL] = helper_le_ldul_mmu, 1098 [MO_LEQ] = helper_le_ldq_mmu, 1099 [MO_BEUW] = helper_be_lduw_mmu, 1100 [MO_BESW] = helper_be_ldsw_mmu, 1101 [MO_BEUL] = helper_be_ldul_mmu, 1102 [MO_BEQ] = helper_be_ldq_mmu, 1103#if TCG_TARGET_REG_BITS == 64 1104 [MO_LESL] = helper_le_ldsl_mmu, 1105 [MO_BESL] = helper_be_ldsl_mmu, 1106#endif 1107}; 1108 1109static void * const qemu_st_helpers[16] = { 1110 [MO_UB] = helper_ret_stb_mmu, 1111 [MO_LEUW] = helper_le_stw_mmu, 1112 [MO_LEUL] = helper_le_stl_mmu, 1113 [MO_LEQ] = helper_le_stq_mmu, 1114 [MO_BEUW] = helper_be_stw_mmu, 1115 [MO_BEUL] = helper_be_stl_mmu, 1116 [MO_BEQ] = helper_be_stq_mmu, 1117}; 1118 1119/* Helper routines for marshalling helper function arguments into 1120 * the correct registers and stack. 1121 * I is where we want to put this argument, and is updated and returned 1122 * for the next call. ARG is the argument itself. 1123 * 1124 * We provide routines for arguments which are: immediate, 32 bit 1125 * value in register, 16 and 8 bit values in register (which must be zero 1126 * extended before use) and 64 bit value in a lo:hi register pair. 1127 */ 1128 1129static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) 1130{ 1131 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1132 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); 1133 } else { 1134 /* For N32 and N64, the initial offset is different. But there 1135 we also have 8 argument register so we don't run out here. */ 1136 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1137 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); 1138 } 1139 return i + 1; 1140} 1141 1142static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) 1143{ 1144 TCGReg tmp = TCG_TMP0; 1145 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1146 tmp = tcg_target_call_iarg_regs[i]; 1147 } 1148 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); 1149 return tcg_out_call_iarg_reg(s, i, tmp); 1150} 1151 1152static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) 1153{ 1154 TCGReg tmp = TCG_TMP0; 1155 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1156 tmp = tcg_target_call_iarg_regs[i]; 1157 } 1158 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); 1159 return tcg_out_call_iarg_reg(s, i, tmp); 1160} 1161 1162static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) 1163{ 1164 TCGReg tmp = TCG_TMP0; 1165 if (arg == 0) { 1166 tmp = TCG_REG_ZERO; 1167 } else { 1168 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1169 tmp = tcg_target_call_iarg_regs[i]; 1170 } 1171 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); 1172 } 1173 return tcg_out_call_iarg_reg(s, i, tmp); 1174} 1175 1176static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) 1177{ 1178 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1179 i = (i + 1) & ~1; 1180 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); 1181 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); 1182 return i; 1183} 1184 1185/* We expect to use a 16-bit negative offset from ENV. */ 1186QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1187QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 1188 1189/* 1190 * Perform the tlb comparison operation. 1191 * The complete host address is placed in BASE. 1192 * Clobbers TMP0, TMP1, TMP2, TMP3. 1193 */ 1194static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, 1195 TCGReg addrh, TCGMemOpIdx oi, 1196 tcg_insn_unit *label_ptr[2], bool is_load) 1197{ 1198 MemOp opc = get_memop(oi); 1199 unsigned s_bits = opc & MO_SIZE; 1200 unsigned a_bits = get_alignment_bits(opc); 1201 int mem_index = get_mmuidx(oi); 1202 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1203 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1204 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1205 int add_off = offsetof(CPUTLBEntry, addend); 1206 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) 1207 : offsetof(CPUTLBEntry, addr_write)); 1208 target_ulong mask; 1209 1210 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1211 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1212 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1213 1214 /* Extract the TLB index from the address into TMP3. */ 1215 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, 1216 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 1217 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1218 1219 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ 1220 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1221 1222 /* We don't currently support unaligned accesses. 1223 We could do so with mips32r6. */ 1224 if (a_bits < s_bits) { 1225 a_bits = s_bits; 1226 } 1227 1228 /* Mask the page bits, keeping the alignment bits to compare against. */ 1229 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); 1230 1231 /* Load the (low-half) tlb comparator. */ 1232 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1233 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); 1234 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); 1235 } else { 1236 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD 1237 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), 1238 TCG_TMP0, TCG_TMP3, cmp_off); 1239 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); 1240 /* No second compare is required here; 1241 load the tlb addend for the fast path. */ 1242 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1243 } 1244 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); 1245 1246 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1247 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1248 tcg_out_ext32u(s, base, addrl); 1249 addrl = base; 1250 } 1251 1252 label_ptr[0] = s->code_ptr; 1253 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1254 1255 /* Load and test the high half tlb comparator. */ 1256 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1257 /* delay slot */ 1258 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1259 1260 /* Load the tlb addend for the fast path. */ 1261 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1262 1263 label_ptr[1] = s->code_ptr; 1264 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); 1265 } 1266 1267 /* delay slot */ 1268 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); 1269} 1270 1271static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, 1272 TCGType ext, 1273 TCGReg datalo, TCGReg datahi, 1274 TCGReg addrlo, TCGReg addrhi, 1275 void *raddr, tcg_insn_unit *label_ptr[2]) 1276{ 1277 TCGLabelQemuLdst *label = new_ldst_label(s); 1278 1279 label->is_ld = is_ld; 1280 label->oi = oi; 1281 label->type = ext; 1282 label->datalo_reg = datalo; 1283 label->datahi_reg = datahi; 1284 label->addrlo_reg = addrlo; 1285 label->addrhi_reg = addrhi; 1286 label->raddr = tcg_splitwx_to_rx(raddr); 1287 label->label_ptr[0] = label_ptr[0]; 1288 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1289 label->label_ptr[1] = label_ptr[1]; 1290 } 1291} 1292 1293static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1294{ 1295 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1296 TCGMemOpIdx oi = l->oi; 1297 MemOp opc = get_memop(oi); 1298 TCGReg v0; 1299 int i; 1300 1301 /* resolve label address */ 1302 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1303 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1304 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1305 return false; 1306 } 1307 1308 i = 1; 1309 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1310 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1311 } else { 1312 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1313 } 1314 i = tcg_out_call_iarg_imm(s, i, oi); 1315 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); 1316 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); 1317 /* delay slot */ 1318 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1319 1320 v0 = l->datalo_reg; 1321 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 1322 /* We eliminated V0 from the possible output registers, so it 1323 cannot be clobbered here. So we must move V1 first. */ 1324 if (MIPS_BE) { 1325 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); 1326 v0 = l->datahi_reg; 1327 } else { 1328 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); 1329 } 1330 } 1331 1332 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1333 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1334 return false; 1335 } 1336 1337 /* delay slot */ 1338 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { 1339 /* we always sign-extend 32-bit loads */ 1340 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); 1341 } else { 1342 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); 1343 } 1344 return true; 1345} 1346 1347static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1348{ 1349 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1350 TCGMemOpIdx oi = l->oi; 1351 MemOp opc = get_memop(oi); 1352 MemOp s_bits = opc & MO_SIZE; 1353 int i; 1354 1355 /* resolve label address */ 1356 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1357 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1358 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1359 return false; 1360 } 1361 1362 i = 1; 1363 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1364 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1365 } else { 1366 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1367 } 1368 switch (s_bits) { 1369 case MO_8: 1370 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); 1371 break; 1372 case MO_16: 1373 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); 1374 break; 1375 case MO_32: 1376 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1377 break; 1378 case MO_64: 1379 if (TCG_TARGET_REG_BITS == 32) { 1380 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); 1381 } else { 1382 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1383 } 1384 break; 1385 default: 1386 tcg_abort(); 1387 } 1388 i = tcg_out_call_iarg_imm(s, i, oi); 1389 1390 /* Tail call to the store helper. Thus force the return address 1391 computation to take place in the return address register. */ 1392 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); 1393 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); 1394 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); 1395 /* delay slot */ 1396 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1397 return true; 1398} 1399#endif 1400 1401static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1402 TCGReg base, MemOp opc, bool is_64) 1403{ 1404 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1405 case MO_UB: 1406 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1407 break; 1408 case MO_SB: 1409 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1410 break; 1411 case MO_UW | MO_BSWAP: 1412 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1413 tcg_out_bswap16(s, lo, TCG_TMP1); 1414 break; 1415 case MO_UW: 1416 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1417 break; 1418 case MO_SW | MO_BSWAP: 1419 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1420 tcg_out_bswap16s(s, lo, TCG_TMP1); 1421 break; 1422 case MO_SW: 1423 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1424 break; 1425 case MO_UL | MO_BSWAP: 1426 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1427 if (use_mips32r2_instructions) { 1428 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1429 tcg_out_bswap32u(s, lo, lo); 1430 } else { 1431 tcg_out_bswap_subr(s, bswap32u_addr); 1432 /* delay slot */ 1433 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); 1434 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1435 } 1436 break; 1437 } 1438 /* FALLTHRU */ 1439 case MO_SL | MO_BSWAP: 1440 if (use_mips32r2_instructions) { 1441 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1442 tcg_out_bswap32(s, lo, lo); 1443 } else { 1444 tcg_out_bswap_subr(s, bswap32_addr); 1445 /* delay slot */ 1446 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1447 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); 1448 } 1449 break; 1450 case MO_UL: 1451 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1452 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1453 break; 1454 } 1455 /* FALLTHRU */ 1456 case MO_SL: 1457 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1458 break; 1459 case MO_Q | MO_BSWAP: 1460 if (TCG_TARGET_REG_BITS == 64) { 1461 if (use_mips32r2_instructions) { 1462 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1463 tcg_out_bswap64(s, lo, lo); 1464 } else { 1465 tcg_out_bswap_subr(s, bswap64_addr); 1466 /* delay slot */ 1467 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); 1468 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1469 } 1470 } else if (use_mips32r2_instructions) { 1471 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1472 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); 1473 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); 1474 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); 1475 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); 1476 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); 1477 } else { 1478 tcg_out_bswap_subr(s, bswap32_addr); 1479 /* delay slot */ 1480 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1481 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); 1482 tcg_out_bswap_subr(s, bswap32_addr); 1483 /* delay slot */ 1484 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); 1485 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); 1486 } 1487 break; 1488 case MO_Q: 1489 /* Prefer to load from offset 0 first, but allow for overlap. */ 1490 if (TCG_TARGET_REG_BITS == 64) { 1491 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1492 } else if (MIPS_BE ? hi != base : lo == base) { 1493 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1494 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1495 } else { 1496 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1497 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1498 } 1499 break; 1500 default: 1501 tcg_abort(); 1502 } 1503} 1504 1505static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) 1506{ 1507 TCGReg addr_regl, addr_regh __attribute__((unused)); 1508 TCGReg data_regl, data_regh; 1509 TCGMemOpIdx oi; 1510 MemOp opc; 1511#if defined(CONFIG_SOFTMMU) 1512 tcg_insn_unit *label_ptr[2]; 1513#endif 1514 TCGReg base = TCG_REG_A0; 1515 1516 data_regl = *args++; 1517 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1518 addr_regl = *args++; 1519 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1520 oi = *args++; 1521 opc = get_memop(oi); 1522 1523#if defined(CONFIG_SOFTMMU) 1524 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); 1525 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1526 add_qemu_ldst_label(s, 1, oi, 1527 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1528 data_regl, data_regh, addr_regl, addr_regh, 1529 s->code_ptr, label_ptr); 1530#else 1531 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1532 tcg_out_ext32u(s, base, addr_regl); 1533 addr_regl = base; 1534 } 1535 if (guest_base == 0 && data_regl != addr_regl) { 1536 base = addr_regl; 1537 } else if (guest_base == (int16_t)guest_base) { 1538 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1539 } else { 1540 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1541 } 1542 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1543#endif 1544} 1545 1546static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1547 TCGReg base, MemOp opc) 1548{ 1549 /* Don't clutter the code below with checks to avoid bswapping ZERO. */ 1550 if ((lo | hi) == 0) { 1551 opc &= ~MO_BSWAP; 1552 } 1553 1554 switch (opc & (MO_SIZE | MO_BSWAP)) { 1555 case MO_8: 1556 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1557 break; 1558 1559 case MO_16 | MO_BSWAP: 1560 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff); 1561 tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1); 1562 lo = TCG_TMP1; 1563 /* FALLTHRU */ 1564 case MO_16: 1565 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1566 break; 1567 1568 case MO_32 | MO_BSWAP: 1569 tcg_out_bswap32(s, TCG_TMP3, lo); 1570 lo = TCG_TMP3; 1571 /* FALLTHRU */ 1572 case MO_32: 1573 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1574 break; 1575 1576 case MO_64 | MO_BSWAP: 1577 if (TCG_TARGET_REG_BITS == 64) { 1578 tcg_out_bswap64(s, TCG_TMP3, lo); 1579 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); 1580 } else if (use_mips32r2_instructions) { 1581 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); 1582 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); 1583 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); 1584 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); 1585 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); 1586 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); 1587 } else { 1588 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi); 1589 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); 1590 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo); 1591 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); 1592 } 1593 break; 1594 case MO_64: 1595 if (TCG_TARGET_REG_BITS == 64) { 1596 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1597 } else { 1598 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); 1599 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); 1600 } 1601 break; 1602 1603 default: 1604 tcg_abort(); 1605 } 1606} 1607 1608static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) 1609{ 1610 TCGReg addr_regl, addr_regh __attribute__((unused)); 1611 TCGReg data_regl, data_regh; 1612 TCGMemOpIdx oi; 1613 MemOp opc; 1614#if defined(CONFIG_SOFTMMU) 1615 tcg_insn_unit *label_ptr[2]; 1616#endif 1617 TCGReg base = TCG_REG_A0; 1618 1619 data_regl = *args++; 1620 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1621 addr_regl = *args++; 1622 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1623 oi = *args++; 1624 opc = get_memop(oi); 1625 1626#if defined(CONFIG_SOFTMMU) 1627 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); 1628 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1629 add_qemu_ldst_label(s, 0, oi, 1630 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1631 data_regl, data_regh, addr_regl, addr_regh, 1632 s->code_ptr, label_ptr); 1633#else 1634 base = TCG_REG_A0; 1635 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1636 tcg_out_ext32u(s, base, addr_regl); 1637 addr_regl = base; 1638 } 1639 if (guest_base == 0) { 1640 base = addr_regl; 1641 } else if (guest_base == (int16_t)guest_base) { 1642 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1643 } else { 1644 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1645 } 1646 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1647#endif 1648} 1649 1650static void tcg_out_mb(TCGContext *s, TCGArg a0) 1651{ 1652 static const MIPSInsn sync[] = { 1653 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1654 as the former is an ordering barrier and the latter 1655 is a completion barrier. */ 1656 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1657 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1658 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1659 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1660 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1661 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1662 }; 1663 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1664} 1665 1666static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1667 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1668{ 1669 if (use_mips32r6_instructions) { 1670 if (a2 == width) { 1671 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1672 } else { 1673 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1674 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1675 } 1676 } else { 1677 if (a2 == width) { 1678 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1679 } else if (a0 == a2) { 1680 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1681 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1682 } else if (a0 != a1) { 1683 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1684 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1685 } else { 1686 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1687 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1688 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1689 } 1690 } 1691} 1692 1693static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 1694 const TCGArg *args, const int *const_args) 1695{ 1696 MIPSInsn i1, i2; 1697 TCGArg a0, a1, a2; 1698 int c2; 1699 1700 a0 = args[0]; 1701 a1 = args[1]; 1702 a2 = args[2]; 1703 c2 = const_args[2]; 1704 1705 switch (opc) { 1706 case INDEX_op_exit_tb: 1707 { 1708 TCGReg b0 = TCG_REG_ZERO; 1709 1710 a0 = (intptr_t)a0; 1711 if (a0 & ~0xffff) { 1712 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); 1713 b0 = TCG_REG_V0; 1714 } 1715 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1716 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, 1717 (uintptr_t)tb_ret_addr); 1718 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1719 } 1720 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); 1721 } 1722 break; 1723 case INDEX_op_goto_tb: 1724 if (s->tb_jmp_insn_offset) { 1725 /* direct jump method */ 1726 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); 1727 /* Avoid clobbering the address during retranslation. */ 1728 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); 1729 } else { 1730 /* indirect jump method */ 1731 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, 1732 (uintptr_t)(s->tb_jmp_target_addr + a0)); 1733 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1734 } 1735 tcg_out_nop(s); 1736 set_jmp_reset_offset(s, a0); 1737 break; 1738 case INDEX_op_goto_ptr: 1739 /* jmp to the given host address (could be epilogue) */ 1740 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1741 tcg_out_nop(s); 1742 break; 1743 case INDEX_op_br: 1744 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1745 arg_label(a0)); 1746 break; 1747 1748 case INDEX_op_ld8u_i32: 1749 case INDEX_op_ld8u_i64: 1750 i1 = OPC_LBU; 1751 goto do_ldst; 1752 case INDEX_op_ld8s_i32: 1753 case INDEX_op_ld8s_i64: 1754 i1 = OPC_LB; 1755 goto do_ldst; 1756 case INDEX_op_ld16u_i32: 1757 case INDEX_op_ld16u_i64: 1758 i1 = OPC_LHU; 1759 goto do_ldst; 1760 case INDEX_op_ld16s_i32: 1761 case INDEX_op_ld16s_i64: 1762 i1 = OPC_LH; 1763 goto do_ldst; 1764 case INDEX_op_ld_i32: 1765 case INDEX_op_ld32s_i64: 1766 i1 = OPC_LW; 1767 goto do_ldst; 1768 case INDEX_op_ld32u_i64: 1769 i1 = OPC_LWU; 1770 goto do_ldst; 1771 case INDEX_op_ld_i64: 1772 i1 = OPC_LD; 1773 goto do_ldst; 1774 case INDEX_op_st8_i32: 1775 case INDEX_op_st8_i64: 1776 i1 = OPC_SB; 1777 goto do_ldst; 1778 case INDEX_op_st16_i32: 1779 case INDEX_op_st16_i64: 1780 i1 = OPC_SH; 1781 goto do_ldst; 1782 case INDEX_op_st_i32: 1783 case INDEX_op_st32_i64: 1784 i1 = OPC_SW; 1785 goto do_ldst; 1786 case INDEX_op_st_i64: 1787 i1 = OPC_SD; 1788 do_ldst: 1789 tcg_out_ldst(s, i1, a0, a1, a2); 1790 break; 1791 1792 case INDEX_op_add_i32: 1793 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1794 goto do_binary; 1795 case INDEX_op_add_i64: 1796 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1797 goto do_binary; 1798 case INDEX_op_or_i32: 1799 case INDEX_op_or_i64: 1800 i1 = OPC_OR, i2 = OPC_ORI; 1801 goto do_binary; 1802 case INDEX_op_xor_i32: 1803 case INDEX_op_xor_i64: 1804 i1 = OPC_XOR, i2 = OPC_XORI; 1805 do_binary: 1806 if (c2) { 1807 tcg_out_opc_imm(s, i2, a0, a1, a2); 1808 break; 1809 } 1810 do_binaryv: 1811 tcg_out_opc_reg(s, i1, a0, a1, a2); 1812 break; 1813 1814 case INDEX_op_sub_i32: 1815 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1816 goto do_subtract; 1817 case INDEX_op_sub_i64: 1818 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1819 do_subtract: 1820 if (c2) { 1821 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1822 break; 1823 } 1824 goto do_binaryv; 1825 case INDEX_op_and_i32: 1826 if (c2 && a2 != (uint16_t)a2) { 1827 int msb = ctz32(~a2) - 1; 1828 tcg_debug_assert(use_mips32r2_instructions); 1829 tcg_debug_assert(is_p2m1(a2)); 1830 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1831 break; 1832 } 1833 i1 = OPC_AND, i2 = OPC_ANDI; 1834 goto do_binary; 1835 case INDEX_op_and_i64: 1836 if (c2 && a2 != (uint16_t)a2) { 1837 int msb = ctz64(~a2) - 1; 1838 tcg_debug_assert(use_mips32r2_instructions); 1839 tcg_debug_assert(is_p2m1(a2)); 1840 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1841 break; 1842 } 1843 i1 = OPC_AND, i2 = OPC_ANDI; 1844 goto do_binary; 1845 case INDEX_op_nor_i32: 1846 case INDEX_op_nor_i64: 1847 i1 = OPC_NOR; 1848 goto do_binaryv; 1849 1850 case INDEX_op_mul_i32: 1851 if (use_mips32_instructions) { 1852 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1853 break; 1854 } 1855 i1 = OPC_MULT, i2 = OPC_MFLO; 1856 goto do_hilo1; 1857 case INDEX_op_mulsh_i32: 1858 if (use_mips32r6_instructions) { 1859 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1860 break; 1861 } 1862 i1 = OPC_MULT, i2 = OPC_MFHI; 1863 goto do_hilo1; 1864 case INDEX_op_muluh_i32: 1865 if (use_mips32r6_instructions) { 1866 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1867 break; 1868 } 1869 i1 = OPC_MULTU, i2 = OPC_MFHI; 1870 goto do_hilo1; 1871 case INDEX_op_div_i32: 1872 if (use_mips32r6_instructions) { 1873 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1874 break; 1875 } 1876 i1 = OPC_DIV, i2 = OPC_MFLO; 1877 goto do_hilo1; 1878 case INDEX_op_divu_i32: 1879 if (use_mips32r6_instructions) { 1880 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1881 break; 1882 } 1883 i1 = OPC_DIVU, i2 = OPC_MFLO; 1884 goto do_hilo1; 1885 case INDEX_op_rem_i32: 1886 if (use_mips32r6_instructions) { 1887 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1888 break; 1889 } 1890 i1 = OPC_DIV, i2 = OPC_MFHI; 1891 goto do_hilo1; 1892 case INDEX_op_remu_i32: 1893 if (use_mips32r6_instructions) { 1894 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1895 break; 1896 } 1897 i1 = OPC_DIVU, i2 = OPC_MFHI; 1898 goto do_hilo1; 1899 case INDEX_op_mul_i64: 1900 if (use_mips32r6_instructions) { 1901 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1902 break; 1903 } 1904 i1 = OPC_DMULT, i2 = OPC_MFLO; 1905 goto do_hilo1; 1906 case INDEX_op_mulsh_i64: 1907 if (use_mips32r6_instructions) { 1908 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1909 break; 1910 } 1911 i1 = OPC_DMULT, i2 = OPC_MFHI; 1912 goto do_hilo1; 1913 case INDEX_op_muluh_i64: 1914 if (use_mips32r6_instructions) { 1915 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1916 break; 1917 } 1918 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1919 goto do_hilo1; 1920 case INDEX_op_div_i64: 1921 if (use_mips32r6_instructions) { 1922 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1923 break; 1924 } 1925 i1 = OPC_DDIV, i2 = OPC_MFLO; 1926 goto do_hilo1; 1927 case INDEX_op_divu_i64: 1928 if (use_mips32r6_instructions) { 1929 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1930 break; 1931 } 1932 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1933 goto do_hilo1; 1934 case INDEX_op_rem_i64: 1935 if (use_mips32r6_instructions) { 1936 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1937 break; 1938 } 1939 i1 = OPC_DDIV, i2 = OPC_MFHI; 1940 goto do_hilo1; 1941 case INDEX_op_remu_i64: 1942 if (use_mips32r6_instructions) { 1943 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1944 break; 1945 } 1946 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1947 do_hilo1: 1948 tcg_out_opc_reg(s, i1, 0, a1, a2); 1949 tcg_out_opc_reg(s, i2, a0, 0, 0); 1950 break; 1951 1952 case INDEX_op_muls2_i32: 1953 i1 = OPC_MULT; 1954 goto do_hilo2; 1955 case INDEX_op_mulu2_i32: 1956 i1 = OPC_MULTU; 1957 goto do_hilo2; 1958 case INDEX_op_muls2_i64: 1959 i1 = OPC_DMULT; 1960 goto do_hilo2; 1961 case INDEX_op_mulu2_i64: 1962 i1 = OPC_DMULTU; 1963 do_hilo2: 1964 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1965 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1966 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1967 break; 1968 1969 case INDEX_op_not_i32: 1970 case INDEX_op_not_i64: 1971 i1 = OPC_NOR; 1972 goto do_unary; 1973 case INDEX_op_bswap16_i32: 1974 case INDEX_op_bswap16_i64: 1975 i1 = OPC_WSBH; 1976 goto do_unary; 1977 case INDEX_op_ext8s_i32: 1978 case INDEX_op_ext8s_i64: 1979 i1 = OPC_SEB; 1980 goto do_unary; 1981 case INDEX_op_ext16s_i32: 1982 case INDEX_op_ext16s_i64: 1983 i1 = OPC_SEH; 1984 do_unary: 1985 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1986 break; 1987 1988 case INDEX_op_bswap32_i32: 1989 tcg_out_bswap32(s, a0, a1); 1990 break; 1991 case INDEX_op_bswap32_i64: 1992 tcg_out_bswap32u(s, a0, a1); 1993 break; 1994 case INDEX_op_bswap64_i64: 1995 tcg_out_bswap64(s, a0, a1); 1996 break; 1997 case INDEX_op_extrh_i64_i32: 1998 tcg_out_dsra(s, a0, a1, 32); 1999 break; 2000 case INDEX_op_ext32s_i64: 2001 case INDEX_op_ext_i32_i64: 2002 case INDEX_op_extrl_i64_i32: 2003 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); 2004 break; 2005 case INDEX_op_ext32u_i64: 2006 case INDEX_op_extu_i32_i64: 2007 tcg_out_ext32u(s, a0, a1); 2008 break; 2009 2010 case INDEX_op_sar_i32: 2011 i1 = OPC_SRAV, i2 = OPC_SRA; 2012 goto do_shift; 2013 case INDEX_op_shl_i32: 2014 i1 = OPC_SLLV, i2 = OPC_SLL; 2015 goto do_shift; 2016 case INDEX_op_shr_i32: 2017 i1 = OPC_SRLV, i2 = OPC_SRL; 2018 goto do_shift; 2019 case INDEX_op_rotr_i32: 2020 i1 = OPC_ROTRV, i2 = OPC_ROTR; 2021 do_shift: 2022 if (c2) { 2023 tcg_out_opc_sa(s, i2, a0, a1, a2); 2024 break; 2025 } 2026 do_shiftv: 2027 tcg_out_opc_reg(s, i1, a0, a2, a1); 2028 break; 2029 case INDEX_op_rotl_i32: 2030 if (c2) { 2031 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 2032 } else { 2033 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2034 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 2035 } 2036 break; 2037 case INDEX_op_sar_i64: 2038 if (c2) { 2039 tcg_out_dsra(s, a0, a1, a2); 2040 break; 2041 } 2042 i1 = OPC_DSRAV; 2043 goto do_shiftv; 2044 case INDEX_op_shl_i64: 2045 if (c2) { 2046 tcg_out_dsll(s, a0, a1, a2); 2047 break; 2048 } 2049 i1 = OPC_DSLLV; 2050 goto do_shiftv; 2051 case INDEX_op_shr_i64: 2052 if (c2) { 2053 tcg_out_dsrl(s, a0, a1, a2); 2054 break; 2055 } 2056 i1 = OPC_DSRLV; 2057 goto do_shiftv; 2058 case INDEX_op_rotr_i64: 2059 if (c2) { 2060 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2061 break; 2062 } 2063 i1 = OPC_DROTRV; 2064 goto do_shiftv; 2065 case INDEX_op_rotl_i64: 2066 if (c2) { 2067 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2068 } else { 2069 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2070 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2071 } 2072 break; 2073 2074 case INDEX_op_clz_i32: 2075 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2076 break; 2077 case INDEX_op_clz_i64: 2078 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2079 break; 2080 2081 case INDEX_op_deposit_i32: 2082 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2083 break; 2084 case INDEX_op_deposit_i64: 2085 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2086 args[3] + args[4] - 1, args[3]); 2087 break; 2088 case INDEX_op_extract_i32: 2089 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2090 break; 2091 case INDEX_op_extract_i64: 2092 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2093 args[3] - 1, a2); 2094 break; 2095 2096 case INDEX_op_brcond_i32: 2097 case INDEX_op_brcond_i64: 2098 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2099 break; 2100 case INDEX_op_brcond2_i32: 2101 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2102 break; 2103 2104 case INDEX_op_movcond_i32: 2105 case INDEX_op_movcond_i64: 2106 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2107 break; 2108 2109 case INDEX_op_setcond_i32: 2110 case INDEX_op_setcond_i64: 2111 tcg_out_setcond(s, args[3], a0, a1, a2); 2112 break; 2113 case INDEX_op_setcond2_i32: 2114 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2115 break; 2116 2117 case INDEX_op_qemu_ld_i32: 2118 tcg_out_qemu_ld(s, args, false); 2119 break; 2120 case INDEX_op_qemu_ld_i64: 2121 tcg_out_qemu_ld(s, args, true); 2122 break; 2123 case INDEX_op_qemu_st_i32: 2124 tcg_out_qemu_st(s, args, false); 2125 break; 2126 case INDEX_op_qemu_st_i64: 2127 tcg_out_qemu_st(s, args, true); 2128 break; 2129 2130 case INDEX_op_add2_i32: 2131 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2132 const_args[4], const_args[5], false); 2133 break; 2134 case INDEX_op_sub2_i32: 2135 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2136 const_args[4], const_args[5], true); 2137 break; 2138 2139 case INDEX_op_mb: 2140 tcg_out_mb(s, a0); 2141 break; 2142 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2143 case INDEX_op_mov_i64: 2144 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2145 default: 2146 tcg_abort(); 2147 } 2148} 2149 2150static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) 2151{ 2152 static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; 2153 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; 2154 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; 2155 static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; 2156 static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } }; 2157 static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } }; 2158 static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; 2159 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; 2160 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; 2161 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; 2162 static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } }; 2163 static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } }; 2164 static const TCGTargetOpDef SZ_SZ_S 2165 = { .args_ct_str = { "SZ", "SZ", "S" } }; 2166 static const TCGTargetOpDef SZ_SZ_S_S 2167 = { .args_ct_str = { "SZ", "SZ", "S", "S" } }; 2168 static const TCGTargetOpDef r_rZ_rN 2169 = { .args_ct_str = { "r", "rZ", "rN" } }; 2170 static const TCGTargetOpDef r_rZ_rZ 2171 = { .args_ct_str = { "r", "rZ", "rZ" } }; 2172 static const TCGTargetOpDef r_r_rIK 2173 = { .args_ct_str = { "r", "r", "rIK" } }; 2174 static const TCGTargetOpDef r_r_rWZ 2175 = { .args_ct_str = { "r", "r", "rWZ" } }; 2176 static const TCGTargetOpDef r_r_r_r 2177 = { .args_ct_str = { "r", "r", "r", "r" } }; 2178 static const TCGTargetOpDef r_r_L_L 2179 = { .args_ct_str = { "r", "r", "L", "L" } }; 2180 static const TCGTargetOpDef dep 2181 = { .args_ct_str = { "r", "0", "rZ" } }; 2182 static const TCGTargetOpDef movc 2183 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } }; 2184 static const TCGTargetOpDef movc_r6 2185 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; 2186 static const TCGTargetOpDef add2 2187 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } }; 2188 static const TCGTargetOpDef br2 2189 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; 2190 static const TCGTargetOpDef setc2 2191 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; 2192 2193 switch (op) { 2194 case INDEX_op_goto_ptr: 2195 return &r; 2196 2197 case INDEX_op_ld8u_i32: 2198 case INDEX_op_ld8s_i32: 2199 case INDEX_op_ld16u_i32: 2200 case INDEX_op_ld16s_i32: 2201 case INDEX_op_ld_i32: 2202 case INDEX_op_not_i32: 2203 case INDEX_op_bswap16_i32: 2204 case INDEX_op_bswap32_i32: 2205 case INDEX_op_ext8s_i32: 2206 case INDEX_op_ext16s_i32: 2207 case INDEX_op_extract_i32: 2208 case INDEX_op_ld8u_i64: 2209 case INDEX_op_ld8s_i64: 2210 case INDEX_op_ld16u_i64: 2211 case INDEX_op_ld16s_i64: 2212 case INDEX_op_ld32s_i64: 2213 case INDEX_op_ld32u_i64: 2214 case INDEX_op_ld_i64: 2215 case INDEX_op_not_i64: 2216 case INDEX_op_bswap16_i64: 2217 case INDEX_op_bswap32_i64: 2218 case INDEX_op_bswap64_i64: 2219 case INDEX_op_ext8s_i64: 2220 case INDEX_op_ext16s_i64: 2221 case INDEX_op_ext32s_i64: 2222 case INDEX_op_ext32u_i64: 2223 case INDEX_op_ext_i32_i64: 2224 case INDEX_op_extu_i32_i64: 2225 case INDEX_op_extrl_i64_i32: 2226 case INDEX_op_extrh_i64_i32: 2227 case INDEX_op_extract_i64: 2228 return &r_r; 2229 2230 case INDEX_op_st8_i32: 2231 case INDEX_op_st16_i32: 2232 case INDEX_op_st_i32: 2233 case INDEX_op_st8_i64: 2234 case INDEX_op_st16_i64: 2235 case INDEX_op_st32_i64: 2236 case INDEX_op_st_i64: 2237 return &rZ_r; 2238 2239 case INDEX_op_add_i32: 2240 case INDEX_op_add_i64: 2241 return &r_r_rJ; 2242 case INDEX_op_sub_i32: 2243 case INDEX_op_sub_i64: 2244 return &r_rZ_rN; 2245 case INDEX_op_mul_i32: 2246 case INDEX_op_mulsh_i32: 2247 case INDEX_op_muluh_i32: 2248 case INDEX_op_div_i32: 2249 case INDEX_op_divu_i32: 2250 case INDEX_op_rem_i32: 2251 case INDEX_op_remu_i32: 2252 case INDEX_op_nor_i32: 2253 case INDEX_op_setcond_i32: 2254 case INDEX_op_mul_i64: 2255 case INDEX_op_mulsh_i64: 2256 case INDEX_op_muluh_i64: 2257 case INDEX_op_div_i64: 2258 case INDEX_op_divu_i64: 2259 case INDEX_op_rem_i64: 2260 case INDEX_op_remu_i64: 2261 case INDEX_op_nor_i64: 2262 case INDEX_op_setcond_i64: 2263 return &r_rZ_rZ; 2264 case INDEX_op_muls2_i32: 2265 case INDEX_op_mulu2_i32: 2266 case INDEX_op_muls2_i64: 2267 case INDEX_op_mulu2_i64: 2268 return &r_r_r_r; 2269 case INDEX_op_and_i32: 2270 case INDEX_op_and_i64: 2271 return &r_r_rIK; 2272 case INDEX_op_or_i32: 2273 case INDEX_op_xor_i32: 2274 case INDEX_op_or_i64: 2275 case INDEX_op_xor_i64: 2276 return &r_r_rI; 2277 case INDEX_op_shl_i32: 2278 case INDEX_op_shr_i32: 2279 case INDEX_op_sar_i32: 2280 case INDEX_op_rotr_i32: 2281 case INDEX_op_rotl_i32: 2282 case INDEX_op_shl_i64: 2283 case INDEX_op_shr_i64: 2284 case INDEX_op_sar_i64: 2285 case INDEX_op_rotr_i64: 2286 case INDEX_op_rotl_i64: 2287 return &r_r_ri; 2288 case INDEX_op_clz_i32: 2289 case INDEX_op_clz_i64: 2290 return &r_r_rWZ; 2291 2292 case INDEX_op_deposit_i32: 2293 case INDEX_op_deposit_i64: 2294 return &dep; 2295 case INDEX_op_brcond_i32: 2296 case INDEX_op_brcond_i64: 2297 return &rZ_rZ; 2298 case INDEX_op_movcond_i32: 2299 case INDEX_op_movcond_i64: 2300 return use_mips32r6_instructions ? &movc_r6 : &movc; 2301 2302 case INDEX_op_add2_i32: 2303 case INDEX_op_sub2_i32: 2304 return &add2; 2305 case INDEX_op_setcond2_i32: 2306 return &setc2; 2307 case INDEX_op_brcond2_i32: 2308 return &br2; 2309 2310 case INDEX_op_qemu_ld_i32: 2311 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2312 ? &r_L : &r_L_L); 2313 case INDEX_op_qemu_st_i32: 2314 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2315 ? &SZ_S : &SZ_S_S); 2316 case INDEX_op_qemu_ld_i64: 2317 return (TCG_TARGET_REG_BITS == 64 ? &r_L 2318 : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L); 2319 case INDEX_op_qemu_st_i64: 2320 return (TCG_TARGET_REG_BITS == 64 ? &SZ_S 2321 : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S); 2322 2323 default: 2324 return NULL; 2325 } 2326} 2327 2328static const int tcg_target_callee_save_regs[] = { 2329 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2330 TCG_REG_S1, 2331 TCG_REG_S2, 2332 TCG_REG_S3, 2333 TCG_REG_S4, 2334 TCG_REG_S5, 2335 TCG_REG_S6, 2336 TCG_REG_S7, 2337 TCG_REG_S8, 2338 TCG_REG_RA, /* should be last for ABI compliance */ 2339}; 2340 2341/* The Linux kernel doesn't provide any information about the available 2342 instruction set. Probe it using a signal handler. */ 2343 2344 2345#ifndef use_movnz_instructions 2346bool use_movnz_instructions = false; 2347#endif 2348 2349#ifndef use_mips32_instructions 2350bool use_mips32_instructions = false; 2351#endif 2352 2353#ifndef use_mips32r2_instructions 2354bool use_mips32r2_instructions = false; 2355#endif 2356 2357static volatile sig_atomic_t got_sigill; 2358 2359static void sigill_handler(int signo, siginfo_t *si, void *data) 2360{ 2361 /* Skip the faulty instruction */ 2362 ucontext_t *uc = (ucontext_t *)data; 2363 uc->uc_mcontext.pc += 4; 2364 2365 got_sigill = 1; 2366} 2367 2368static void tcg_target_detect_isa(void) 2369{ 2370 struct sigaction sa_old, sa_new; 2371 2372 memset(&sa_new, 0, sizeof(sa_new)); 2373 sa_new.sa_flags = SA_SIGINFO; 2374 sa_new.sa_sigaction = sigill_handler; 2375 sigaction(SIGILL, &sa_new, &sa_old); 2376 2377 /* Probe for movn/movz, necessary to implement movcond. */ 2378#ifndef use_movnz_instructions 2379 got_sigill = 0; 2380 asm volatile(".set push\n" 2381 ".set mips32\n" 2382 "movn $zero, $zero, $zero\n" 2383 "movz $zero, $zero, $zero\n" 2384 ".set pop\n" 2385 : : : ); 2386 use_movnz_instructions = !got_sigill; 2387#endif 2388 2389 /* Probe for MIPS32 instructions. As no subsetting is allowed 2390 by the specification, it is only necessary to probe for one 2391 of the instructions. */ 2392#ifndef use_mips32_instructions 2393 got_sigill = 0; 2394 asm volatile(".set push\n" 2395 ".set mips32\n" 2396 "mul $zero, $zero\n" 2397 ".set pop\n" 2398 : : : ); 2399 use_mips32_instructions = !got_sigill; 2400#endif 2401 2402 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2403 available. As no subsetting is allowed by the specification, 2404 it is only necessary to probe for one of the instructions. */ 2405#ifndef use_mips32r2_instructions 2406 if (use_mips32_instructions) { 2407 got_sigill = 0; 2408 asm volatile(".set push\n" 2409 ".set mips32r2\n" 2410 "seb $zero, $zero\n" 2411 ".set pop\n" 2412 : : : ); 2413 use_mips32r2_instructions = !got_sigill; 2414 } 2415#endif 2416 2417 sigaction(SIGILL, &sa_old, NULL); 2418} 2419 2420static tcg_insn_unit *align_code_ptr(TCGContext *s) 2421{ 2422 uintptr_t p = (uintptr_t)s->code_ptr; 2423 if (p & 15) { 2424 p = (p + 15) & -16; 2425 s->code_ptr = (void *)p; 2426 } 2427 return s->code_ptr; 2428} 2429 2430/* Stack frame parameters. */ 2431#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2432#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2433#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2434 2435#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2436 + TCG_TARGET_STACK_ALIGN - 1) \ 2437 & -TCG_TARGET_STACK_ALIGN) 2438#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2439 2440/* We're expecting to be able to use an immediate for frame allocation. */ 2441QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2442 2443/* Generate global QEMU prologue and epilogue code */ 2444static void tcg_target_qemu_prologue(TCGContext *s) 2445{ 2446 int i; 2447 2448 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2449 2450 /* TB prologue */ 2451 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2452 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2453 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2454 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2455 } 2456 2457#ifndef CONFIG_SOFTMMU 2458 if (guest_base) { 2459 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2460 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2461 } 2462#endif 2463 2464 /* Call generated code */ 2465 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2466 /* delay slot */ 2467 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2468 2469 /* 2470 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2471 * and fall through to the rest of the epilogue. 2472 */ 2473 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2474 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2475 2476 /* TB epilogue */ 2477 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2478 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2479 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2480 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2481 } 2482 2483 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2484 /* delay slot */ 2485 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2486 2487 if (use_mips32r2_instructions) { 2488 return; 2489 } 2490 2491 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2492 clobbers TCG_TMP1, TCG_TMP2. */ 2493 2494 /* 2495 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2496 */ 2497 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2498 /* t3 = (ssss)d000 */ 2499 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2500 /* t1 = 000a */ 2501 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2502 /* t2 = 00c0 */ 2503 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2504 /* t3 = d00a */ 2505 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2506 /* t1 = 0abc */ 2507 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2508 /* t2 = 0c00 */ 2509 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2510 /* t1 = 00b0 */ 2511 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2512 /* t3 = dc0a */ 2513 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2514 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2515 /* t3 = dcba -- delay slot */ 2516 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2517 2518 if (TCG_TARGET_REG_BITS == 32) { 2519 return; 2520 } 2521 2522 /* 2523 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2524 */ 2525 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2526 /* t1 = (0000)000d */ 2527 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2528 /* t3 = 000a */ 2529 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2530 /* t1 = (0000)d000 */ 2531 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2532 /* t2 = 00c0 */ 2533 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2534 /* t3 = d00a */ 2535 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2536 /* t1 = 0abc */ 2537 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2538 /* t2 = 0c00 */ 2539 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2540 /* t1 = 00b0 */ 2541 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2542 /* t3 = dc0a */ 2543 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2544 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2545 /* t3 = dcba -- delay slot */ 2546 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2547 2548 /* 2549 * bswap64 -- 64-bit swap. a0 = abcdefgh 2550 */ 2551 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2552 /* t3 = h0000000 */ 2553 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2554 /* t1 = 0000000a */ 2555 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2556 2557 /* t2 = 000000g0 */ 2558 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2559 /* t3 = h000000a */ 2560 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2561 /* t1 = 00000abc */ 2562 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2563 /* t2 = 0g000000 */ 2564 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2565 /* t1 = 000000b0 */ 2566 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2567 2568 /* t3 = hg00000a */ 2569 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2570 /* t2 = 0000abcd */ 2571 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2572 /* t3 = hg0000ba */ 2573 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2574 2575 /* t1 = 000000c0 */ 2576 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2577 /* t2 = 0000000d */ 2578 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2579 /* t1 = 00000c00 */ 2580 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2581 /* t2 = 0000d000 */ 2582 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2583 2584 /* t3 = hg000cba */ 2585 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2586 /* t1 = 00abcdef */ 2587 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2588 /* t3 = hg00dcba */ 2589 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2590 2591 /* t2 = 0000000f */ 2592 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2593 /* t1 = 000000e0 */ 2594 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2595 /* t2 = 00f00000 */ 2596 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2597 /* t1 = 000e0000 */ 2598 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2599 2600 /* t3 = hgf0dcba */ 2601 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2602 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2603 /* t3 = hgfedcba -- delay slot */ 2604 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2605} 2606 2607static void tcg_target_init(TCGContext *s) 2608{ 2609 tcg_target_detect_isa(); 2610 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2611 if (TCG_TARGET_REG_BITS == 64) { 2612 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2613 } 2614 2615 tcg_target_call_clobber_regs = 0; 2616 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2617 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2618 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2619 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2620 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2621 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2622 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2623 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2624 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2625 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2626 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2627 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2628 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2629 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2630 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2631 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2632 2633 s->reserved_regs = 0; 2634 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2635 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2636 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2637 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2638 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2639 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2640 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2641 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2642 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2643 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2644} 2645 2646void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, 2647 uintptr_t jmp_rw, uintptr_t addr) 2648{ 2649 qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); 2650 flush_idcache_range(jmp_rx, jmp_rw, 4); 2651} 2652 2653typedef struct { 2654 DebugFrameHeader h; 2655 uint8_t fde_def_cfa[4]; 2656 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2657} DebugFrame; 2658 2659#define ELF_HOST_MACHINE EM_MIPS 2660/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2661 which is good because they're really quite complicated for MIPS. */ 2662 2663static const DebugFrame debug_frame = { 2664 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2665 .h.cie.id = -1, 2666 .h.cie.version = 1, 2667 .h.cie.code_align = 1, 2668 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2669 .h.cie.return_column = TCG_REG_RA, 2670 2671 /* Total FDE size does not include the "len" member. */ 2672 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2673 2674 .fde_def_cfa = { 2675 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2676 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2677 (FRAME_SIZE >> 7) 2678 }, 2679 .fde_reg_ofs = { 2680 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2681 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2682 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2683 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2684 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2685 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2686 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2687 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2688 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2689 } 2690}; 2691 2692void tcg_register_jit(const void *buf, size_t buf_size) 2693{ 2694 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2695} 2696