xref: /qemu/tcg/mips/tcg-target.h (revision 2f28d2ff)
1 /*
2  * Tiny Code Generator for QEMU
3  *
4  * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5  * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6  * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  */
26 #define TCG_TARGET_MIPS 1
27 
28 #ifdef __MIPSEB__
29 # define TCG_TARGET_WORDS_BIGENDIAN
30 #endif
31 
32 #define TCG_TARGET_NB_REGS 32
33 
34 typedef enum {
35     TCG_REG_ZERO = 0,
36     TCG_REG_AT,
37     TCG_REG_V0,
38     TCG_REG_V1,
39     TCG_REG_A0,
40     TCG_REG_A1,
41     TCG_REG_A2,
42     TCG_REG_A3,
43     TCG_REG_T0,
44     TCG_REG_T1,
45     TCG_REG_T2,
46     TCG_REG_T3,
47     TCG_REG_T4,
48     TCG_REG_T5,
49     TCG_REG_T6,
50     TCG_REG_T7,
51     TCG_REG_S0,
52     TCG_REG_S1,
53     TCG_REG_S2,
54     TCG_REG_S3,
55     TCG_REG_S4,
56     TCG_REG_S5,
57     TCG_REG_S6,
58     TCG_REG_S7,
59     TCG_REG_T8,
60     TCG_REG_T9,
61     TCG_REG_K0,
62     TCG_REG_K1,
63     TCG_REG_GP,
64     TCG_REG_SP,
65     TCG_REG_FP,
66     TCG_REG_RA,
67 } TCGReg;
68 
69 #define TCG_CT_CONST_ZERO 0x100
70 #define TCG_CT_CONST_U16  0x200
71 #define TCG_CT_CONST_S16  0x400
72 
73 /* used for function call generation */
74 #define TCG_REG_CALL_STACK TCG_REG_SP
75 #define TCG_TARGET_STACK_ALIGN 8
76 #define TCG_TARGET_CALL_STACK_OFFSET 16
77 #define TCG_TARGET_CALL_ALIGN_ARGS 1
78 
79 /* optional instructions */
80 #define TCG_TARGET_HAS_div_i32          1
81 #define TCG_TARGET_HAS_not_i32          1
82 #define TCG_TARGET_HAS_nor_i32          1
83 #define TCG_TARGET_HAS_rot_i32          0
84 #define TCG_TARGET_HAS_ext8s_i32        1
85 #define TCG_TARGET_HAS_ext16s_i32       1
86 #define TCG_TARGET_HAS_bswap32_i32      0
87 #define TCG_TARGET_HAS_bswap16_i32      0
88 #define TCG_TARGET_HAS_andc_i32         0
89 #define TCG_TARGET_HAS_orc_i32          0
90 #define TCG_TARGET_HAS_eqv_i32          0
91 #define TCG_TARGET_HAS_nand_i32         0
92 #define TCG_TARGET_HAS_deposit_i32      0
93 
94 /* optional instructions automatically implemented */
95 #define TCG_TARGET_HAS_neg_i32          0 /* sub  rd, zero, rt   */
96 #define TCG_TARGET_HAS_ext8u_i32        0 /* andi rt, rs, 0xff   */
97 #define TCG_TARGET_HAS_ext16u_i32       0 /* andi rt, rs, 0xffff */
98 
99 /* Note: must be synced with dyngen-exec.h */
100 #define TCG_AREG0 TCG_REG_S0
101 
102 /* guest base is supported */
103 #define TCG_TARGET_HAS_GUEST_BASE
104 
105 #ifdef __OpenBSD__
106 #include <machine/sysarch.h>
107 #else
108 #include <sys/cachectl.h>
109 #endif
110 
111 static inline void flush_icache_range(unsigned long start, unsigned long stop)
112 {
113     cacheflush ((void *)start, stop-start, ICACHE);
114 }
115