1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26#include "../tcg-pool.c.inc" 27#include "../tcg-ldst.c.inc" 28 29/* 30 * Standardize on the _CALL_FOO symbols used by GCC: 31 * Apple XCode does not define _CALL_DARWIN. 32 * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit). 33 */ 34#if !defined(_CALL_SYSV) && \ 35 !defined(_CALL_DARWIN) && \ 36 !defined(_CALL_AIX) && \ 37 !defined(_CALL_ELF) 38# if defined(__APPLE__) 39# define _CALL_DARWIN 40# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32 41# define _CALL_SYSV 42# else 43# error "Unknown ABI" 44# endif 45#endif 46 47#if TCG_TARGET_REG_BITS == 64 48# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 49# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 50#else 51# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 52# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 53#endif 54#ifdef _CALL_SYSV 55# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 56# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 57#else 58# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 59# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 60#endif 61 62/* For some memory operations, we need a scratch that isn't R0. For the AIX 63 calling convention, we can re-use the TOC register since we'll be reloading 64 it at every call. Otherwise R12 will do nicely as neither a call-saved 65 register nor a parameter register. */ 66#ifdef _CALL_AIX 67# define TCG_REG_TMP1 TCG_REG_R2 68#else 69# define TCG_REG_TMP1 TCG_REG_R12 70#endif 71#define TCG_REG_TMP2 TCG_REG_R11 72 73#define TCG_VEC_TMP1 TCG_REG_V0 74#define TCG_VEC_TMP2 TCG_REG_V1 75 76#define TCG_REG_TB TCG_REG_R31 77#define USE_REG_TB (TCG_TARGET_REG_BITS == 64) 78 79/* Shorthand for size of a pointer. Avoid promotion to unsigned. */ 80#define SZP ((int)sizeof(void *)) 81 82/* Shorthand for size of a register. */ 83#define SZR (TCG_TARGET_REG_BITS / 8) 84 85#define TCG_CT_CONST_S16 0x100 86#define TCG_CT_CONST_S32 0x400 87#define TCG_CT_CONST_U32 0x800 88#define TCG_CT_CONST_ZERO 0x1000 89#define TCG_CT_CONST_MONE 0x2000 90#define TCG_CT_CONST_WSZ 0x4000 91 92#define ALL_GENERAL_REGS 0xffffffffu 93#define ALL_VECTOR_REGS 0xffffffff00000000ull 94 95TCGPowerISA have_isa; 96static bool have_isel; 97bool have_altivec; 98bool have_vsx; 99 100#ifndef CONFIG_SOFTMMU 101#define TCG_GUEST_BASE_REG 30 102#endif 103 104#ifdef CONFIG_DEBUG_TCG 105static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = { 106 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 107 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 108 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 109 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 110 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 111 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 112 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 113 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 114}; 115#endif 116 117static const int tcg_target_reg_alloc_order[] = { 118 TCG_REG_R14, /* call saved registers */ 119 TCG_REG_R15, 120 TCG_REG_R16, 121 TCG_REG_R17, 122 TCG_REG_R18, 123 TCG_REG_R19, 124 TCG_REG_R20, 125 TCG_REG_R21, 126 TCG_REG_R22, 127 TCG_REG_R23, 128 TCG_REG_R24, 129 TCG_REG_R25, 130 TCG_REG_R26, 131 TCG_REG_R27, 132 TCG_REG_R28, 133 TCG_REG_R29, 134 TCG_REG_R30, 135 TCG_REG_R31, 136 TCG_REG_R12, /* call clobbered, non-arguments */ 137 TCG_REG_R11, 138 TCG_REG_R2, 139 TCG_REG_R13, 140 TCG_REG_R10, /* call clobbered, arguments */ 141 TCG_REG_R9, 142 TCG_REG_R8, 143 TCG_REG_R7, 144 TCG_REG_R6, 145 TCG_REG_R5, 146 TCG_REG_R4, 147 TCG_REG_R3, 148 149 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */ 150 TCG_REG_V2, /* call clobbered, vectors */ 151 TCG_REG_V3, 152 TCG_REG_V4, 153 TCG_REG_V5, 154 TCG_REG_V6, 155 TCG_REG_V7, 156 TCG_REG_V8, 157 TCG_REG_V9, 158 TCG_REG_V10, 159 TCG_REG_V11, 160 TCG_REG_V12, 161 TCG_REG_V13, 162 TCG_REG_V14, 163 TCG_REG_V15, 164 TCG_REG_V16, 165 TCG_REG_V17, 166 TCG_REG_V18, 167 TCG_REG_V19, 168}; 169 170static const int tcg_target_call_iarg_regs[] = { 171 TCG_REG_R3, 172 TCG_REG_R4, 173 TCG_REG_R5, 174 TCG_REG_R6, 175 TCG_REG_R7, 176 TCG_REG_R8, 177 TCG_REG_R9, 178 TCG_REG_R10 179}; 180 181static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 182{ 183 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 184 tcg_debug_assert(slot >= 0 && slot <= 1); 185 return TCG_REG_R3 + slot; 186} 187 188static const int tcg_target_callee_save_regs[] = { 189#ifdef _CALL_DARWIN 190 TCG_REG_R11, 191#endif 192 TCG_REG_R14, 193 TCG_REG_R15, 194 TCG_REG_R16, 195 TCG_REG_R17, 196 TCG_REG_R18, 197 TCG_REG_R19, 198 TCG_REG_R20, 199 TCG_REG_R21, 200 TCG_REG_R22, 201 TCG_REG_R23, 202 TCG_REG_R24, 203 TCG_REG_R25, 204 TCG_REG_R26, 205 TCG_REG_R27, /* currently used for the global env */ 206 TCG_REG_R28, 207 TCG_REG_R29, 208 TCG_REG_R30, 209 TCG_REG_R31 210}; 211 212static inline bool in_range_b(tcg_target_long target) 213{ 214 return target == sextract64(target, 0, 26); 215} 216 217static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, 218 const tcg_insn_unit *target) 219{ 220 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 221 tcg_debug_assert(in_range_b(disp)); 222 return disp & 0x3fffffc; 223} 224 225static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 226{ 227 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 228 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 229 230 if (in_range_b(disp)) { 231 *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc); 232 return true; 233 } 234 return false; 235} 236 237static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, 238 const tcg_insn_unit *target) 239{ 240 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 241 tcg_debug_assert(disp == (int16_t) disp); 242 return disp & 0xfffc; 243} 244 245static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 246{ 247 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 248 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 249 250 if (disp == (int16_t) disp) { 251 *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc); 252 return true; 253 } 254 return false; 255} 256 257/* test if a constant matches the constraint */ 258static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 259{ 260 if (ct & TCG_CT_CONST) { 261 return 1; 262 } 263 264 /* The only 32-bit constraint we use aside from 265 TCG_CT_CONST is TCG_CT_CONST_S16. */ 266 if (type == TCG_TYPE_I32) { 267 val = (int32_t)val; 268 } 269 270 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 271 return 1; 272 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 273 return 1; 274 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 275 return 1; 276 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 277 return 1; 278 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) { 279 return 1; 280 } else if ((ct & TCG_CT_CONST_WSZ) 281 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 282 return 1; 283 } 284 return 0; 285} 286 287#define OPCD(opc) ((opc)<<26) 288#define XO19(opc) (OPCD(19)|((opc)<<1)) 289#define MD30(opc) (OPCD(30)|((opc)<<2)) 290#define MDS30(opc) (OPCD(30)|((opc)<<1)) 291#define XO31(opc) (OPCD(31)|((opc)<<1)) 292#define XO58(opc) (OPCD(58)|(opc)) 293#define XO62(opc) (OPCD(62)|(opc)) 294#define VX4(opc) (OPCD(4)|(opc)) 295 296#define B OPCD( 18) 297#define BC OPCD( 16) 298#define LBZ OPCD( 34) 299#define LHZ OPCD( 40) 300#define LHA OPCD( 42) 301#define LWZ OPCD( 32) 302#define LWZUX XO31( 55) 303#define STB OPCD( 38) 304#define STH OPCD( 44) 305#define STW OPCD( 36) 306 307#define STD XO62( 0) 308#define STDU XO62( 1) 309#define STDX XO31(149) 310 311#define LD XO58( 0) 312#define LDX XO31( 21) 313#define LDU XO58( 1) 314#define LDUX XO31( 53) 315#define LWA XO58( 2) 316#define LWAX XO31(341) 317 318#define ADDIC OPCD( 12) 319#define ADDI OPCD( 14) 320#define ADDIS OPCD( 15) 321#define ORI OPCD( 24) 322#define ORIS OPCD( 25) 323#define XORI OPCD( 26) 324#define XORIS OPCD( 27) 325#define ANDI OPCD( 28) 326#define ANDIS OPCD( 29) 327#define MULLI OPCD( 7) 328#define CMPLI OPCD( 10) 329#define CMPI OPCD( 11) 330#define SUBFIC OPCD( 8) 331 332#define LWZU OPCD( 33) 333#define STWU OPCD( 37) 334 335#define RLWIMI OPCD( 20) 336#define RLWINM OPCD( 21) 337#define RLWNM OPCD( 23) 338 339#define RLDICL MD30( 0) 340#define RLDICR MD30( 1) 341#define RLDIMI MD30( 3) 342#define RLDCL MDS30( 8) 343 344#define BCLR XO19( 16) 345#define BCCTR XO19(528) 346#define CRAND XO19(257) 347#define CRANDC XO19(129) 348#define CRNAND XO19(225) 349#define CROR XO19(449) 350#define CRNOR XO19( 33) 351 352#define EXTSB XO31(954) 353#define EXTSH XO31(922) 354#define EXTSW XO31(986) 355#define ADD XO31(266) 356#define ADDE XO31(138) 357#define ADDME XO31(234) 358#define ADDZE XO31(202) 359#define ADDC XO31( 10) 360#define AND XO31( 28) 361#define SUBF XO31( 40) 362#define SUBFC XO31( 8) 363#define SUBFE XO31(136) 364#define SUBFME XO31(232) 365#define SUBFZE XO31(200) 366#define OR XO31(444) 367#define XOR XO31(316) 368#define MULLW XO31(235) 369#define MULHW XO31( 75) 370#define MULHWU XO31( 11) 371#define DIVW XO31(491) 372#define DIVWU XO31(459) 373#define MODSW XO31(779) 374#define MODUW XO31(267) 375#define CMP XO31( 0) 376#define CMPL XO31( 32) 377#define LHBRX XO31(790) 378#define LWBRX XO31(534) 379#define LDBRX XO31(532) 380#define STHBRX XO31(918) 381#define STWBRX XO31(662) 382#define STDBRX XO31(660) 383#define MFSPR XO31(339) 384#define MTSPR XO31(467) 385#define SRAWI XO31(824) 386#define NEG XO31(104) 387#define MFCR XO31( 19) 388#define MFOCRF (MFCR | (1u << 20)) 389#define NOR XO31(124) 390#define CNTLZW XO31( 26) 391#define CNTLZD XO31( 58) 392#define CNTTZW XO31(538) 393#define CNTTZD XO31(570) 394#define CNTPOPW XO31(378) 395#define CNTPOPD XO31(506) 396#define ANDC XO31( 60) 397#define ORC XO31(412) 398#define EQV XO31(284) 399#define NAND XO31(476) 400#define ISEL XO31( 15) 401 402#define MULLD XO31(233) 403#define MULHD XO31( 73) 404#define MULHDU XO31( 9) 405#define DIVD XO31(489) 406#define DIVDU XO31(457) 407#define MODSD XO31(777) 408#define MODUD XO31(265) 409 410#define LBZX XO31( 87) 411#define LHZX XO31(279) 412#define LHAX XO31(343) 413#define LWZX XO31( 23) 414#define STBX XO31(215) 415#define STHX XO31(407) 416#define STWX XO31(151) 417 418#define EIEIO XO31(854) 419#define HWSYNC XO31(598) 420#define LWSYNC (HWSYNC | (1u << 21)) 421 422#define SPR(a, b) ((((a)<<5)|(b))<<11) 423#define LR SPR(8, 0) 424#define CTR SPR(9, 0) 425 426#define SLW XO31( 24) 427#define SRW XO31(536) 428#define SRAW XO31(792) 429 430#define SLD XO31( 27) 431#define SRD XO31(539) 432#define SRAD XO31(794) 433#define SRADI XO31(413<<1) 434 435#define BRH XO31(219) 436#define BRW XO31(155) 437#define BRD XO31(187) 438 439#define TW XO31( 4) 440#define TRAP (TW | TO(31)) 441 442#define NOP ORI /* ori 0,0,0 */ 443 444#define LVX XO31(103) 445#define LVEBX XO31(7) 446#define LVEHX XO31(39) 447#define LVEWX XO31(71) 448#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */ 449#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */ 450#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */ 451#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */ 452#define LXSD (OPCD(57) | 2) /* v3.00 */ 453#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */ 454 455#define STVX XO31(231) 456#define STVEWX XO31(199) 457#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */ 458#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */ 459#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */ 460#define STXSD (OPCD(61) | 2) /* v3.00 */ 461 462#define VADDSBS VX4(768) 463#define VADDUBS VX4(512) 464#define VADDUBM VX4(0) 465#define VADDSHS VX4(832) 466#define VADDUHS VX4(576) 467#define VADDUHM VX4(64) 468#define VADDSWS VX4(896) 469#define VADDUWS VX4(640) 470#define VADDUWM VX4(128) 471#define VADDUDM VX4(192) /* v2.07 */ 472 473#define VSUBSBS VX4(1792) 474#define VSUBUBS VX4(1536) 475#define VSUBUBM VX4(1024) 476#define VSUBSHS VX4(1856) 477#define VSUBUHS VX4(1600) 478#define VSUBUHM VX4(1088) 479#define VSUBSWS VX4(1920) 480#define VSUBUWS VX4(1664) 481#define VSUBUWM VX4(1152) 482#define VSUBUDM VX4(1216) /* v2.07 */ 483 484#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ 485#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ 486 487#define VMAXSB VX4(258) 488#define VMAXSH VX4(322) 489#define VMAXSW VX4(386) 490#define VMAXSD VX4(450) /* v2.07 */ 491#define VMAXUB VX4(2) 492#define VMAXUH VX4(66) 493#define VMAXUW VX4(130) 494#define VMAXUD VX4(194) /* v2.07 */ 495#define VMINSB VX4(770) 496#define VMINSH VX4(834) 497#define VMINSW VX4(898) 498#define VMINSD VX4(962) /* v2.07 */ 499#define VMINUB VX4(514) 500#define VMINUH VX4(578) 501#define VMINUW VX4(642) 502#define VMINUD VX4(706) /* v2.07 */ 503 504#define VCMPEQUB VX4(6) 505#define VCMPEQUH VX4(70) 506#define VCMPEQUW VX4(134) 507#define VCMPEQUD VX4(199) /* v2.07 */ 508#define VCMPGTSB VX4(774) 509#define VCMPGTSH VX4(838) 510#define VCMPGTSW VX4(902) 511#define VCMPGTSD VX4(967) /* v2.07 */ 512#define VCMPGTUB VX4(518) 513#define VCMPGTUH VX4(582) 514#define VCMPGTUW VX4(646) 515#define VCMPGTUD VX4(711) /* v2.07 */ 516#define VCMPNEB VX4(7) /* v3.00 */ 517#define VCMPNEH VX4(71) /* v3.00 */ 518#define VCMPNEW VX4(135) /* v3.00 */ 519 520#define VSLB VX4(260) 521#define VSLH VX4(324) 522#define VSLW VX4(388) 523#define VSLD VX4(1476) /* v2.07 */ 524#define VSRB VX4(516) 525#define VSRH VX4(580) 526#define VSRW VX4(644) 527#define VSRD VX4(1732) /* v2.07 */ 528#define VSRAB VX4(772) 529#define VSRAH VX4(836) 530#define VSRAW VX4(900) 531#define VSRAD VX4(964) /* v2.07 */ 532#define VRLB VX4(4) 533#define VRLH VX4(68) 534#define VRLW VX4(132) 535#define VRLD VX4(196) /* v2.07 */ 536 537#define VMULEUB VX4(520) 538#define VMULEUH VX4(584) 539#define VMULEUW VX4(648) /* v2.07 */ 540#define VMULOUB VX4(8) 541#define VMULOUH VX4(72) 542#define VMULOUW VX4(136) /* v2.07 */ 543#define VMULUWM VX4(137) /* v2.07 */ 544#define VMULLD VX4(457) /* v3.10 */ 545#define VMSUMUHM VX4(38) 546 547#define VMRGHB VX4(12) 548#define VMRGHH VX4(76) 549#define VMRGHW VX4(140) 550#define VMRGLB VX4(268) 551#define VMRGLH VX4(332) 552#define VMRGLW VX4(396) 553 554#define VPKUHUM VX4(14) 555#define VPKUWUM VX4(78) 556 557#define VAND VX4(1028) 558#define VANDC VX4(1092) 559#define VNOR VX4(1284) 560#define VOR VX4(1156) 561#define VXOR VX4(1220) 562#define VEQV VX4(1668) /* v2.07 */ 563#define VNAND VX4(1412) /* v2.07 */ 564#define VORC VX4(1348) /* v2.07 */ 565 566#define VSPLTB VX4(524) 567#define VSPLTH VX4(588) 568#define VSPLTW VX4(652) 569#define VSPLTISB VX4(780) 570#define VSPLTISH VX4(844) 571#define VSPLTISW VX4(908) 572 573#define VSLDOI VX4(44) 574 575#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */ 576#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */ 577#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */ 578 579#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */ 580#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */ 581#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */ 582#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */ 583#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */ 584#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */ 585 586#define RT(r) ((r)<<21) 587#define RS(r) ((r)<<21) 588#define RA(r) ((r)<<16) 589#define RB(r) ((r)<<11) 590#define TO(t) ((t)<<21) 591#define SH(s) ((s)<<11) 592#define MB(b) ((b)<<6) 593#define ME(e) ((e)<<1) 594#define BO(o) ((o)<<21) 595#define MB64(b) ((b)<<5) 596#define FXM(b) (1 << (19 - (b))) 597 598#define VRT(r) (((r) & 31) << 21) 599#define VRA(r) (((r) & 31) << 16) 600#define VRB(r) (((r) & 31) << 11) 601#define VRC(r) (((r) & 31) << 6) 602 603#define LK 1 604 605#define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) 606#define SAB(s, a, b) (RS(s) | RA(a) | RB(b)) 607#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff)) 608#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff)) 609 610#define BF(n) ((n)<<23) 611#define BI(n, c) (((c)+((n)*4))<<16) 612#define BT(n, c) (((c)+((n)*4))<<21) 613#define BA(n, c) (((c)+((n)*4))<<16) 614#define BB(n, c) (((c)+((n)*4))<<11) 615#define BC_(n, c) (((c)+((n)*4))<<6) 616 617#define BO_COND_TRUE BO(12) 618#define BO_COND_FALSE BO( 4) 619#define BO_ALWAYS BO(20) 620 621enum { 622 CR_LT, 623 CR_GT, 624 CR_EQ, 625 CR_SO 626}; 627 628static const uint32_t tcg_to_bc[] = { 629 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE, 630 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE, 631 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE, 632 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE, 633 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE, 634 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE, 635 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE, 636 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE, 637 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE, 638 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE, 639}; 640 641/* The low bit here is set if the RA and RB fields must be inverted. */ 642static const uint32_t tcg_to_isel[] = { 643 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ), 644 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1, 645 [TCG_COND_LT] = ISEL | BC_(7, CR_LT), 646 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1, 647 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1, 648 [TCG_COND_GT] = ISEL | BC_(7, CR_GT), 649 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT), 650 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1, 651 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1, 652 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), 653}; 654 655static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 656 intptr_t value, intptr_t addend) 657{ 658 const tcg_insn_unit *target; 659 int16_t lo; 660 int32_t hi; 661 662 value += addend; 663 target = (const tcg_insn_unit *)value; 664 665 switch (type) { 666 case R_PPC_REL14: 667 return reloc_pc14(code_ptr, target); 668 case R_PPC_REL24: 669 return reloc_pc24(code_ptr, target); 670 case R_PPC_ADDR16: 671 /* 672 * We are (slightly) abusing this relocation type. In particular, 673 * assert that the low 2 bits are zero, and do not modify them. 674 * That way we can use this with LD et al that have opcode bits 675 * in the low 2 bits of the insn. 676 */ 677 if ((value & 3) || value != (int16_t)value) { 678 return false; 679 } 680 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc); 681 break; 682 case R_PPC_ADDR32: 683 /* 684 * We are abusing this relocation type. Again, this points to 685 * a pair of insns, lis + load. This is an absolute address 686 * relocation for PPC32 so the lis cannot be removed. 687 */ 688 lo = value; 689 hi = value - lo; 690 if (hi + lo != value) { 691 return false; 692 } 693 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); 694 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); 695 break; 696 default: 697 g_assert_not_reached(); 698 } 699 return true; 700} 701 702static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 703 TCGReg base, tcg_target_long offset); 704 705static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 706{ 707 if (ret == arg) { 708 return true; 709 } 710 switch (type) { 711 case TCG_TYPE_I64: 712 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 713 /* fallthru */ 714 case TCG_TYPE_I32: 715 if (ret < TCG_REG_V0) { 716 if (arg < TCG_REG_V0) { 717 tcg_out32(s, OR | SAB(arg, ret, arg)); 718 break; 719 } else if (have_isa_2_07) { 720 tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD) 721 | VRT(arg) | RA(ret)); 722 break; 723 } else { 724 /* Altivec does not support vector->integer moves. */ 725 return false; 726 } 727 } else if (arg < TCG_REG_V0) { 728 if (have_isa_2_07) { 729 tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD) 730 | VRT(ret) | RA(arg)); 731 break; 732 } else { 733 /* Altivec does not support integer->vector moves. */ 734 return false; 735 } 736 } 737 /* fallthru */ 738 case TCG_TYPE_V64: 739 case TCG_TYPE_V128: 740 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0); 741 tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg)); 742 break; 743 default: 744 g_assert_not_reached(); 745 } 746 return true; 747} 748 749static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, 750 int sh, int mb) 751{ 752 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 753 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); 754 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f)); 755 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb); 756} 757 758static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs, 759 int sh, int mb, int me) 760{ 761 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me)); 762} 763 764static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 765{ 766 tcg_out32(s, EXTSB | RA(dst) | RS(src)); 767} 768 769static void tcg_out_ext8u(TCGContext *s, TCGReg dst, TCGReg src) 770{ 771 tcg_out32(s, ANDI | SAI(src, dst, 0xff)); 772} 773 774static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 775{ 776 tcg_out32(s, EXTSH | RA(dst) | RS(src)); 777} 778 779static void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src) 780{ 781 tcg_out32(s, ANDI | SAI(src, dst, 0xffff)); 782} 783 784static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src) 785{ 786 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 787 tcg_out32(s, EXTSW | RA(dst) | RS(src)); 788} 789 790static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) 791{ 792 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 793 tcg_out_rld(s, RLDICL, dst, src, 0, 32); 794} 795 796static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 797{ 798 tcg_out_ext32s(s, dst, src); 799} 800 801static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 802{ 803 tcg_out_ext32u(s, dst, src); 804} 805 806static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 807{ 808 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 809 tcg_out_mov(s, TCG_TYPE_I32, rd, rn); 810} 811 812static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c) 813{ 814 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); 815} 816 817static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c) 818{ 819 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c); 820} 821 822static inline void tcg_out_sari32(TCGContext *s, TCGReg dst, TCGReg src, int c) 823{ 824 /* Limit immediate shift count lest we create an illegal insn. */ 825 tcg_out32(s, SRAWI | RA(dst) | RS(src) | SH(c & 31)); 826} 827 828static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c) 829{ 830 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31); 831} 832 833static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) 834{ 835 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); 836} 837 838static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c) 839{ 840 tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2)); 841} 842 843static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags) 844{ 845 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 846 847 if (have_isa_3_10) { 848 tcg_out32(s, BRH | RA(dst) | RS(src)); 849 if (flags & TCG_BSWAP_OS) { 850 tcg_out_ext16s(s, TCG_TYPE_REG, dst, dst); 851 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 852 tcg_out_ext16u(s, dst, dst); 853 } 854 return; 855 } 856 857 /* 858 * In the following, 859 * dep(a, b, m) -> (a & ~m) | (b & m) 860 * 861 * Begin with: src = xxxxabcd 862 */ 863 /* tmp = rol32(src, 24) & 0x000000ff = 0000000c */ 864 tcg_out_rlw(s, RLWINM, tmp, src, 24, 24, 31); 865 /* tmp = dep(tmp, rol32(src, 8), 0x0000ff00) = 000000dc */ 866 tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23); 867 868 if (flags & TCG_BSWAP_OS) { 869 tcg_out_ext16s(s, TCG_TYPE_REG, dst, tmp); 870 } else { 871 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 872 } 873} 874 875static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags) 876{ 877 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 878 879 if (have_isa_3_10) { 880 tcg_out32(s, BRW | RA(dst) | RS(src)); 881 if (flags & TCG_BSWAP_OS) { 882 tcg_out_ext32s(s, dst, dst); 883 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 884 tcg_out_ext32u(s, dst, dst); 885 } 886 return; 887 } 888 889 /* 890 * Stolen from gcc's builtin_bswap32. 891 * In the following, 892 * dep(a, b, m) -> (a & ~m) | (b & m) 893 * 894 * Begin with: src = xxxxabcd 895 */ 896 /* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */ 897 tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31); 898 /* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */ 899 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7); 900 /* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */ 901 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23); 902 903 if (flags & TCG_BSWAP_OS) { 904 tcg_out_ext32s(s, dst, tmp); 905 } else { 906 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 907 } 908} 909 910static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src) 911{ 912 TCGReg t0 = dst == src ? TCG_REG_R0 : dst; 913 TCGReg t1 = dst == src ? dst : TCG_REG_R0; 914 915 if (have_isa_3_10) { 916 tcg_out32(s, BRD | RA(dst) | RS(src)); 917 return; 918 } 919 920 /* 921 * In the following, 922 * dep(a, b, m) -> (a & ~m) | (b & m) 923 * 924 * Begin with: src = abcdefgh 925 */ 926 /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */ 927 tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31); 928 /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */ 929 tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7); 930 /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */ 931 tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23); 932 933 /* t0 = rol64(t0, 32) = hgfe0000 */ 934 tcg_out_rld(s, RLDICL, t0, t0, 32, 0); 935 /* t1 = rol64(src, 32) = efghabcd */ 936 tcg_out_rld(s, RLDICL, t1, src, 32, 0); 937 938 /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */ 939 tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31); 940 /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */ 941 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7); 942 /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */ 943 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23); 944 945 tcg_out_mov(s, TCG_TYPE_REG, dst, t0); 946} 947 948/* Emit a move into ret of arg, if it can be done in one insn. */ 949static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 950{ 951 if (arg == (int16_t)arg) { 952 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 953 return true; 954 } 955 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 956 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 957 return true; 958 } 959 return false; 960} 961 962static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 963 tcg_target_long arg, bool in_prologue) 964{ 965 intptr_t tb_diff; 966 tcg_target_long tmp; 967 int shift; 968 969 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 970 971 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 972 arg = (int32_t)arg; 973 } 974 975 /* Load 16-bit immediates with one insn. */ 976 if (tcg_out_movi_one(s, ret, arg)) { 977 return; 978 } 979 980 /* Load addresses within the TB with one insn. */ 981 tb_diff = tcg_tbrel_diff(s, (void *)arg); 982 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { 983 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); 984 return; 985 } 986 987 /* Load 32-bit immediates with two insns. Note that we've already 988 eliminated bare ADDIS, so we know both insns are required. */ 989 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 990 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 991 tcg_out32(s, ORI | SAI(ret, ret, arg)); 992 return; 993 } 994 if (arg == (uint32_t)arg && !(arg & 0x8000)) { 995 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 996 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 997 return; 998 } 999 1000 /* Load masked 16-bit value. */ 1001 if (arg > 0 && (arg & 0x8000)) { 1002 tmp = arg | 0x7fff; 1003 if ((tmp & (tmp + 1)) == 0) { 1004 int mb = clz64(tmp + 1) + 1; 1005 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1006 tcg_out_rld(s, RLDICL, ret, ret, 0, mb); 1007 return; 1008 } 1009 } 1010 1011 /* Load common masks with 2 insns. */ 1012 shift = ctz64(arg); 1013 tmp = arg >> shift; 1014 if (tmp == (int16_t)tmp) { 1015 tcg_out32(s, ADDI | TAI(ret, 0, tmp)); 1016 tcg_out_shli64(s, ret, ret, shift); 1017 return; 1018 } 1019 shift = clz64(arg); 1020 if (tcg_out_movi_one(s, ret, arg << shift)) { 1021 tcg_out_shri64(s, ret, ret, shift); 1022 return; 1023 } 1024 1025 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ 1026 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) { 1027 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); 1028 return; 1029 } 1030 1031 /* Use the constant pool, if possible. */ 1032 if (!in_prologue && USE_REG_TB) { 1033 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, 1034 tcg_tbrel_diff(s, NULL)); 1035 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); 1036 return; 1037 } 1038 1039 tmp = arg >> 31 >> 1; 1040 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); 1041 if (tmp) { 1042 tcg_out_shli64(s, ret, ret, 32); 1043 } 1044 if (arg & 0xffff0000) { 1045 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 1046 } 1047 if (arg & 0xffff) { 1048 tcg_out32(s, ORI | SAI(ret, ret, arg)); 1049 } 1050} 1051 1052static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1053 TCGReg ret, int64_t val) 1054{ 1055 uint32_t load_insn; 1056 int rel, low; 1057 intptr_t add; 1058 1059 switch (vece) { 1060 case MO_8: 1061 low = (int8_t)val; 1062 if (low >= -16 && low < 16) { 1063 tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); 1064 return; 1065 } 1066 if (have_isa_3_00) { 1067 tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); 1068 return; 1069 } 1070 break; 1071 1072 case MO_16: 1073 low = (int16_t)val; 1074 if (low >= -16 && low < 16) { 1075 tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); 1076 return; 1077 } 1078 break; 1079 1080 case MO_32: 1081 low = (int32_t)val; 1082 if (low >= -16 && low < 16) { 1083 tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); 1084 return; 1085 } 1086 break; 1087 } 1088 1089 /* 1090 * Otherwise we must load the value from the constant pool. 1091 */ 1092 if (USE_REG_TB) { 1093 rel = R_PPC_ADDR16; 1094 add = tcg_tbrel_diff(s, NULL); 1095 } else { 1096 rel = R_PPC_ADDR32; 1097 add = 0; 1098 } 1099 1100 if (have_vsx) { 1101 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX; 1102 load_insn |= VRT(ret) | RB(TCG_REG_TMP1); 1103 if (TCG_TARGET_REG_BITS == 64) { 1104 new_pool_label(s, val, rel, s->code_ptr, add); 1105 } else { 1106 new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); 1107 } 1108 } else { 1109 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); 1110 if (TCG_TARGET_REG_BITS == 64) { 1111 new_pool_l2(s, rel, s->code_ptr, add, val, val); 1112 } else { 1113 new_pool_l4(s, rel, s->code_ptr, add, 1114 val >> 32, val, val >> 32, val); 1115 } 1116 } 1117 1118 if (USE_REG_TB) { 1119 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0)); 1120 load_insn |= RA(TCG_REG_TB); 1121 } else { 1122 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0)); 1123 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); 1124 } 1125 tcg_out32(s, load_insn); 1126} 1127 1128static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, 1129 tcg_target_long arg) 1130{ 1131 switch (type) { 1132 case TCG_TYPE_I32: 1133 case TCG_TYPE_I64: 1134 tcg_debug_assert(ret < TCG_REG_V0); 1135 tcg_out_movi_int(s, type, ret, arg, false); 1136 break; 1137 1138 default: 1139 g_assert_not_reached(); 1140 } 1141} 1142 1143static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1144{ 1145 return false; 1146} 1147 1148static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1149 tcg_target_long imm) 1150{ 1151 /* This function is only used for passing structs by reference. */ 1152 g_assert_not_reached(); 1153} 1154 1155static bool mask_operand(uint32_t c, int *mb, int *me) 1156{ 1157 uint32_t lsb, test; 1158 1159 /* Accept a bit pattern like: 1160 0....01....1 1161 1....10....0 1162 0..01..10..0 1163 Keep track of the transitions. */ 1164 if (c == 0 || c == -1) { 1165 return false; 1166 } 1167 test = c; 1168 lsb = test & -test; 1169 test += lsb; 1170 if (test & (test - 1)) { 1171 return false; 1172 } 1173 1174 *me = clz32(lsb); 1175 *mb = test ? clz32(test & -test) + 1 : 0; 1176 return true; 1177} 1178 1179static bool mask64_operand(uint64_t c, int *mb, int *me) 1180{ 1181 uint64_t lsb; 1182 1183 if (c == 0) { 1184 return false; 1185 } 1186 1187 lsb = c & -c; 1188 /* Accept 1..10..0. */ 1189 if (c == -lsb) { 1190 *mb = 0; 1191 *me = clz64(lsb); 1192 return true; 1193 } 1194 /* Accept 0..01..1. */ 1195 if (lsb == 1 && (c & (c + 1)) == 0) { 1196 *mb = clz64(c + 1) + 1; 1197 *me = 63; 1198 return true; 1199 } 1200 return false; 1201} 1202 1203static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1204{ 1205 int mb, me; 1206 1207 if (mask_operand(c, &mb, &me)) { 1208 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); 1209 } else if ((c & 0xffff) == c) { 1210 tcg_out32(s, ANDI | SAI(src, dst, c)); 1211 return; 1212 } else if ((c & 0xffff0000) == c) { 1213 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1214 return; 1215 } else { 1216 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); 1217 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1218 } 1219} 1220 1221static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) 1222{ 1223 int mb, me; 1224 1225 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1226 if (mask64_operand(c, &mb, &me)) { 1227 if (mb == 0) { 1228 tcg_out_rld(s, RLDICR, dst, src, 0, me); 1229 } else { 1230 tcg_out_rld(s, RLDICL, dst, src, 0, mb); 1231 } 1232 } else if ((c & 0xffff) == c) { 1233 tcg_out32(s, ANDI | SAI(src, dst, c)); 1234 return; 1235 } else if ((c & 0xffff0000) == c) { 1236 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1237 return; 1238 } else { 1239 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); 1240 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1241 } 1242} 1243 1244static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, 1245 int op_lo, int op_hi) 1246{ 1247 if (c >> 16) { 1248 tcg_out32(s, op_hi | SAI(src, dst, c >> 16)); 1249 src = dst; 1250 } 1251 if (c & 0xffff) { 1252 tcg_out32(s, op_lo | SAI(src, dst, c)); 1253 src = dst; 1254 } 1255} 1256 1257static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1258{ 1259 tcg_out_zori32(s, dst, src, c, ORI, ORIS); 1260} 1261 1262static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1263{ 1264 tcg_out_zori32(s, dst, src, c, XORI, XORIS); 1265} 1266 1267static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target) 1268{ 1269 ptrdiff_t disp = tcg_pcrel_diff(s, target); 1270 if (in_range_b(disp)) { 1271 tcg_out32(s, B | (disp & 0x3fffffc) | mask); 1272 } else { 1273 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target); 1274 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR); 1275 tcg_out32(s, BCCTR | BO_ALWAYS | mask); 1276 } 1277} 1278 1279static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 1280 TCGReg base, tcg_target_long offset) 1281{ 1282 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0; 1283 bool is_int_store = false; 1284 TCGReg rs = TCG_REG_TMP1; 1285 1286 switch (opi) { 1287 case LD: case LWA: 1288 align = 3; 1289 /* FALLTHRU */ 1290 default: 1291 if (rt > TCG_REG_R0 && rt < TCG_REG_V0) { 1292 rs = rt; 1293 break; 1294 } 1295 break; 1296 case LXSD: 1297 case STXSD: 1298 align = 3; 1299 break; 1300 case LXV: 1301 case STXV: 1302 align = 15; 1303 break; 1304 case STD: 1305 align = 3; 1306 /* FALLTHRU */ 1307 case STB: case STH: case STW: 1308 is_int_store = true; 1309 break; 1310 } 1311 1312 /* For unaligned, or very large offsets, use the indexed form. */ 1313 if (offset & align || offset != (int32_t)offset || opi == 0) { 1314 if (rs == base) { 1315 rs = TCG_REG_R0; 1316 } 1317 tcg_debug_assert(!is_int_store || rs != rt); 1318 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); 1319 tcg_out32(s, opx | TAB(rt & 31, base, rs)); 1320 return; 1321 } 1322 1323 l0 = (int16_t)offset; 1324 offset = (offset - l0) >> 16; 1325 l1 = (int16_t)offset; 1326 1327 if (l1 < 0 && orig >= 0) { 1328 extra = 0x4000; 1329 l1 = (int16_t)(offset - 0x4000); 1330 } 1331 if (l1) { 1332 tcg_out32(s, ADDIS | TAI(rs, base, l1)); 1333 base = rs; 1334 } 1335 if (extra) { 1336 tcg_out32(s, ADDIS | TAI(rs, base, extra)); 1337 base = rs; 1338 } 1339 if (opi != ADDI || base != rt || l0 != 0) { 1340 tcg_out32(s, opi | TAI(rt & 31, base, l0)); 1341 } 1342} 1343 1344static void tcg_out_vsldoi(TCGContext *s, TCGReg ret, 1345 TCGReg va, TCGReg vb, int shb) 1346{ 1347 tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6)); 1348} 1349 1350static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1351 TCGReg base, intptr_t offset) 1352{ 1353 int shift; 1354 1355 switch (type) { 1356 case TCG_TYPE_I32: 1357 if (ret < TCG_REG_V0) { 1358 tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); 1359 break; 1360 } 1361 if (have_isa_2_07 && have_vsx) { 1362 tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset); 1363 break; 1364 } 1365 tcg_debug_assert((offset & 3) == 0); 1366 tcg_out_mem_long(s, 0, LVEWX, ret, base, offset); 1367 shift = (offset - 4) & 0xc; 1368 if (shift) { 1369 tcg_out_vsldoi(s, ret, ret, ret, shift); 1370 } 1371 break; 1372 case TCG_TYPE_I64: 1373 if (ret < TCG_REG_V0) { 1374 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1375 tcg_out_mem_long(s, LD, LDX, ret, base, offset); 1376 break; 1377 } 1378 /* fallthru */ 1379 case TCG_TYPE_V64: 1380 tcg_debug_assert(ret >= TCG_REG_V0); 1381 if (have_vsx) { 1382 tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX, 1383 ret, base, offset); 1384 break; 1385 } 1386 tcg_debug_assert((offset & 7) == 0); 1387 tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16); 1388 if (offset & 8) { 1389 tcg_out_vsldoi(s, ret, ret, ret, 8); 1390 } 1391 break; 1392 case TCG_TYPE_V128: 1393 tcg_debug_assert(ret >= TCG_REG_V0); 1394 tcg_debug_assert((offset & 15) == 0); 1395 tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0, 1396 LVX, ret, base, offset); 1397 break; 1398 default: 1399 g_assert_not_reached(); 1400 } 1401} 1402 1403static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1404 TCGReg base, intptr_t offset) 1405{ 1406 int shift; 1407 1408 switch (type) { 1409 case TCG_TYPE_I32: 1410 if (arg < TCG_REG_V0) { 1411 tcg_out_mem_long(s, STW, STWX, arg, base, offset); 1412 break; 1413 } 1414 if (have_isa_2_07 && have_vsx) { 1415 tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset); 1416 break; 1417 } 1418 assert((offset & 3) == 0); 1419 tcg_debug_assert((offset & 3) == 0); 1420 shift = (offset - 4) & 0xc; 1421 if (shift) { 1422 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift); 1423 arg = TCG_VEC_TMP1; 1424 } 1425 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1426 break; 1427 case TCG_TYPE_I64: 1428 if (arg < TCG_REG_V0) { 1429 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1430 tcg_out_mem_long(s, STD, STDX, arg, base, offset); 1431 break; 1432 } 1433 /* fallthru */ 1434 case TCG_TYPE_V64: 1435 tcg_debug_assert(arg >= TCG_REG_V0); 1436 if (have_vsx) { 1437 tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0, 1438 STXSDX, arg, base, offset); 1439 break; 1440 } 1441 tcg_debug_assert((offset & 7) == 0); 1442 if (offset & 8) { 1443 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8); 1444 arg = TCG_VEC_TMP1; 1445 } 1446 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1447 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4); 1448 break; 1449 case TCG_TYPE_V128: 1450 tcg_debug_assert(arg >= TCG_REG_V0); 1451 tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0, 1452 STVX, arg, base, offset); 1453 break; 1454 default: 1455 g_assert_not_reached(); 1456 } 1457} 1458 1459static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1460 TCGReg base, intptr_t ofs) 1461{ 1462 return false; 1463} 1464 1465static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, 1466 int const_arg2, int cr, TCGType type) 1467{ 1468 int imm; 1469 uint32_t op; 1470 1471 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1472 1473 /* Simplify the comparisons below wrt CMPI. */ 1474 if (type == TCG_TYPE_I32) { 1475 arg2 = (int32_t)arg2; 1476 } 1477 1478 switch (cond) { 1479 case TCG_COND_EQ: 1480 case TCG_COND_NE: 1481 if (const_arg2) { 1482 if ((int16_t) arg2 == arg2) { 1483 op = CMPI; 1484 imm = 1; 1485 break; 1486 } else if ((uint16_t) arg2 == arg2) { 1487 op = CMPLI; 1488 imm = 1; 1489 break; 1490 } 1491 } 1492 op = CMPL; 1493 imm = 0; 1494 break; 1495 1496 case TCG_COND_LT: 1497 case TCG_COND_GE: 1498 case TCG_COND_LE: 1499 case TCG_COND_GT: 1500 if (const_arg2) { 1501 if ((int16_t) arg2 == arg2) { 1502 op = CMPI; 1503 imm = 1; 1504 break; 1505 } 1506 } 1507 op = CMP; 1508 imm = 0; 1509 break; 1510 1511 case TCG_COND_LTU: 1512 case TCG_COND_GEU: 1513 case TCG_COND_LEU: 1514 case TCG_COND_GTU: 1515 if (const_arg2) { 1516 if ((uint16_t) arg2 == arg2) { 1517 op = CMPLI; 1518 imm = 1; 1519 break; 1520 } 1521 } 1522 op = CMPL; 1523 imm = 0; 1524 break; 1525 1526 default: 1527 g_assert_not_reached(); 1528 } 1529 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21); 1530 1531 if (imm) { 1532 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff)); 1533 } else { 1534 if (const_arg2) { 1535 tcg_out_movi(s, type, TCG_REG_R0, arg2); 1536 arg2 = TCG_REG_R0; 1537 } 1538 tcg_out32(s, op | RA(arg1) | RB(arg2)); 1539 } 1540} 1541 1542static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, 1543 TCGReg dst, TCGReg src) 1544{ 1545 if (type == TCG_TYPE_I32) { 1546 tcg_out32(s, CNTLZW | RS(src) | RA(dst)); 1547 tcg_out_shri32(s, dst, dst, 5); 1548 } else { 1549 tcg_out32(s, CNTLZD | RS(src) | RA(dst)); 1550 tcg_out_shri64(s, dst, dst, 6); 1551 } 1552} 1553 1554static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src) 1555{ 1556 /* X != 0 implies X + -1 generates a carry. Extra addition 1557 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */ 1558 if (dst != src) { 1559 tcg_out32(s, ADDIC | TAI(dst, src, -1)); 1560 tcg_out32(s, SUBFE | TAB(dst, dst, src)); 1561 } else { 1562 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); 1563 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src)); 1564 } 1565} 1566 1567static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2, 1568 bool const_arg2) 1569{ 1570 if (const_arg2) { 1571 if ((uint32_t)arg2 == arg2) { 1572 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2); 1573 } else { 1574 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2); 1575 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0)); 1576 } 1577 } else { 1578 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2)); 1579 } 1580 return TCG_REG_R0; 1581} 1582 1583static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, 1584 TCGArg arg0, TCGArg arg1, TCGArg arg2, 1585 int const_arg2) 1586{ 1587 int crop, sh; 1588 1589 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1590 1591 /* Ignore high bits of a potential constant arg2. */ 1592 if (type == TCG_TYPE_I32) { 1593 arg2 = (uint32_t)arg2; 1594 } 1595 1596 /* Handle common and trivial cases before handling anything else. */ 1597 if (arg2 == 0) { 1598 switch (cond) { 1599 case TCG_COND_EQ: 1600 tcg_out_setcond_eq0(s, type, arg0, arg1); 1601 return; 1602 case TCG_COND_NE: 1603 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 1604 tcg_out_ext32u(s, TCG_REG_R0, arg1); 1605 arg1 = TCG_REG_R0; 1606 } 1607 tcg_out_setcond_ne0(s, arg0, arg1); 1608 return; 1609 case TCG_COND_GE: 1610 tcg_out32(s, NOR | SAB(arg1, arg0, arg1)); 1611 arg1 = arg0; 1612 /* FALLTHRU */ 1613 case TCG_COND_LT: 1614 /* Extract the sign bit. */ 1615 if (type == TCG_TYPE_I32) { 1616 tcg_out_shri32(s, arg0, arg1, 31); 1617 } else { 1618 tcg_out_shri64(s, arg0, arg1, 63); 1619 } 1620 return; 1621 default: 1622 break; 1623 } 1624 } 1625 1626 /* If we have ISEL, we can implement everything with 3 or 4 insns. 1627 All other cases below are also at least 3 insns, so speed up the 1628 code generator by not considering them and always using ISEL. */ 1629 if (have_isel) { 1630 int isel, tab; 1631 1632 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1633 1634 isel = tcg_to_isel[cond]; 1635 1636 tcg_out_movi(s, type, arg0, 1); 1637 if (isel & 1) { 1638 /* arg0 = (bc ? 0 : 1) */ 1639 tab = TAB(arg0, 0, arg0); 1640 isel &= ~1; 1641 } else { 1642 /* arg0 = (bc ? 1 : 0) */ 1643 tcg_out_movi(s, type, TCG_REG_R0, 0); 1644 tab = TAB(arg0, arg0, TCG_REG_R0); 1645 } 1646 tcg_out32(s, isel | tab); 1647 return; 1648 } 1649 1650 switch (cond) { 1651 case TCG_COND_EQ: 1652 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 1653 tcg_out_setcond_eq0(s, type, arg0, arg1); 1654 return; 1655 1656 case TCG_COND_NE: 1657 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 1658 /* Discard the high bits only once, rather than both inputs. */ 1659 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 1660 tcg_out_ext32u(s, TCG_REG_R0, arg1); 1661 arg1 = TCG_REG_R0; 1662 } 1663 tcg_out_setcond_ne0(s, arg0, arg1); 1664 return; 1665 1666 case TCG_COND_GT: 1667 case TCG_COND_GTU: 1668 sh = 30; 1669 crop = 0; 1670 goto crtest; 1671 1672 case TCG_COND_LT: 1673 case TCG_COND_LTU: 1674 sh = 29; 1675 crop = 0; 1676 goto crtest; 1677 1678 case TCG_COND_GE: 1679 case TCG_COND_GEU: 1680 sh = 31; 1681 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT); 1682 goto crtest; 1683 1684 case TCG_COND_LE: 1685 case TCG_COND_LEU: 1686 sh = 31; 1687 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT); 1688 crtest: 1689 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1690 if (crop) { 1691 tcg_out32(s, crop); 1692 } 1693 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 1694 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); 1695 break; 1696 1697 default: 1698 g_assert_not_reached(); 1699 } 1700} 1701 1702static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l) 1703{ 1704 if (l->has_value) { 1705 bc |= reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr); 1706 } else { 1707 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); 1708 } 1709 tcg_out32(s, bc); 1710} 1711 1712static void tcg_out_brcond(TCGContext *s, TCGCond cond, 1713 TCGArg arg1, TCGArg arg2, int const_arg2, 1714 TCGLabel *l, TCGType type) 1715{ 1716 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1717 tcg_out_bc(s, tcg_to_bc[cond], l); 1718} 1719 1720static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, 1721 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1, 1722 TCGArg v2, bool const_c2) 1723{ 1724 /* If for some reason both inputs are zero, don't produce bad code. */ 1725 if (v1 == 0 && v2 == 0) { 1726 tcg_out_movi(s, type, dest, 0); 1727 return; 1728 } 1729 1730 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); 1731 1732 if (have_isel) { 1733 int isel = tcg_to_isel[cond]; 1734 1735 /* Swap the V operands if the operation indicates inversion. */ 1736 if (isel & 1) { 1737 int t = v1; 1738 v1 = v2; 1739 v2 = t; 1740 isel &= ~1; 1741 } 1742 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */ 1743 if (v2 == 0) { 1744 tcg_out_movi(s, type, TCG_REG_R0, 0); 1745 } 1746 tcg_out32(s, isel | TAB(dest, v1, v2)); 1747 } else { 1748 if (dest == v2) { 1749 cond = tcg_invert_cond(cond); 1750 v2 = v1; 1751 } else if (dest != v1) { 1752 if (v1 == 0) { 1753 tcg_out_movi(s, type, dest, 0); 1754 } else { 1755 tcg_out_mov(s, type, dest, v1); 1756 } 1757 } 1758 /* Branch forward over one insn */ 1759 tcg_out32(s, tcg_to_bc[cond] | 8); 1760 if (v2 == 0) { 1761 tcg_out_movi(s, type, dest, 0); 1762 } else { 1763 tcg_out_mov(s, type, dest, v2); 1764 } 1765 } 1766} 1767 1768static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc, 1769 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2) 1770{ 1771 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) { 1772 tcg_out32(s, opc | RA(a0) | RS(a1)); 1773 } else { 1774 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type); 1775 /* Note that the only other valid constant for a2 is 0. */ 1776 if (have_isel) { 1777 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); 1778 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0)); 1779 } else if (!const_a2 && a0 == a2) { 1780 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8); 1781 tcg_out32(s, opc | RA(a0) | RS(a1)); 1782 } else { 1783 tcg_out32(s, opc | RA(a0) | RS(a1)); 1784 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8); 1785 if (const_a2) { 1786 tcg_out_movi(s, type, a0, 0); 1787 } else { 1788 tcg_out_mov(s, type, a0, a2); 1789 } 1790 } 1791 } 1792} 1793 1794static void tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1795 const int *const_args) 1796{ 1797 static const struct { uint8_t bit1, bit2; } bits[] = { 1798 [TCG_COND_LT ] = { CR_LT, CR_LT }, 1799 [TCG_COND_LE ] = { CR_LT, CR_GT }, 1800 [TCG_COND_GT ] = { CR_GT, CR_GT }, 1801 [TCG_COND_GE ] = { CR_GT, CR_LT }, 1802 [TCG_COND_LTU] = { CR_LT, CR_LT }, 1803 [TCG_COND_LEU] = { CR_LT, CR_GT }, 1804 [TCG_COND_GTU] = { CR_GT, CR_GT }, 1805 [TCG_COND_GEU] = { CR_GT, CR_LT }, 1806 }; 1807 1808 TCGCond cond = args[4], cond2; 1809 TCGArg al, ah, bl, bh; 1810 int blconst, bhconst; 1811 int op, bit1, bit2; 1812 1813 al = args[0]; 1814 ah = args[1]; 1815 bl = args[2]; 1816 bh = args[3]; 1817 blconst = const_args[2]; 1818 bhconst = const_args[3]; 1819 1820 switch (cond) { 1821 case TCG_COND_EQ: 1822 op = CRAND; 1823 goto do_equality; 1824 case TCG_COND_NE: 1825 op = CRNAND; 1826 do_equality: 1827 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); 1828 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); 1829 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 1830 break; 1831 1832 case TCG_COND_LT: 1833 case TCG_COND_LE: 1834 case TCG_COND_GT: 1835 case TCG_COND_GE: 1836 case TCG_COND_LTU: 1837 case TCG_COND_LEU: 1838 case TCG_COND_GTU: 1839 case TCG_COND_GEU: 1840 bit1 = bits[cond].bit1; 1841 bit2 = bits[cond].bit2; 1842 op = (bit1 != bit2 ? CRANDC : CRAND); 1843 cond2 = tcg_unsigned_cond(cond); 1844 1845 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); 1846 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); 1847 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); 1848 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ)); 1849 break; 1850 1851 default: 1852 g_assert_not_reached(); 1853 } 1854} 1855 1856static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, 1857 const int *const_args) 1858{ 1859 tcg_out_cmp2(s, args + 1, const_args + 1); 1860 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 1861 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); 1862} 1863 1864static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, 1865 const int *const_args) 1866{ 1867 tcg_out_cmp2(s, args, const_args); 1868 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5])); 1869} 1870 1871static void tcg_out_mb(TCGContext *s, TCGArg a0) 1872{ 1873 uint32_t insn; 1874 1875 if (a0 & TCG_MO_ST_LD) { 1876 insn = HWSYNC; 1877 } else { 1878 insn = LWSYNC; 1879 } 1880 1881 tcg_out32(s, insn); 1882} 1883 1884static void tcg_out_call_int(TCGContext *s, int lk, 1885 const tcg_insn_unit *target) 1886{ 1887#ifdef _CALL_AIX 1888 /* Look through the descriptor. If the branch is in range, and we 1889 don't have to spend too much effort on building the toc. */ 1890 const void *tgt = ((const void * const *)target)[0]; 1891 uintptr_t toc = ((const uintptr_t *)target)[1]; 1892 intptr_t diff = tcg_pcrel_diff(s, tgt); 1893 1894 if (in_range_b(diff) && toc == (uint32_t)toc) { 1895 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); 1896 tcg_out_b(s, lk, tgt); 1897 } else { 1898 /* Fold the low bits of the constant into the addresses below. */ 1899 intptr_t arg = (intptr_t)target; 1900 int ofs = (int16_t)arg; 1901 1902 if (ofs + 8 < 0x8000) { 1903 arg -= ofs; 1904 } else { 1905 ofs = 0; 1906 } 1907 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg); 1908 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); 1909 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); 1910 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); 1911 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 1912 } 1913#elif defined(_CALL_ELF) && _CALL_ELF == 2 1914 intptr_t diff; 1915 1916 /* In the ELFv2 ABI, we have to set up r12 to contain the destination 1917 address, which the callee uses to compute its TOC address. */ 1918 /* FIXME: when the branch is in range, we could avoid r12 load if we 1919 knew that the destination uses the same TOC, and what its local 1920 entry point offset is. */ 1921 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target); 1922 1923 diff = tcg_pcrel_diff(s, target); 1924 if (in_range_b(diff)) { 1925 tcg_out_b(s, lk, target); 1926 } else { 1927 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); 1928 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 1929 } 1930#else 1931 tcg_out_b(s, lk, target); 1932#endif 1933} 1934 1935static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, 1936 const TCGHelperInfo *info) 1937{ 1938 tcg_out_call_int(s, LK, target); 1939} 1940 1941static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = { 1942 [MO_UB] = LBZX, 1943 [MO_UW] = LHZX, 1944 [MO_UL] = LWZX, 1945 [MO_UQ] = LDX, 1946 [MO_SW] = LHAX, 1947 [MO_SL] = LWAX, 1948 [MO_BSWAP | MO_UB] = LBZX, 1949 [MO_BSWAP | MO_UW] = LHBRX, 1950 [MO_BSWAP | MO_UL] = LWBRX, 1951 [MO_BSWAP | MO_UQ] = LDBRX, 1952}; 1953 1954static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = { 1955 [MO_UB] = STBX, 1956 [MO_UW] = STHX, 1957 [MO_UL] = STWX, 1958 [MO_UQ] = STDX, 1959 [MO_BSWAP | MO_UB] = STBX, 1960 [MO_BSWAP | MO_UW] = STHBRX, 1961 [MO_BSWAP | MO_UL] = STWBRX, 1962 [MO_BSWAP | MO_UQ] = STDBRX, 1963}; 1964 1965#if defined (CONFIG_SOFTMMU) 1966/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, 1967 * int mmu_idx, uintptr_t ra) 1968 */ 1969static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = { 1970 [MO_UB] = helper_ret_ldub_mmu, 1971 [MO_LEUW] = helper_le_lduw_mmu, 1972 [MO_LEUL] = helper_le_ldul_mmu, 1973 [MO_LEUQ] = helper_le_ldq_mmu, 1974 [MO_BEUW] = helper_be_lduw_mmu, 1975 [MO_BEUL] = helper_be_ldul_mmu, 1976 [MO_BEUQ] = helper_be_ldq_mmu, 1977}; 1978 1979/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, 1980 * uintxx_t val, int mmu_idx, uintptr_t ra) 1981 */ 1982static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = { 1983 [MO_UB] = helper_ret_stb_mmu, 1984 [MO_LEUW] = helper_le_stw_mmu, 1985 [MO_LEUL] = helper_le_stl_mmu, 1986 [MO_LEUQ] = helper_le_stq_mmu, 1987 [MO_BEUW] = helper_be_stw_mmu, 1988 [MO_BEUL] = helper_be_stl_mmu, 1989 [MO_BEUQ] = helper_be_stq_mmu, 1990}; 1991 1992static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1993{ 1994 if (arg < 0) { 1995 arg = TCG_REG_TMP1; 1996 } 1997 tcg_out32(s, MFSPR | RT(arg) | LR); 1998 return arg; 1999} 2000 2001/* 2002 * For the purposes of ppc32 sorting 4 input registers into 4 argument 2003 * registers, there is an outside chance we would require 3 temps. 2004 */ 2005static const TCGLdstHelperParam ldst_helper_param = { 2006 .ra_gen = ldst_ra_gen, 2007 .ntmp = 3, 2008 .tmp = { TCG_REG_TMP1, TCG_REG_TMP2, TCG_REG_R0 } 2009}; 2010 2011static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2012{ 2013 MemOp opc = get_memop(lb->oi); 2014 2015 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2016 return false; 2017 } 2018 2019 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 2020 tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); 2021 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 2022 2023 tcg_out_b(s, 0, lb->raddr); 2024 return true; 2025} 2026 2027static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2028{ 2029 MemOp opc = get_memop(lb->oi); 2030 2031 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2032 return false; 2033 } 2034 2035 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 2036 tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); 2037 2038 tcg_out_b(s, 0, lb->raddr); 2039 return true; 2040} 2041#else 2042static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 2043{ 2044 if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2045 return false; 2046 } 2047 2048 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2049 TCGReg arg = TCG_REG_R4; 2050 2051 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); 2052 if (l->addrlo_reg != arg) { 2053 tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); 2054 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); 2055 } else if (l->addrhi_reg != arg + 1) { 2056 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); 2057 tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); 2058 } else { 2059 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg); 2060 tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1); 2061 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0); 2062 } 2063 } else { 2064 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg); 2065 } 2066 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0); 2067 2068 /* "Tail call" to the helper, with the return address back inline. */ 2069 tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld 2070 : helper_unaligned_st)); 2071 return true; 2072} 2073 2074static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2075{ 2076 return tcg_out_fail_alignment(s, l); 2077} 2078 2079static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2080{ 2081 return tcg_out_fail_alignment(s, l); 2082} 2083#endif /* SOFTMMU */ 2084 2085typedef struct { 2086 TCGReg base; 2087 TCGReg index; 2088} HostAddress; 2089 2090/* 2091 * For softmmu, perform the TLB load and compare. 2092 * For useronly, perform any required alignment tests. 2093 * In both cases, return a TCGLabelQemuLdst structure if the slow path 2094 * is required and fill in @h with the host address for the fast path. 2095 */ 2096static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 2097 TCGReg addrlo, TCGReg addrhi, 2098 MemOpIdx oi, bool is_ld) 2099{ 2100 TCGLabelQemuLdst *ldst = NULL; 2101 MemOp opc = get_memop(oi); 2102 unsigned a_bits = get_alignment_bits(opc); 2103 2104#ifdef CONFIG_SOFTMMU 2105 int mem_index = get_mmuidx(oi); 2106 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 2107 : offsetof(CPUTLBEntry, addr_write); 2108 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 2109 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 2110 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 2111 unsigned s_bits = opc & MO_SIZE; 2112 2113 ldst = new_ldst_label(s); 2114 ldst->is_ld = is_ld; 2115 ldst->oi = oi; 2116 ldst->addrlo_reg = addrlo; 2117 ldst->addrhi_reg = addrhi; 2118 2119 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 2120 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 2121 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 2122 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); 2123 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); 2124 2125 /* Extract the page index, shifted into place for tlb index. */ 2126 if (TCG_TARGET_REG_BITS == 32) { 2127 tcg_out_shri32(s, TCG_REG_R0, addrlo, 2128 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 2129 } else { 2130 tcg_out_shri64(s, TCG_REG_R0, addrlo, 2131 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 2132 } 2133 tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); 2134 2135 /* Load the (low part) TLB comparator into TMP2. */ 2136 if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 2137 uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32 2138 ? LWZUX : LDUX); 2139 tcg_out32(s, lxu | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); 2140 } else { 2141 tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); 2142 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2143 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, 2144 TCG_REG_TMP1, cmp_off + 4 * HOST_BIG_ENDIAN); 2145 } else { 2146 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off); 2147 } 2148 } 2149 2150 /* 2151 * Load the TLB addend for use on the fast path. 2152 * Do this asap to minimize any load use delay. 2153 */ 2154 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 2155 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, 2156 offsetof(CPUTLBEntry, addend)); 2157 } 2158 2159 /* Clear the non-page, non-alignment bits from the address in R0. */ 2160 if (TCG_TARGET_REG_BITS == 32) { 2161 /* 2162 * We don't support unaligned accesses on 32-bits. 2163 * Preserve the bottom bits and thus trigger a comparison 2164 * failure on unaligned accesses. 2165 */ 2166 if (a_bits < s_bits) { 2167 a_bits = s_bits; 2168 } 2169 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, 2170 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); 2171 } else { 2172 TCGReg t = addrlo; 2173 2174 /* 2175 * If the access is unaligned, we need to make sure we fail if we 2176 * cross a page boundary. The trick is to add the access size-1 2177 * to the address before masking the low bits. That will make the 2178 * address overflow to the next page if we cross a page boundary, 2179 * which will then force a mismatch of the TLB compare. 2180 */ 2181 if (a_bits < s_bits) { 2182 unsigned a_mask = (1 << a_bits) - 1; 2183 unsigned s_mask = (1 << s_bits) - 1; 2184 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); 2185 t = TCG_REG_R0; 2186 } 2187 2188 /* Mask the address for the requested alignment. */ 2189 if (TARGET_LONG_BITS == 32) { 2190 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, 2191 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); 2192 } else if (a_bits == 0) { 2193 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS); 2194 } else { 2195 tcg_out_rld(s, RLDICL, TCG_REG_R0, t, 2196 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); 2197 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0); 2198 } 2199 } 2200 2201 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2202 /* Low part comparison into cr7. */ 2203 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 2204 0, 7, TCG_TYPE_I32); 2205 2206 /* Load the high part TLB comparator into TMP2. */ 2207 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, 2208 cmp_off + 4 * !HOST_BIG_ENDIAN); 2209 2210 /* Load addend, deferred for this case. */ 2211 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, 2212 offsetof(CPUTLBEntry, addend)); 2213 2214 /* High part comparison into cr6. */ 2215 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I32); 2216 2217 /* Combine comparisons into cr7. */ 2218 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 2219 } else { 2220 /* Full comparison into cr7. */ 2221 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 2222 0, 7, TCG_TYPE_TL); 2223 } 2224 2225 /* Load a pointer into the current opcode w/conditional branch-link. */ 2226 ldst->label_ptr[0] = s->code_ptr; 2227 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); 2228 2229 h->base = TCG_REG_TMP1; 2230#else 2231 if (a_bits) { 2232 ldst = new_ldst_label(s); 2233 ldst->is_ld = is_ld; 2234 ldst->oi = oi; 2235 ldst->addrlo_reg = addrlo; 2236 ldst->addrhi_reg = addrhi; 2237 2238 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 2239 tcg_debug_assert(a_bits < 16); 2240 tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1)); 2241 2242 ldst->label_ptr[0] = s->code_ptr; 2243 tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); 2244 } 2245 2246 h->base = guest_base ? TCG_GUEST_BASE_REG : 0; 2247#endif 2248 2249 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 2250 /* Zero-extend the guest address for use in the host address. */ 2251 tcg_out_ext32u(s, TCG_REG_R0, addrlo); 2252 h->index = TCG_REG_R0; 2253 } else { 2254 h->index = addrlo; 2255 } 2256 2257 return ldst; 2258} 2259 2260static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 2261 TCGReg addrlo, TCGReg addrhi, 2262 MemOpIdx oi, TCGType data_type) 2263{ 2264 MemOp opc = get_memop(oi); 2265 TCGLabelQemuLdst *ldst; 2266 HostAddress h; 2267 2268 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 2269 2270 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 2271 if (opc & MO_BSWAP) { 2272 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2273 tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); 2274 tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0)); 2275 } else if (h.base != 0) { 2276 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2277 tcg_out32(s, LWZX | TAB(datahi, h.base, h.index)); 2278 tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0)); 2279 } else if (h.index == datahi) { 2280 tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); 2281 tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); 2282 } else { 2283 tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); 2284 tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); 2285 } 2286 } else { 2287 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; 2288 if (!have_isa_2_06 && insn == LDBRX) { 2289 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2290 tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); 2291 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); 2292 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); 2293 } else if (insn) { 2294 tcg_out32(s, insn | TAB(datalo, h.base, h.index)); 2295 } else { 2296 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; 2297 tcg_out32(s, insn | TAB(datalo, h.base, h.index)); 2298 tcg_out_movext(s, TCG_TYPE_REG, datalo, 2299 TCG_TYPE_REG, opc & MO_SSIZE, datalo); 2300 } 2301 } 2302 2303 if (ldst) { 2304 ldst->type = data_type; 2305 ldst->datalo_reg = datalo; 2306 ldst->datahi_reg = datahi; 2307 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2308 } 2309} 2310 2311static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 2312 TCGReg addrlo, TCGReg addrhi, 2313 MemOpIdx oi, TCGType data_type) 2314{ 2315 MemOp opc = get_memop(oi); 2316 TCGLabelQemuLdst *ldst; 2317 HostAddress h; 2318 2319 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 2320 2321 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 2322 if (opc & MO_BSWAP) { 2323 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2324 tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); 2325 tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0)); 2326 } else if (h.base != 0) { 2327 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2328 tcg_out32(s, STWX | SAB(datahi, h.base, h.index)); 2329 tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0)); 2330 } else { 2331 tcg_out32(s, STW | TAI(datahi, h.index, 0)); 2332 tcg_out32(s, STW | TAI(datalo, h.index, 4)); 2333 } 2334 } else { 2335 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; 2336 if (!have_isa_2_06 && insn == STDBRX) { 2337 tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); 2338 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, h.index, 4)); 2339 tcg_out_shri64(s, TCG_REG_R0, datalo, 32); 2340 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP1)); 2341 } else { 2342 tcg_out32(s, insn | SAB(datalo, h.base, h.index)); 2343 } 2344 } 2345 2346 if (ldst) { 2347 ldst->type = data_type; 2348 ldst->datalo_reg = datalo; 2349 ldst->datahi_reg = datahi; 2350 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2351 } 2352} 2353 2354static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2355{ 2356 int i; 2357 for (i = 0; i < count; ++i) { 2358 p[i] = NOP; 2359 } 2360} 2361 2362/* Parameters for function call generation, used in tcg.c. */ 2363#define TCG_TARGET_STACK_ALIGN 16 2364 2365#ifdef _CALL_AIX 2366# define LINK_AREA_SIZE (6 * SZR) 2367# define LR_OFFSET (1 * SZR) 2368# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) 2369#elif defined(_CALL_DARWIN) 2370# define LINK_AREA_SIZE (6 * SZR) 2371# define LR_OFFSET (2 * SZR) 2372#elif TCG_TARGET_REG_BITS == 64 2373# if defined(_CALL_ELF) && _CALL_ELF == 2 2374# define LINK_AREA_SIZE (4 * SZR) 2375# define LR_OFFSET (1 * SZR) 2376# endif 2377#else /* TCG_TARGET_REG_BITS == 32 */ 2378# if defined(_CALL_SYSV) 2379# define LINK_AREA_SIZE (2 * SZR) 2380# define LR_OFFSET (1 * SZR) 2381# endif 2382#endif 2383#ifndef LR_OFFSET 2384# error "Unhandled abi" 2385#endif 2386#ifndef TCG_TARGET_CALL_STACK_OFFSET 2387# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE 2388#endif 2389 2390#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2391#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR) 2392 2393#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \ 2394 + TCG_STATIC_CALL_ARGS_SIZE \ 2395 + CPU_TEMP_BUF_SIZE \ 2396 + REG_SAVE_SIZE \ 2397 + TCG_TARGET_STACK_ALIGN - 1) \ 2398 & -TCG_TARGET_STACK_ALIGN) 2399 2400#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE) 2401 2402static void tcg_target_qemu_prologue(TCGContext *s) 2403{ 2404 int i; 2405 2406#ifdef _CALL_AIX 2407 const void **desc = (const void **)s->code_ptr; 2408 desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */ 2409 desc[1] = 0; /* environment pointer */ 2410 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ 2411#endif 2412 2413 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, 2414 CPU_TEMP_BUF_SIZE); 2415 2416 /* Prologue */ 2417 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR); 2418 tcg_out32(s, (SZR == 8 ? STDU : STWU) 2419 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); 2420 2421 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2422 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2423 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2424 } 2425 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2426 2427#ifndef CONFIG_SOFTMMU 2428 if (guest_base) { 2429 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); 2430 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2431 } 2432#endif 2433 2434 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2435 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); 2436 if (USE_REG_TB) { 2437 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2438 } 2439 tcg_out32(s, BCCTR | BO_ALWAYS); 2440 2441 /* Epilogue */ 2442 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2443 2444 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2445 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2446 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2447 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2448 } 2449 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR); 2450 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE)); 2451 tcg_out32(s, BCLR | BO_ALWAYS); 2452} 2453 2454static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 2455{ 2456 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, arg); 2457 tcg_out_b(s, 0, tcg_code_gen_epilogue); 2458} 2459 2460static void tcg_out_goto_tb(TCGContext *s, int which) 2461{ 2462 uintptr_t ptr = get_jmp_target_addr(s, which); 2463 2464 if (USE_REG_TB) { 2465 ptrdiff_t offset = tcg_tbrel_diff(s, (void *)ptr); 2466 tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset); 2467 2468 /* Direct branch will be patched by tb_target_set_jmp_target. */ 2469 set_jmp_insn_offset(s, which); 2470 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); 2471 2472 /* When branch is out of range, fall through to indirect. */ 2473 tcg_out32(s, BCCTR | BO_ALWAYS); 2474 2475 /* For the unlinked case, need to reset TCG_REG_TB. */ 2476 set_jmp_reset_offset(s, which); 2477 tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, 2478 -tcg_current_code_size(s)); 2479 } else { 2480 /* Direct branch will be patched by tb_target_set_jmp_target. */ 2481 set_jmp_insn_offset(s, which); 2482 tcg_out32(s, NOP); 2483 2484 /* When branch is out of range, fall through to indirect. */ 2485 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); 2486 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)ptr); 2487 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); 2488 tcg_out32(s, BCCTR | BO_ALWAYS); 2489 set_jmp_reset_offset(s, which); 2490 } 2491} 2492 2493void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2494 uintptr_t jmp_rx, uintptr_t jmp_rw) 2495{ 2496 uintptr_t addr = tb->jmp_target_addr[n]; 2497 intptr_t diff = addr - jmp_rx; 2498 tcg_insn_unit insn; 2499 2500 if (in_range_b(diff)) { 2501 insn = B | (diff & 0x3fffffc); 2502 } else if (USE_REG_TB) { 2503 insn = MTSPR | RS(TCG_REG_TB) | CTR; 2504 } else { 2505 insn = NOP; 2506 } 2507 2508 qatomic_set((uint32_t *)jmp_rw, insn); 2509 flush_idcache_range(jmp_rx, jmp_rw, 4); 2510} 2511 2512static void tcg_out_op(TCGContext *s, TCGOpcode opc, 2513 const TCGArg args[TCG_MAX_OP_ARGS], 2514 const int const_args[TCG_MAX_OP_ARGS]) 2515{ 2516 TCGArg a0, a1, a2; 2517 2518 switch (opc) { 2519 case INDEX_op_goto_ptr: 2520 tcg_out32(s, MTSPR | RS(args[0]) | CTR); 2521 if (USE_REG_TB) { 2522 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); 2523 } 2524 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); 2525 tcg_out32(s, BCCTR | BO_ALWAYS); 2526 break; 2527 case INDEX_op_br: 2528 { 2529 TCGLabel *l = arg_label(args[0]); 2530 uint32_t insn = B; 2531 2532 if (l->has_value) { 2533 insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr), 2534 l->u.value_ptr); 2535 } else { 2536 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0); 2537 } 2538 tcg_out32(s, insn); 2539 } 2540 break; 2541 case INDEX_op_ld8u_i32: 2542 case INDEX_op_ld8u_i64: 2543 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 2544 break; 2545 case INDEX_op_ld8s_i32: 2546 case INDEX_op_ld8s_i64: 2547 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 2548 tcg_out_ext8s(s, TCG_TYPE_REG, args[0], args[0]); 2549 break; 2550 case INDEX_op_ld16u_i32: 2551 case INDEX_op_ld16u_i64: 2552 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); 2553 break; 2554 case INDEX_op_ld16s_i32: 2555 case INDEX_op_ld16s_i64: 2556 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); 2557 break; 2558 case INDEX_op_ld_i32: 2559 case INDEX_op_ld32u_i64: 2560 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); 2561 break; 2562 case INDEX_op_ld32s_i64: 2563 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); 2564 break; 2565 case INDEX_op_ld_i64: 2566 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); 2567 break; 2568 case INDEX_op_st8_i32: 2569 case INDEX_op_st8_i64: 2570 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); 2571 break; 2572 case INDEX_op_st16_i32: 2573 case INDEX_op_st16_i64: 2574 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); 2575 break; 2576 case INDEX_op_st_i32: 2577 case INDEX_op_st32_i64: 2578 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); 2579 break; 2580 case INDEX_op_st_i64: 2581 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); 2582 break; 2583 2584 case INDEX_op_add_i32: 2585 a0 = args[0], a1 = args[1], a2 = args[2]; 2586 if (const_args[2]) { 2587 do_addi_32: 2588 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); 2589 } else { 2590 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2591 } 2592 break; 2593 case INDEX_op_sub_i32: 2594 a0 = args[0], a1 = args[1], a2 = args[2]; 2595 if (const_args[1]) { 2596 if (const_args[2]) { 2597 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); 2598 } else { 2599 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 2600 } 2601 } else if (const_args[2]) { 2602 a2 = -a2; 2603 goto do_addi_32; 2604 } else { 2605 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 2606 } 2607 break; 2608 2609 case INDEX_op_and_i32: 2610 a0 = args[0], a1 = args[1], a2 = args[2]; 2611 if (const_args[2]) { 2612 tcg_out_andi32(s, a0, a1, a2); 2613 } else { 2614 tcg_out32(s, AND | SAB(a1, a0, a2)); 2615 } 2616 break; 2617 case INDEX_op_and_i64: 2618 a0 = args[0], a1 = args[1], a2 = args[2]; 2619 if (const_args[2]) { 2620 tcg_out_andi64(s, a0, a1, a2); 2621 } else { 2622 tcg_out32(s, AND | SAB(a1, a0, a2)); 2623 } 2624 break; 2625 case INDEX_op_or_i64: 2626 case INDEX_op_or_i32: 2627 a0 = args[0], a1 = args[1], a2 = args[2]; 2628 if (const_args[2]) { 2629 tcg_out_ori32(s, a0, a1, a2); 2630 } else { 2631 tcg_out32(s, OR | SAB(a1, a0, a2)); 2632 } 2633 break; 2634 case INDEX_op_xor_i64: 2635 case INDEX_op_xor_i32: 2636 a0 = args[0], a1 = args[1], a2 = args[2]; 2637 if (const_args[2]) { 2638 tcg_out_xori32(s, a0, a1, a2); 2639 } else { 2640 tcg_out32(s, XOR | SAB(a1, a0, a2)); 2641 } 2642 break; 2643 case INDEX_op_andc_i32: 2644 a0 = args[0], a1 = args[1], a2 = args[2]; 2645 if (const_args[2]) { 2646 tcg_out_andi32(s, a0, a1, ~a2); 2647 } else { 2648 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2649 } 2650 break; 2651 case INDEX_op_andc_i64: 2652 a0 = args[0], a1 = args[1], a2 = args[2]; 2653 if (const_args[2]) { 2654 tcg_out_andi64(s, a0, a1, ~a2); 2655 } else { 2656 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2657 } 2658 break; 2659 case INDEX_op_orc_i32: 2660 if (const_args[2]) { 2661 tcg_out_ori32(s, args[0], args[1], ~args[2]); 2662 break; 2663 } 2664 /* FALLTHRU */ 2665 case INDEX_op_orc_i64: 2666 tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); 2667 break; 2668 case INDEX_op_eqv_i32: 2669 if (const_args[2]) { 2670 tcg_out_xori32(s, args[0], args[1], ~args[2]); 2671 break; 2672 } 2673 /* FALLTHRU */ 2674 case INDEX_op_eqv_i64: 2675 tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); 2676 break; 2677 case INDEX_op_nand_i32: 2678 case INDEX_op_nand_i64: 2679 tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); 2680 break; 2681 case INDEX_op_nor_i32: 2682 case INDEX_op_nor_i64: 2683 tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); 2684 break; 2685 2686 case INDEX_op_clz_i32: 2687 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1], 2688 args[2], const_args[2]); 2689 break; 2690 case INDEX_op_ctz_i32: 2691 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1], 2692 args[2], const_args[2]); 2693 break; 2694 case INDEX_op_ctpop_i32: 2695 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0)); 2696 break; 2697 2698 case INDEX_op_clz_i64: 2699 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1], 2700 args[2], const_args[2]); 2701 break; 2702 case INDEX_op_ctz_i64: 2703 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1], 2704 args[2], const_args[2]); 2705 break; 2706 case INDEX_op_ctpop_i64: 2707 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0)); 2708 break; 2709 2710 case INDEX_op_mul_i32: 2711 a0 = args[0], a1 = args[1], a2 = args[2]; 2712 if (const_args[2]) { 2713 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 2714 } else { 2715 tcg_out32(s, MULLW | TAB(a0, a1, a2)); 2716 } 2717 break; 2718 2719 case INDEX_op_div_i32: 2720 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); 2721 break; 2722 2723 case INDEX_op_divu_i32: 2724 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); 2725 break; 2726 2727 case INDEX_op_rem_i32: 2728 tcg_out32(s, MODSW | TAB(args[0], args[1], args[2])); 2729 break; 2730 2731 case INDEX_op_remu_i32: 2732 tcg_out32(s, MODUW | TAB(args[0], args[1], args[2])); 2733 break; 2734 2735 case INDEX_op_shl_i32: 2736 if (const_args[2]) { 2737 /* Limit immediate shift count lest we create an illegal insn. */ 2738 tcg_out_shli32(s, args[0], args[1], args[2] & 31); 2739 } else { 2740 tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); 2741 } 2742 break; 2743 case INDEX_op_shr_i32: 2744 if (const_args[2]) { 2745 /* Limit immediate shift count lest we create an illegal insn. */ 2746 tcg_out_shri32(s, args[0], args[1], args[2] & 31); 2747 } else { 2748 tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); 2749 } 2750 break; 2751 case INDEX_op_sar_i32: 2752 if (const_args[2]) { 2753 tcg_out_sari32(s, args[0], args[1], args[2]); 2754 } else { 2755 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); 2756 } 2757 break; 2758 case INDEX_op_rotl_i32: 2759 if (const_args[2]) { 2760 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); 2761 } else { 2762 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) 2763 | MB(0) | ME(31)); 2764 } 2765 break; 2766 case INDEX_op_rotr_i32: 2767 if (const_args[2]) { 2768 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); 2769 } else { 2770 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); 2771 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) 2772 | MB(0) | ME(31)); 2773 } 2774 break; 2775 2776 case INDEX_op_brcond_i32: 2777 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 2778 arg_label(args[3]), TCG_TYPE_I32); 2779 break; 2780 case INDEX_op_brcond_i64: 2781 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 2782 arg_label(args[3]), TCG_TYPE_I64); 2783 break; 2784 case INDEX_op_brcond2_i32: 2785 tcg_out_brcond2(s, args, const_args); 2786 break; 2787 2788 case INDEX_op_neg_i32: 2789 case INDEX_op_neg_i64: 2790 tcg_out32(s, NEG | RT(args[0]) | RA(args[1])); 2791 break; 2792 2793 case INDEX_op_not_i32: 2794 case INDEX_op_not_i64: 2795 tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); 2796 break; 2797 2798 case INDEX_op_add_i64: 2799 a0 = args[0], a1 = args[1], a2 = args[2]; 2800 if (const_args[2]) { 2801 do_addi_64: 2802 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); 2803 } else { 2804 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2805 } 2806 break; 2807 case INDEX_op_sub_i64: 2808 a0 = args[0], a1 = args[1], a2 = args[2]; 2809 if (const_args[1]) { 2810 if (const_args[2]) { 2811 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); 2812 } else { 2813 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 2814 } 2815 } else if (const_args[2]) { 2816 a2 = -a2; 2817 goto do_addi_64; 2818 } else { 2819 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 2820 } 2821 break; 2822 2823 case INDEX_op_shl_i64: 2824 if (const_args[2]) { 2825 /* Limit immediate shift count lest we create an illegal insn. */ 2826 tcg_out_shli64(s, args[0], args[1], args[2] & 63); 2827 } else { 2828 tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); 2829 } 2830 break; 2831 case INDEX_op_shr_i64: 2832 if (const_args[2]) { 2833 /* Limit immediate shift count lest we create an illegal insn. */ 2834 tcg_out_shri64(s, args[0], args[1], args[2] & 63); 2835 } else { 2836 tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); 2837 } 2838 break; 2839 case INDEX_op_sar_i64: 2840 if (const_args[2]) { 2841 tcg_out_sari64(s, args[0], args[1], args[2]); 2842 } else { 2843 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); 2844 } 2845 break; 2846 case INDEX_op_rotl_i64: 2847 if (const_args[2]) { 2848 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); 2849 } else { 2850 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); 2851 } 2852 break; 2853 case INDEX_op_rotr_i64: 2854 if (const_args[2]) { 2855 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); 2856 } else { 2857 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); 2858 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0)); 2859 } 2860 break; 2861 2862 case INDEX_op_mul_i64: 2863 a0 = args[0], a1 = args[1], a2 = args[2]; 2864 if (const_args[2]) { 2865 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 2866 } else { 2867 tcg_out32(s, MULLD | TAB(a0, a1, a2)); 2868 } 2869 break; 2870 case INDEX_op_div_i64: 2871 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); 2872 break; 2873 case INDEX_op_divu_i64: 2874 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); 2875 break; 2876 case INDEX_op_rem_i64: 2877 tcg_out32(s, MODSD | TAB(args[0], args[1], args[2])); 2878 break; 2879 case INDEX_op_remu_i64: 2880 tcg_out32(s, MODUD | TAB(args[0], args[1], args[2])); 2881 break; 2882 2883 case INDEX_op_qemu_ld_i32: 2884 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 2885 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, 2886 args[2], TCG_TYPE_I32); 2887 } else { 2888 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], 2889 args[3], TCG_TYPE_I32); 2890 } 2891 break; 2892 case INDEX_op_qemu_ld_i64: 2893 if (TCG_TARGET_REG_BITS == 64) { 2894 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, 2895 args[2], TCG_TYPE_I64); 2896 } else if (TARGET_LONG_BITS == 32) { 2897 tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, 2898 args[3], TCG_TYPE_I64); 2899 } else { 2900 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], 2901 args[4], TCG_TYPE_I64); 2902 } 2903 break; 2904 case INDEX_op_qemu_st_i32: 2905 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 2906 tcg_out_qemu_st(s, args[0], -1, args[1], -1, 2907 args[2], TCG_TYPE_I32); 2908 } else { 2909 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], 2910 args[3], TCG_TYPE_I32); 2911 } 2912 break; 2913 case INDEX_op_qemu_st_i64: 2914 if (TCG_TARGET_REG_BITS == 64) { 2915 tcg_out_qemu_st(s, args[0], -1, args[1], -1, 2916 args[2], TCG_TYPE_I64); 2917 } else if (TARGET_LONG_BITS == 32) { 2918 tcg_out_qemu_st(s, args[0], args[1], args[2], -1, 2919 args[3], TCG_TYPE_I64); 2920 } else { 2921 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], 2922 args[4], TCG_TYPE_I64); 2923 } 2924 break; 2925 2926 case INDEX_op_setcond_i32: 2927 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], 2928 const_args[2]); 2929 break; 2930 case INDEX_op_setcond_i64: 2931 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], 2932 const_args[2]); 2933 break; 2934 case INDEX_op_setcond2_i32: 2935 tcg_out_setcond2(s, args, const_args); 2936 break; 2937 2938 case INDEX_op_bswap16_i32: 2939 case INDEX_op_bswap16_i64: 2940 tcg_out_bswap16(s, args[0], args[1], args[2]); 2941 break; 2942 case INDEX_op_bswap32_i32: 2943 tcg_out_bswap32(s, args[0], args[1], 0); 2944 break; 2945 case INDEX_op_bswap32_i64: 2946 tcg_out_bswap32(s, args[0], args[1], args[2]); 2947 break; 2948 case INDEX_op_bswap64_i64: 2949 tcg_out_bswap64(s, args[0], args[1]); 2950 break; 2951 2952 case INDEX_op_deposit_i32: 2953 if (const_args[2]) { 2954 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; 2955 tcg_out_andi32(s, args[0], args[0], ~mask); 2956 } else { 2957 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], 2958 32 - args[3] - args[4], 31 - args[3]); 2959 } 2960 break; 2961 case INDEX_op_deposit_i64: 2962 if (const_args[2]) { 2963 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; 2964 tcg_out_andi64(s, args[0], args[0], ~mask); 2965 } else { 2966 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], 2967 64 - args[3] - args[4]); 2968 } 2969 break; 2970 2971 case INDEX_op_extract_i32: 2972 tcg_out_rlw(s, RLWINM, args[0], args[1], 2973 32 - args[2], 32 - args[3], 31); 2974 break; 2975 case INDEX_op_extract_i64: 2976 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]); 2977 break; 2978 2979 case INDEX_op_movcond_i32: 2980 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], 2981 args[3], args[4], const_args[2]); 2982 break; 2983 case INDEX_op_movcond_i64: 2984 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], 2985 args[3], args[4], const_args[2]); 2986 break; 2987 2988#if TCG_TARGET_REG_BITS == 64 2989 case INDEX_op_add2_i64: 2990#else 2991 case INDEX_op_add2_i32: 2992#endif 2993 /* Note that the CA bit is defined based on the word size of the 2994 environment. So in 64-bit mode it's always carry-out of bit 63. 2995 The fallback code using deposit works just as well for 32-bit. */ 2996 a0 = args[0], a1 = args[1]; 2997 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { 2998 a0 = TCG_REG_R0; 2999 } 3000 if (const_args[4]) { 3001 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); 3002 } else { 3003 tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); 3004 } 3005 if (const_args[5]) { 3006 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); 3007 } else { 3008 tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); 3009 } 3010 if (a0 != args[0]) { 3011 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3012 } 3013 break; 3014 3015#if TCG_TARGET_REG_BITS == 64 3016 case INDEX_op_sub2_i64: 3017#else 3018 case INDEX_op_sub2_i32: 3019#endif 3020 a0 = args[0], a1 = args[1]; 3021 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { 3022 a0 = TCG_REG_R0; 3023 } 3024 if (const_args[2]) { 3025 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); 3026 } else { 3027 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); 3028 } 3029 if (const_args[3]) { 3030 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); 3031 } else { 3032 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); 3033 } 3034 if (a0 != args[0]) { 3035 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3036 } 3037 break; 3038 3039 case INDEX_op_muluh_i32: 3040 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); 3041 break; 3042 case INDEX_op_mulsh_i32: 3043 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); 3044 break; 3045 case INDEX_op_muluh_i64: 3046 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); 3047 break; 3048 case INDEX_op_mulsh_i64: 3049 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); 3050 break; 3051 3052 case INDEX_op_mb: 3053 tcg_out_mb(s, args[0]); 3054 break; 3055 3056 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 3057 case INDEX_op_mov_i64: 3058 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 3059 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 3060 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 3061 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 3062 case INDEX_op_ext8s_i64: 3063 case INDEX_op_ext8u_i32: 3064 case INDEX_op_ext8u_i64: 3065 case INDEX_op_ext16s_i32: 3066 case INDEX_op_ext16s_i64: 3067 case INDEX_op_ext16u_i32: 3068 case INDEX_op_ext16u_i64: 3069 case INDEX_op_ext32s_i64: 3070 case INDEX_op_ext32u_i64: 3071 case INDEX_op_ext_i32_i64: 3072 case INDEX_op_extu_i32_i64: 3073 case INDEX_op_extrl_i64_i32: 3074 default: 3075 g_assert_not_reached(); 3076 } 3077} 3078 3079int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3080{ 3081 switch (opc) { 3082 case INDEX_op_and_vec: 3083 case INDEX_op_or_vec: 3084 case INDEX_op_xor_vec: 3085 case INDEX_op_andc_vec: 3086 case INDEX_op_not_vec: 3087 case INDEX_op_nor_vec: 3088 case INDEX_op_eqv_vec: 3089 case INDEX_op_nand_vec: 3090 return 1; 3091 case INDEX_op_orc_vec: 3092 return have_isa_2_07; 3093 case INDEX_op_add_vec: 3094 case INDEX_op_sub_vec: 3095 case INDEX_op_smax_vec: 3096 case INDEX_op_smin_vec: 3097 case INDEX_op_umax_vec: 3098 case INDEX_op_umin_vec: 3099 case INDEX_op_shlv_vec: 3100 case INDEX_op_shrv_vec: 3101 case INDEX_op_sarv_vec: 3102 case INDEX_op_rotlv_vec: 3103 return vece <= MO_32 || have_isa_2_07; 3104 case INDEX_op_ssadd_vec: 3105 case INDEX_op_sssub_vec: 3106 case INDEX_op_usadd_vec: 3107 case INDEX_op_ussub_vec: 3108 return vece <= MO_32; 3109 case INDEX_op_cmp_vec: 3110 case INDEX_op_shli_vec: 3111 case INDEX_op_shri_vec: 3112 case INDEX_op_sari_vec: 3113 case INDEX_op_rotli_vec: 3114 return vece <= MO_32 || have_isa_2_07 ? -1 : 0; 3115 case INDEX_op_neg_vec: 3116 return vece >= MO_32 && have_isa_3_00; 3117 case INDEX_op_mul_vec: 3118 switch (vece) { 3119 case MO_8: 3120 case MO_16: 3121 return -1; 3122 case MO_32: 3123 return have_isa_2_07 ? 1 : -1; 3124 case MO_64: 3125 return have_isa_3_10; 3126 } 3127 return 0; 3128 case INDEX_op_bitsel_vec: 3129 return have_vsx; 3130 case INDEX_op_rotrv_vec: 3131 return -1; 3132 default: 3133 return 0; 3134 } 3135} 3136 3137static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 3138 TCGReg dst, TCGReg src) 3139{ 3140 tcg_debug_assert(dst >= TCG_REG_V0); 3141 3142 /* Splat from integer reg allowed via constraints for v3.00. */ 3143 if (src < TCG_REG_V0) { 3144 tcg_debug_assert(have_isa_3_00); 3145 switch (vece) { 3146 case MO_64: 3147 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src)); 3148 return true; 3149 case MO_32: 3150 tcg_out32(s, MTVSRWS | VRT(dst) | RA(src)); 3151 return true; 3152 default: 3153 /* Fail, so that we fall back on either dupm or mov+dup. */ 3154 return false; 3155 } 3156 } 3157 3158 /* 3159 * Recall we use (or emulate) VSX integer loads, so the integer is 3160 * right justified within the left (zero-index) double-word. 3161 */ 3162 switch (vece) { 3163 case MO_8: 3164 tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16)); 3165 break; 3166 case MO_16: 3167 tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16)); 3168 break; 3169 case MO_32: 3170 tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16)); 3171 break; 3172 case MO_64: 3173 if (have_vsx) { 3174 tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src)); 3175 break; 3176 } 3177 tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8); 3178 tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8); 3179 break; 3180 default: 3181 g_assert_not_reached(); 3182 } 3183 return true; 3184} 3185 3186static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 3187 TCGReg out, TCGReg base, intptr_t offset) 3188{ 3189 int elt; 3190 3191 tcg_debug_assert(out >= TCG_REG_V0); 3192 switch (vece) { 3193 case MO_8: 3194 if (have_isa_3_00) { 3195 tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16); 3196 } else { 3197 tcg_out_mem_long(s, 0, LVEBX, out, base, offset); 3198 } 3199 elt = extract32(offset, 0, 4); 3200#if !HOST_BIG_ENDIAN 3201 elt ^= 15; 3202#endif 3203 tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); 3204 break; 3205 case MO_16: 3206 tcg_debug_assert((offset & 1) == 0); 3207 if (have_isa_3_00) { 3208 tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16); 3209 } else { 3210 tcg_out_mem_long(s, 0, LVEHX, out, base, offset); 3211 } 3212 elt = extract32(offset, 1, 3); 3213#if !HOST_BIG_ENDIAN 3214 elt ^= 7; 3215#endif 3216 tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); 3217 break; 3218 case MO_32: 3219 if (have_isa_3_00) { 3220 tcg_out_mem_long(s, 0, LXVWSX, out, base, offset); 3221 break; 3222 } 3223 tcg_debug_assert((offset & 3) == 0); 3224 tcg_out_mem_long(s, 0, LVEWX, out, base, offset); 3225 elt = extract32(offset, 2, 2); 3226#if !HOST_BIG_ENDIAN 3227 elt ^= 3; 3228#endif 3229 tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); 3230 break; 3231 case MO_64: 3232 if (have_vsx) { 3233 tcg_out_mem_long(s, 0, LXVDSX, out, base, offset); 3234 break; 3235 } 3236 tcg_debug_assert((offset & 7) == 0); 3237 tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); 3238 tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); 3239 elt = extract32(offset, 3, 1); 3240#if !HOST_BIG_ENDIAN 3241 elt = !elt; 3242#endif 3243 if (elt) { 3244 tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8); 3245 } else { 3246 tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8); 3247 } 3248 break; 3249 default: 3250 g_assert_not_reached(); 3251 } 3252 return true; 3253} 3254 3255static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3256 unsigned vecl, unsigned vece, 3257 const TCGArg args[TCG_MAX_OP_ARGS], 3258 const int const_args[TCG_MAX_OP_ARGS]) 3259{ 3260 static const uint32_t 3261 add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, 3262 sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, 3263 mul_op[4] = { 0, 0, VMULUWM, VMULLD }, 3264 neg_op[4] = { 0, 0, VNEGW, VNEGD }, 3265 eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, 3266 ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, 3267 gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, 3268 gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, 3269 ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 }, 3270 usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 }, 3271 sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, 3272 ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, 3273 umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD }, 3274 smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD }, 3275 umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD }, 3276 smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD }, 3277 shlv_op[4] = { VSLB, VSLH, VSLW, VSLD }, 3278 shrv_op[4] = { VSRB, VSRH, VSRW, VSRD }, 3279 sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD }, 3280 mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 }, 3281 mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 }, 3282 muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 }, 3283 mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 }, 3284 pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 }, 3285 rotl_op[4] = { VRLB, VRLH, VRLW, VRLD }; 3286 3287 TCGType type = vecl + TCG_TYPE_V64; 3288 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 3289 uint32_t insn; 3290 3291 switch (opc) { 3292 case INDEX_op_ld_vec: 3293 tcg_out_ld(s, type, a0, a1, a2); 3294 return; 3295 case INDEX_op_st_vec: 3296 tcg_out_st(s, type, a0, a1, a2); 3297 return; 3298 case INDEX_op_dupm_vec: 3299 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3300 return; 3301 3302 case INDEX_op_add_vec: 3303 insn = add_op[vece]; 3304 break; 3305 case INDEX_op_sub_vec: 3306 insn = sub_op[vece]; 3307 break; 3308 case INDEX_op_neg_vec: 3309 insn = neg_op[vece]; 3310 a2 = a1; 3311 a1 = 0; 3312 break; 3313 case INDEX_op_mul_vec: 3314 insn = mul_op[vece]; 3315 break; 3316 case INDEX_op_ssadd_vec: 3317 insn = ssadd_op[vece]; 3318 break; 3319 case INDEX_op_sssub_vec: 3320 insn = sssub_op[vece]; 3321 break; 3322 case INDEX_op_usadd_vec: 3323 insn = usadd_op[vece]; 3324 break; 3325 case INDEX_op_ussub_vec: 3326 insn = ussub_op[vece]; 3327 break; 3328 case INDEX_op_smin_vec: 3329 insn = smin_op[vece]; 3330 break; 3331 case INDEX_op_umin_vec: 3332 insn = umin_op[vece]; 3333 break; 3334 case INDEX_op_smax_vec: 3335 insn = smax_op[vece]; 3336 break; 3337 case INDEX_op_umax_vec: 3338 insn = umax_op[vece]; 3339 break; 3340 case INDEX_op_shlv_vec: 3341 insn = shlv_op[vece]; 3342 break; 3343 case INDEX_op_shrv_vec: 3344 insn = shrv_op[vece]; 3345 break; 3346 case INDEX_op_sarv_vec: 3347 insn = sarv_op[vece]; 3348 break; 3349 case INDEX_op_and_vec: 3350 insn = VAND; 3351 break; 3352 case INDEX_op_or_vec: 3353 insn = VOR; 3354 break; 3355 case INDEX_op_xor_vec: 3356 insn = VXOR; 3357 break; 3358 case INDEX_op_andc_vec: 3359 insn = VANDC; 3360 break; 3361 case INDEX_op_not_vec: 3362 insn = VNOR; 3363 a2 = a1; 3364 break; 3365 case INDEX_op_orc_vec: 3366 insn = VORC; 3367 break; 3368 case INDEX_op_nand_vec: 3369 insn = VNAND; 3370 break; 3371 case INDEX_op_nor_vec: 3372 insn = VNOR; 3373 break; 3374 case INDEX_op_eqv_vec: 3375 insn = VEQV; 3376 break; 3377 3378 case INDEX_op_cmp_vec: 3379 switch (args[3]) { 3380 case TCG_COND_EQ: 3381 insn = eq_op[vece]; 3382 break; 3383 case TCG_COND_NE: 3384 insn = ne_op[vece]; 3385 break; 3386 case TCG_COND_GT: 3387 insn = gts_op[vece]; 3388 break; 3389 case TCG_COND_GTU: 3390 insn = gtu_op[vece]; 3391 break; 3392 default: 3393 g_assert_not_reached(); 3394 } 3395 break; 3396 3397 case INDEX_op_bitsel_vec: 3398 tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3])); 3399 return; 3400 3401 case INDEX_op_dup2_vec: 3402 assert(TCG_TARGET_REG_BITS == 32); 3403 /* With inputs a1 = xLxx, a2 = xHxx */ 3404 tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ 3405 tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ 3406 tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ 3407 return; 3408 3409 case INDEX_op_ppc_mrgh_vec: 3410 insn = mrgh_op[vece]; 3411 break; 3412 case INDEX_op_ppc_mrgl_vec: 3413 insn = mrgl_op[vece]; 3414 break; 3415 case INDEX_op_ppc_muleu_vec: 3416 insn = muleu_op[vece]; 3417 break; 3418 case INDEX_op_ppc_mulou_vec: 3419 insn = mulou_op[vece]; 3420 break; 3421 case INDEX_op_ppc_pkum_vec: 3422 insn = pkum_op[vece]; 3423 break; 3424 case INDEX_op_rotlv_vec: 3425 insn = rotl_op[vece]; 3426 break; 3427 case INDEX_op_ppc_msum_vec: 3428 tcg_debug_assert(vece == MO_16); 3429 tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])); 3430 return; 3431 3432 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3433 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3434 default: 3435 g_assert_not_reached(); 3436 } 3437 3438 tcg_debug_assert(insn != 0); 3439 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); 3440} 3441 3442static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, 3443 TCGv_vec v1, TCGArg imm, TCGOpcode opci) 3444{ 3445 TCGv_vec t1; 3446 3447 if (vece == MO_32) { 3448 /* 3449 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 3450 * So using negative numbers gets us the 4th bit easily. 3451 */ 3452 imm = sextract32(imm, 0, 5); 3453 } else { 3454 imm &= (8 << vece) - 1; 3455 } 3456 3457 /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */ 3458 t1 = tcg_constant_vec(type, MO_8, imm); 3459 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), 3460 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3461} 3462 3463static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, 3464 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 3465{ 3466 bool need_swap = false, need_inv = false; 3467 3468 tcg_debug_assert(vece <= MO_32 || have_isa_2_07); 3469 3470 switch (cond) { 3471 case TCG_COND_EQ: 3472 case TCG_COND_GT: 3473 case TCG_COND_GTU: 3474 break; 3475 case TCG_COND_NE: 3476 if (have_isa_3_00 && vece <= MO_32) { 3477 break; 3478 } 3479 /* fall through */ 3480 case TCG_COND_LE: 3481 case TCG_COND_LEU: 3482 need_inv = true; 3483 break; 3484 case TCG_COND_LT: 3485 case TCG_COND_LTU: 3486 need_swap = true; 3487 break; 3488 case TCG_COND_GE: 3489 case TCG_COND_GEU: 3490 need_swap = need_inv = true; 3491 break; 3492 default: 3493 g_assert_not_reached(); 3494 } 3495 3496 if (need_inv) { 3497 cond = tcg_invert_cond(cond); 3498 } 3499 if (need_swap) { 3500 TCGv_vec t1; 3501 t1 = v1, v1 = v2, v2 = t1; 3502 cond = tcg_swap_cond(cond); 3503 } 3504 3505 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), 3506 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); 3507 3508 if (need_inv) { 3509 tcg_gen_not_vec(vece, v0, v0); 3510 } 3511} 3512 3513static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, 3514 TCGv_vec v1, TCGv_vec v2) 3515{ 3516 TCGv_vec t1 = tcg_temp_new_vec(type); 3517 TCGv_vec t2 = tcg_temp_new_vec(type); 3518 TCGv_vec c0, c16; 3519 3520 switch (vece) { 3521 case MO_8: 3522 case MO_16: 3523 vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), 3524 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3525 vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), 3526 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3527 vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), 3528 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3529 vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), 3530 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3531 vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), 3532 tcgv_vec_arg(v0), tcgv_vec_arg(t1)); 3533 break; 3534 3535 case MO_32: 3536 tcg_debug_assert(!have_isa_2_07); 3537 /* 3538 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 3539 * So using -16 is a quick way to represent 16. 3540 */ 3541 c16 = tcg_constant_vec(type, MO_8, -16); 3542 c0 = tcg_constant_vec(type, MO_8, 0); 3543 3544 vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), 3545 tcgv_vec_arg(v2), tcgv_vec_arg(c16)); 3546 vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), 3547 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3548 vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1), 3549 tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0)); 3550 vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1), 3551 tcgv_vec_arg(t1), tcgv_vec_arg(c16)); 3552 tcg_gen_add_vec(MO_32, v0, t1, t2); 3553 break; 3554 3555 default: 3556 g_assert_not_reached(); 3557 } 3558 tcg_temp_free_vec(t1); 3559 tcg_temp_free_vec(t2); 3560} 3561 3562void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3563 TCGArg a0, ...) 3564{ 3565 va_list va; 3566 TCGv_vec v0, v1, v2, t0; 3567 TCGArg a2; 3568 3569 va_start(va, a0); 3570 v0 = temp_tcgv_vec(arg_temp(a0)); 3571 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3572 a2 = va_arg(va, TCGArg); 3573 3574 switch (opc) { 3575 case INDEX_op_shli_vec: 3576 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); 3577 break; 3578 case INDEX_op_shri_vec: 3579 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); 3580 break; 3581 case INDEX_op_sari_vec: 3582 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); 3583 break; 3584 case INDEX_op_rotli_vec: 3585 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); 3586 break; 3587 case INDEX_op_cmp_vec: 3588 v2 = temp_tcgv_vec(arg_temp(a2)); 3589 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); 3590 break; 3591 case INDEX_op_mul_vec: 3592 v2 = temp_tcgv_vec(arg_temp(a2)); 3593 expand_vec_mul(type, vece, v0, v1, v2); 3594 break; 3595 case INDEX_op_rotlv_vec: 3596 v2 = temp_tcgv_vec(arg_temp(a2)); 3597 t0 = tcg_temp_new_vec(type); 3598 tcg_gen_neg_vec(vece, t0, v2); 3599 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3600 tcg_temp_free_vec(t0); 3601 break; 3602 default: 3603 g_assert_not_reached(); 3604 } 3605 va_end(va); 3606} 3607 3608static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 3609{ 3610 switch (op) { 3611 case INDEX_op_goto_ptr: 3612 return C_O0_I1(r); 3613 3614 case INDEX_op_ld8u_i32: 3615 case INDEX_op_ld8s_i32: 3616 case INDEX_op_ld16u_i32: 3617 case INDEX_op_ld16s_i32: 3618 case INDEX_op_ld_i32: 3619 case INDEX_op_ctpop_i32: 3620 case INDEX_op_neg_i32: 3621 case INDEX_op_not_i32: 3622 case INDEX_op_ext8s_i32: 3623 case INDEX_op_ext16s_i32: 3624 case INDEX_op_bswap16_i32: 3625 case INDEX_op_bswap32_i32: 3626 case INDEX_op_extract_i32: 3627 case INDEX_op_ld8u_i64: 3628 case INDEX_op_ld8s_i64: 3629 case INDEX_op_ld16u_i64: 3630 case INDEX_op_ld16s_i64: 3631 case INDEX_op_ld32u_i64: 3632 case INDEX_op_ld32s_i64: 3633 case INDEX_op_ld_i64: 3634 case INDEX_op_ctpop_i64: 3635 case INDEX_op_neg_i64: 3636 case INDEX_op_not_i64: 3637 case INDEX_op_ext8s_i64: 3638 case INDEX_op_ext16s_i64: 3639 case INDEX_op_ext32s_i64: 3640 case INDEX_op_ext_i32_i64: 3641 case INDEX_op_extu_i32_i64: 3642 case INDEX_op_bswap16_i64: 3643 case INDEX_op_bswap32_i64: 3644 case INDEX_op_bswap64_i64: 3645 case INDEX_op_extract_i64: 3646 return C_O1_I1(r, r); 3647 3648 case INDEX_op_st8_i32: 3649 case INDEX_op_st16_i32: 3650 case INDEX_op_st_i32: 3651 case INDEX_op_st8_i64: 3652 case INDEX_op_st16_i64: 3653 case INDEX_op_st32_i64: 3654 case INDEX_op_st_i64: 3655 return C_O0_I2(r, r); 3656 3657 case INDEX_op_add_i32: 3658 case INDEX_op_and_i32: 3659 case INDEX_op_or_i32: 3660 case INDEX_op_xor_i32: 3661 case INDEX_op_andc_i32: 3662 case INDEX_op_orc_i32: 3663 case INDEX_op_eqv_i32: 3664 case INDEX_op_shl_i32: 3665 case INDEX_op_shr_i32: 3666 case INDEX_op_sar_i32: 3667 case INDEX_op_rotl_i32: 3668 case INDEX_op_rotr_i32: 3669 case INDEX_op_setcond_i32: 3670 case INDEX_op_and_i64: 3671 case INDEX_op_andc_i64: 3672 case INDEX_op_shl_i64: 3673 case INDEX_op_shr_i64: 3674 case INDEX_op_sar_i64: 3675 case INDEX_op_rotl_i64: 3676 case INDEX_op_rotr_i64: 3677 case INDEX_op_setcond_i64: 3678 return C_O1_I2(r, r, ri); 3679 3680 case INDEX_op_mul_i32: 3681 case INDEX_op_mul_i64: 3682 return C_O1_I2(r, r, rI); 3683 3684 case INDEX_op_div_i32: 3685 case INDEX_op_divu_i32: 3686 case INDEX_op_rem_i32: 3687 case INDEX_op_remu_i32: 3688 case INDEX_op_nand_i32: 3689 case INDEX_op_nor_i32: 3690 case INDEX_op_muluh_i32: 3691 case INDEX_op_mulsh_i32: 3692 case INDEX_op_orc_i64: 3693 case INDEX_op_eqv_i64: 3694 case INDEX_op_nand_i64: 3695 case INDEX_op_nor_i64: 3696 case INDEX_op_div_i64: 3697 case INDEX_op_divu_i64: 3698 case INDEX_op_rem_i64: 3699 case INDEX_op_remu_i64: 3700 case INDEX_op_mulsh_i64: 3701 case INDEX_op_muluh_i64: 3702 return C_O1_I2(r, r, r); 3703 3704 case INDEX_op_sub_i32: 3705 return C_O1_I2(r, rI, ri); 3706 case INDEX_op_add_i64: 3707 return C_O1_I2(r, r, rT); 3708 case INDEX_op_or_i64: 3709 case INDEX_op_xor_i64: 3710 return C_O1_I2(r, r, rU); 3711 case INDEX_op_sub_i64: 3712 return C_O1_I2(r, rI, rT); 3713 case INDEX_op_clz_i32: 3714 case INDEX_op_ctz_i32: 3715 case INDEX_op_clz_i64: 3716 case INDEX_op_ctz_i64: 3717 return C_O1_I2(r, r, rZW); 3718 3719 case INDEX_op_brcond_i32: 3720 case INDEX_op_brcond_i64: 3721 return C_O0_I2(r, ri); 3722 3723 case INDEX_op_movcond_i32: 3724 case INDEX_op_movcond_i64: 3725 return C_O1_I4(r, r, ri, rZ, rZ); 3726 case INDEX_op_deposit_i32: 3727 case INDEX_op_deposit_i64: 3728 return C_O1_I2(r, 0, rZ); 3729 case INDEX_op_brcond2_i32: 3730 return C_O0_I4(r, r, ri, ri); 3731 case INDEX_op_setcond2_i32: 3732 return C_O1_I4(r, r, r, ri, ri); 3733 case INDEX_op_add2_i64: 3734 case INDEX_op_add2_i32: 3735 return C_O2_I4(r, r, r, r, rI, rZM); 3736 case INDEX_op_sub2_i64: 3737 case INDEX_op_sub2_i32: 3738 return C_O2_I4(r, r, rI, rZM, r, r); 3739 3740 case INDEX_op_qemu_ld_i32: 3741 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 3742 ? C_O1_I1(r, r) 3743 : C_O1_I2(r, r, r)); 3744 3745 case INDEX_op_qemu_st_i32: 3746 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 3747 ? C_O0_I2(r, r) 3748 : C_O0_I3(r, r, r)); 3749 3750 case INDEX_op_qemu_ld_i64: 3751 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) 3752 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, r) 3753 : C_O2_I2(r, r, r, r)); 3754 3755 case INDEX_op_qemu_st_i64: 3756 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) 3757 : TARGET_LONG_BITS == 32 ? C_O0_I3(r, r, r) 3758 : C_O0_I4(r, r, r, r)); 3759 3760 case INDEX_op_add_vec: 3761 case INDEX_op_sub_vec: 3762 case INDEX_op_mul_vec: 3763 case INDEX_op_and_vec: 3764 case INDEX_op_or_vec: 3765 case INDEX_op_xor_vec: 3766 case INDEX_op_andc_vec: 3767 case INDEX_op_orc_vec: 3768 case INDEX_op_nor_vec: 3769 case INDEX_op_eqv_vec: 3770 case INDEX_op_nand_vec: 3771 case INDEX_op_cmp_vec: 3772 case INDEX_op_ssadd_vec: 3773 case INDEX_op_sssub_vec: 3774 case INDEX_op_usadd_vec: 3775 case INDEX_op_ussub_vec: 3776 case INDEX_op_smax_vec: 3777 case INDEX_op_smin_vec: 3778 case INDEX_op_umax_vec: 3779 case INDEX_op_umin_vec: 3780 case INDEX_op_shlv_vec: 3781 case INDEX_op_shrv_vec: 3782 case INDEX_op_sarv_vec: 3783 case INDEX_op_rotlv_vec: 3784 case INDEX_op_rotrv_vec: 3785 case INDEX_op_ppc_mrgh_vec: 3786 case INDEX_op_ppc_mrgl_vec: 3787 case INDEX_op_ppc_muleu_vec: 3788 case INDEX_op_ppc_mulou_vec: 3789 case INDEX_op_ppc_pkum_vec: 3790 case INDEX_op_dup2_vec: 3791 return C_O1_I2(v, v, v); 3792 3793 case INDEX_op_not_vec: 3794 case INDEX_op_neg_vec: 3795 return C_O1_I1(v, v); 3796 3797 case INDEX_op_dup_vec: 3798 return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); 3799 3800 case INDEX_op_ld_vec: 3801 case INDEX_op_dupm_vec: 3802 return C_O1_I1(v, r); 3803 3804 case INDEX_op_st_vec: 3805 return C_O0_I2(v, r); 3806 3807 case INDEX_op_bitsel_vec: 3808 case INDEX_op_ppc_msum_vec: 3809 return C_O1_I3(v, v, v, v); 3810 3811 default: 3812 g_assert_not_reached(); 3813 } 3814} 3815 3816static void tcg_target_init(TCGContext *s) 3817{ 3818 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3819 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); 3820 3821 have_isa = tcg_isa_base; 3822 if (hwcap & PPC_FEATURE_ARCH_2_06) { 3823 have_isa = tcg_isa_2_06; 3824 } 3825#ifdef PPC_FEATURE2_ARCH_2_07 3826 if (hwcap2 & PPC_FEATURE2_ARCH_2_07) { 3827 have_isa = tcg_isa_2_07; 3828 } 3829#endif 3830#ifdef PPC_FEATURE2_ARCH_3_00 3831 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { 3832 have_isa = tcg_isa_3_00; 3833 } 3834#endif 3835#ifdef PPC_FEATURE2_ARCH_3_10 3836 if (hwcap2 & PPC_FEATURE2_ARCH_3_10) { 3837 have_isa = tcg_isa_3_10; 3838 } 3839#endif 3840 3841#ifdef PPC_FEATURE2_HAS_ISEL 3842 /* Prefer explicit instruction from the kernel. */ 3843 have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0; 3844#else 3845 /* Fall back to knowing Power7 (2.06) has ISEL. */ 3846 have_isel = have_isa_2_06; 3847#endif 3848 3849 if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { 3850 have_altivec = true; 3851 /* We only care about the portion of VSX that overlaps Altivec. */ 3852 if (hwcap & PPC_FEATURE_HAS_VSX) { 3853 have_vsx = true; 3854 } 3855 } 3856 3857 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 3858 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 3859 if (have_altivec) { 3860 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3861 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3862 } 3863 3864 tcg_target_call_clobber_regs = 0; 3865 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3866 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3867 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3868 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3869 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3870 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3871 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7); 3872 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); 3873 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); 3874 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); 3875 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); 3876 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 3877 3878 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3879 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3880 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3881 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3882 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3883 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3884 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3885 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3886 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8); 3887 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9); 3888 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10); 3889 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11); 3890 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12); 3891 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13); 3892 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14); 3893 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15); 3894 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3895 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3896 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3897 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3898 3899 s->reserved_regs = 0; 3900 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ 3901 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ 3902#if defined(_CALL_SYSV) 3903 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ 3904#endif 3905#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64 3906 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ 3907#endif 3908 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 3909 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 3910 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); 3911 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); 3912 if (USE_REG_TB) { 3913 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ 3914 } 3915} 3916 3917#ifdef __ELF__ 3918typedef struct { 3919 DebugFrameCIE cie; 3920 DebugFrameFDEHeader fde; 3921 uint8_t fde_def_cfa[4]; 3922 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3]; 3923} DebugFrame; 3924 3925/* We're expecting a 2 byte uleb128 encoded value. */ 3926QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3927 3928#if TCG_TARGET_REG_BITS == 64 3929# define ELF_HOST_MACHINE EM_PPC64 3930#else 3931# define ELF_HOST_MACHINE EM_PPC 3932#endif 3933 3934static DebugFrame debug_frame = { 3935 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3936 .cie.id = -1, 3937 .cie.version = 1, 3938 .cie.code_align = 1, 3939 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */ 3940 .cie.return_column = 65, 3941 3942 /* Total FDE size does not include the "len" member. */ 3943 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset), 3944 3945 .fde_def_cfa = { 3946 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */ 3947 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3948 (FRAME_SIZE >> 7) 3949 }, 3950 .fde_reg_ofs = { 3951 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */ 3952 0x11, 65, (LR_OFFSET / -SZR) & 0x7f, 3953 } 3954}; 3955 3956void tcg_register_jit(const void *buf, size_t buf_size) 3957{ 3958 uint8_t *p = &debug_frame.fde_reg_ofs[3]; 3959 int i; 3960 3961 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) { 3962 p[0] = 0x80 + tcg_target_callee_save_regs[i]; 3963 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR; 3964 } 3965 3966 debug_frame.fde.func_start = (uintptr_t)buf; 3967 debug_frame.fde.func_len = buf_size; 3968 3969 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3970} 3971#endif /* __ELF__ */ 3972#undef VMULEUB 3973#undef VMULEUH 3974#undef VMULEUW 3975#undef VMULOUB 3976#undef VMULOUH 3977#undef VMULOUW 3978#undef VMSUMUHM 3979