1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2018 SiFive, Inc 5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 7 * Copyright (c) 2008 Fabrice Bellard 8 * 9 * Based on i386/tcg-target.c and mips/tcg-target.c 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a copy 12 * of this software and associated documentation files (the "Software"), to deal 13 * in the Software without restriction, including without limitation the rights 14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 * copies of the Software, and to permit persons to whom the Software is 16 * furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included in 19 * all copies or substantial portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 * THE SOFTWARE. 28 */ 29 30#include "../tcg-ldst.c.inc" 31#include "../tcg-pool.c.inc" 32 33#ifdef CONFIG_DEBUG_TCG 34static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 35 "zero", 36 "ra", 37 "sp", 38 "gp", 39 "tp", 40 "t0", 41 "t1", 42 "t2", 43 "s0", 44 "s1", 45 "a0", 46 "a1", 47 "a2", 48 "a3", 49 "a4", 50 "a5", 51 "a6", 52 "a7", 53 "s2", 54 "s3", 55 "s4", 56 "s5", 57 "s6", 58 "s7", 59 "s8", 60 "s9", 61 "s10", 62 "s11", 63 "t3", 64 "t4", 65 "t5", 66 "t6" 67}; 68#endif 69 70static const int tcg_target_reg_alloc_order[] = { 71 /* Call saved registers */ 72 /* TCG_REG_S0 reservered for TCG_AREG0 */ 73 TCG_REG_S1, 74 TCG_REG_S2, 75 TCG_REG_S3, 76 TCG_REG_S4, 77 TCG_REG_S5, 78 TCG_REG_S6, 79 TCG_REG_S7, 80 TCG_REG_S8, 81 TCG_REG_S9, 82 TCG_REG_S10, 83 TCG_REG_S11, 84 85 /* Call clobbered registers */ 86 TCG_REG_T0, 87 TCG_REG_T1, 88 TCG_REG_T2, 89 TCG_REG_T3, 90 TCG_REG_T4, 91 TCG_REG_T5, 92 TCG_REG_T6, 93 94 /* Argument registers */ 95 TCG_REG_A0, 96 TCG_REG_A1, 97 TCG_REG_A2, 98 TCG_REG_A3, 99 TCG_REG_A4, 100 TCG_REG_A5, 101 TCG_REG_A6, 102 TCG_REG_A7, 103}; 104 105static const int tcg_target_call_iarg_regs[] = { 106 TCG_REG_A0, 107 TCG_REG_A1, 108 TCG_REG_A2, 109 TCG_REG_A3, 110 TCG_REG_A4, 111 TCG_REG_A5, 112 TCG_REG_A6, 113 TCG_REG_A7, 114}; 115 116static const int tcg_target_call_oarg_regs[] = { 117 TCG_REG_A0, 118 TCG_REG_A1, 119}; 120 121#define TCG_CT_CONST_ZERO 0x100 122#define TCG_CT_CONST_S12 0x200 123#define TCG_CT_CONST_N12 0x400 124#define TCG_CT_CONST_M12 0x800 125 126#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 127/* 128 * For softmmu, we need to avoid conflicts with the first 5 129 * argument registers to call the helper. Some of these are 130 * also used for the tlb lookup. 131 */ 132#ifdef CONFIG_SOFTMMU 133#define SOFTMMU_RESERVE_REGS MAKE_64BIT_MASK(TCG_REG_A0, 5) 134#else 135#define SOFTMMU_RESERVE_REGS 0 136#endif 137 138 139static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 140{ 141 if (TCG_TARGET_REG_BITS == 32) { 142 return sextract32(val, pos, len); 143 } else { 144 return sextract64(val, pos, len); 145 } 146} 147 148/* test if a constant matches the constraint */ 149static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 150{ 151 if (ct & TCG_CT_CONST) { 152 return 1; 153 } 154 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 155 return 1; 156 } 157 /* 158 * Sign extended from 12 bits: [-0x800, 0x7ff]. 159 * Used for most arithmetic, as this is the isa field. 160 */ 161 if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) { 162 return 1; 163 } 164 /* 165 * Sign extended from 12 bits, negated: [-0x7ff, 0x800]. 166 * Used for subtraction, where a constant must be handled by ADDI. 167 */ 168 if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) { 169 return 1; 170 } 171 /* 172 * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff]. 173 * Used by addsub2, which may need the negative operation, 174 * and requires the modified constant to be representable. 175 */ 176 if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) { 177 return 1; 178 } 179 return 0; 180} 181 182/* 183 * RISC-V Base ISA opcodes (IM) 184 */ 185 186typedef enum { 187 OPC_ADD = 0x33, 188 OPC_ADDI = 0x13, 189 OPC_AND = 0x7033, 190 OPC_ANDI = 0x7013, 191 OPC_AUIPC = 0x17, 192 OPC_BEQ = 0x63, 193 OPC_BGE = 0x5063, 194 OPC_BGEU = 0x7063, 195 OPC_BLT = 0x4063, 196 OPC_BLTU = 0x6063, 197 OPC_BNE = 0x1063, 198 OPC_DIV = 0x2004033, 199 OPC_DIVU = 0x2005033, 200 OPC_JAL = 0x6f, 201 OPC_JALR = 0x67, 202 OPC_LB = 0x3, 203 OPC_LBU = 0x4003, 204 OPC_LD = 0x3003, 205 OPC_LH = 0x1003, 206 OPC_LHU = 0x5003, 207 OPC_LUI = 0x37, 208 OPC_LW = 0x2003, 209 OPC_LWU = 0x6003, 210 OPC_MUL = 0x2000033, 211 OPC_MULH = 0x2001033, 212 OPC_MULHSU = 0x2002033, 213 OPC_MULHU = 0x2003033, 214 OPC_OR = 0x6033, 215 OPC_ORI = 0x6013, 216 OPC_REM = 0x2006033, 217 OPC_REMU = 0x2007033, 218 OPC_SB = 0x23, 219 OPC_SD = 0x3023, 220 OPC_SH = 0x1023, 221 OPC_SLL = 0x1033, 222 OPC_SLLI = 0x1013, 223 OPC_SLT = 0x2033, 224 OPC_SLTI = 0x2013, 225 OPC_SLTIU = 0x3013, 226 OPC_SLTU = 0x3033, 227 OPC_SRA = 0x40005033, 228 OPC_SRAI = 0x40005013, 229 OPC_SRL = 0x5033, 230 OPC_SRLI = 0x5013, 231 OPC_SUB = 0x40000033, 232 OPC_SW = 0x2023, 233 OPC_XOR = 0x4033, 234 OPC_XORI = 0x4013, 235 236#if TCG_TARGET_REG_BITS == 64 237 OPC_ADDIW = 0x1b, 238 OPC_ADDW = 0x3b, 239 OPC_DIVUW = 0x200503b, 240 OPC_DIVW = 0x200403b, 241 OPC_MULW = 0x200003b, 242 OPC_REMUW = 0x200703b, 243 OPC_REMW = 0x200603b, 244 OPC_SLLIW = 0x101b, 245 OPC_SLLW = 0x103b, 246 OPC_SRAIW = 0x4000501b, 247 OPC_SRAW = 0x4000503b, 248 OPC_SRLIW = 0x501b, 249 OPC_SRLW = 0x503b, 250 OPC_SUBW = 0x4000003b, 251#else 252 /* Simplify code throughout by defining aliases for RV32. */ 253 OPC_ADDIW = OPC_ADDI, 254 OPC_ADDW = OPC_ADD, 255 OPC_DIVUW = OPC_DIVU, 256 OPC_DIVW = OPC_DIV, 257 OPC_MULW = OPC_MUL, 258 OPC_REMUW = OPC_REMU, 259 OPC_REMW = OPC_REM, 260 OPC_SLLIW = OPC_SLLI, 261 OPC_SLLW = OPC_SLL, 262 OPC_SRAIW = OPC_SRAI, 263 OPC_SRAW = OPC_SRA, 264 OPC_SRLIW = OPC_SRLI, 265 OPC_SRLW = OPC_SRL, 266 OPC_SUBW = OPC_SUB, 267#endif 268 269 OPC_FENCE = 0x0000000f, 270} RISCVInsn; 271 272/* 273 * RISC-V immediate and instruction encoders (excludes 16-bit RVC) 274 */ 275 276/* Type-R */ 277 278static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) 279{ 280 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; 281} 282 283/* Type-I */ 284 285static int32_t encode_imm12(uint32_t imm) 286{ 287 return (imm & 0xfff) << 20; 288} 289 290static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) 291{ 292 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); 293} 294 295/* Type-S */ 296 297static int32_t encode_simm12(uint32_t imm) 298{ 299 int32_t ret = 0; 300 301 ret |= (imm & 0xFE0) << 20; 302 ret |= (imm & 0x1F) << 7; 303 304 return ret; 305} 306 307static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) 308{ 309 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); 310} 311 312/* Type-SB */ 313 314static int32_t encode_sbimm12(uint32_t imm) 315{ 316 int32_t ret = 0; 317 318 ret |= (imm & 0x1000) << 19; 319 ret |= (imm & 0x7e0) << 20; 320 ret |= (imm & 0x1e) << 7; 321 ret |= (imm & 0x800) >> 4; 322 323 return ret; 324} 325 326static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) 327{ 328 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); 329} 330 331/* Type-U */ 332 333static int32_t encode_uimm20(uint32_t imm) 334{ 335 return imm & 0xfffff000; 336} 337 338static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) 339{ 340 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); 341} 342 343/* Type-UJ */ 344 345static int32_t encode_ujimm20(uint32_t imm) 346{ 347 int32_t ret = 0; 348 349 ret |= (imm & 0x0007fe) << (21 - 1); 350 ret |= (imm & 0x000800) << (20 - 11); 351 ret |= (imm & 0x0ff000) << (12 - 12); 352 ret |= (imm & 0x100000) << (31 - 20); 353 354 return ret; 355} 356 357static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) 358{ 359 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); 360} 361 362/* 363 * RISC-V instruction emitters 364 */ 365 366static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc, 367 TCGReg rd, TCGReg rs1, TCGReg rs2) 368{ 369 tcg_out32(s, encode_r(opc, rd, rs1, rs2)); 370} 371 372static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc, 373 TCGReg rd, TCGReg rs1, TCGArg imm) 374{ 375 tcg_out32(s, encode_i(opc, rd, rs1, imm)); 376} 377 378static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc, 379 TCGReg rs1, TCGReg rs2, uint32_t imm) 380{ 381 tcg_out32(s, encode_s(opc, rs1, rs2, imm)); 382} 383 384static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc, 385 TCGReg rs1, TCGReg rs2, uint32_t imm) 386{ 387 tcg_out32(s, encode_sb(opc, rs1, rs2, imm)); 388} 389 390static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc, 391 TCGReg rd, uint32_t imm) 392{ 393 tcg_out32(s, encode_u(opc, rd, imm)); 394} 395 396static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc, 397 TCGReg rd, uint32_t imm) 398{ 399 tcg_out32(s, encode_uj(opc, rd, imm)); 400} 401 402static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 403{ 404 int i; 405 for (i = 0; i < count; ++i) { 406 p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); 407 } 408} 409 410/* 411 * Relocations 412 */ 413 414static bool reloc_sbimm12(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 415{ 416 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 417 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 418 419 tcg_debug_assert((offset & 1) == 0); 420 if (offset == sextreg(offset, 0, 12)) { 421 *src_rw |= encode_sbimm12(offset); 422 return true; 423 } 424 425 return false; 426} 427 428static bool reloc_jimm20(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 429{ 430 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 431 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 432 433 tcg_debug_assert((offset & 1) == 0); 434 if (offset == sextreg(offset, 0, 20)) { 435 *src_rw |= encode_ujimm20(offset); 436 return true; 437 } 438 439 return false; 440} 441 442static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 443{ 444 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 445 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 446 int32_t lo = sextreg(offset, 0, 12); 447 int32_t hi = offset - lo; 448 449 if (offset == hi + lo) { 450 src_rw[0] |= encode_uimm20(hi); 451 src_rw[1] |= encode_imm12(lo); 452 return true; 453 } 454 455 return false; 456} 457 458static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 459 intptr_t value, intptr_t addend) 460{ 461 tcg_debug_assert(addend == 0); 462 switch (type) { 463 case R_RISCV_BRANCH: 464 return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); 465 case R_RISCV_JAL: 466 return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); 467 case R_RISCV_CALL: 468 return reloc_call(code_ptr, (tcg_insn_unit *)value); 469 default: 470 g_assert_not_reached(); 471 } 472} 473 474/* 475 * TCG intrinsics 476 */ 477 478static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 479{ 480 if (ret == arg) { 481 return true; 482 } 483 switch (type) { 484 case TCG_TYPE_I32: 485 case TCG_TYPE_I64: 486 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); 487 break; 488 default: 489 g_assert_not_reached(); 490 } 491 return true; 492} 493 494static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 495 tcg_target_long val) 496{ 497 tcg_target_long lo, hi, tmp; 498 int shift, ret; 499 500 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 501 val = (int32_t)val; 502 } 503 504 lo = sextreg(val, 0, 12); 505 if (val == lo) { 506 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo); 507 return; 508 } 509 510 hi = val - lo; 511 if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) { 512 tcg_out_opc_upper(s, OPC_LUI, rd, hi); 513 if (lo != 0) { 514 tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); 515 } 516 return; 517 } 518 519 /* We can only be here if TCG_TARGET_REG_BITS != 32 */ 520 tmp = tcg_pcrel_diff(s, (void *)val); 521 if (tmp == (int32_t)tmp) { 522 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); 523 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); 524 ret = reloc_call(s->code_ptr - 2, (const tcg_insn_unit *)val); 525 tcg_debug_assert(ret == true); 526 return; 527 } 528 529 /* Look for a single 20-bit section. */ 530 shift = ctz64(val); 531 tmp = val >> shift; 532 if (tmp == sextreg(tmp, 0, 20)) { 533 tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12); 534 if (shift > 12) { 535 tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12); 536 } else { 537 tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift); 538 } 539 return; 540 } 541 542 /* Look for a few high zero bits, with lots of bits set in the middle. */ 543 shift = clz64(val); 544 tmp = val << shift; 545 if (tmp == sextreg(tmp, 12, 20) << 12) { 546 tcg_out_opc_upper(s, OPC_LUI, rd, tmp); 547 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); 548 return; 549 } else if (tmp == sextreg(tmp, 0, 12)) { 550 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp); 551 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); 552 return; 553 } 554 555 /* Drop into the constant pool. */ 556 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0); 557 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); 558 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); 559} 560 561static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 562{ 563 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); 564} 565 566static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 567{ 568 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); 569 tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16); 570} 571 572static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 573{ 574 tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); 575 tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32); 576} 577 578static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) 579{ 580 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); 581 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); 582} 583 584static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) 585{ 586 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); 587 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16); 588} 589 590static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 591{ 592 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0); 593} 594 595static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, 596 TCGReg addr, intptr_t offset) 597{ 598 intptr_t imm12 = sextreg(offset, 0, 12); 599 600 if (offset != imm12) { 601 intptr_t diff = offset - (uintptr_t)s->code_ptr; 602 603 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 604 imm12 = sextreg(diff, 0, 12); 605 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12); 606 } else { 607 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 608 if (addr != TCG_REG_ZERO) { 609 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr); 610 } 611 } 612 addr = TCG_REG_TMP2; 613 } 614 615 switch (opc) { 616 case OPC_SB: 617 case OPC_SH: 618 case OPC_SW: 619 case OPC_SD: 620 tcg_out_opc_store(s, opc, addr, data, imm12); 621 break; 622 case OPC_LB: 623 case OPC_LBU: 624 case OPC_LH: 625 case OPC_LHU: 626 case OPC_LW: 627 case OPC_LWU: 628 case OPC_LD: 629 tcg_out_opc_imm(s, opc, data, addr, imm12); 630 break; 631 default: 632 g_assert_not_reached(); 633 } 634} 635 636static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 637 TCGReg arg1, intptr_t arg2) 638{ 639 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); 640 tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2); 641} 642 643static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 644 TCGReg arg1, intptr_t arg2) 645{ 646 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); 647 tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2); 648} 649 650static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 651 TCGReg base, intptr_t ofs) 652{ 653 if (val == 0) { 654 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 655 return true; 656 } 657 return false; 658} 659 660static void tcg_out_addsub2(TCGContext *s, 661 TCGReg rl, TCGReg rh, 662 TCGReg al, TCGReg ah, 663 TCGArg bl, TCGArg bh, 664 bool cbl, bool cbh, bool is_sub, bool is32bit) 665{ 666 const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD; 667 const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI; 668 const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB; 669 TCGReg th = TCG_REG_TMP1; 670 671 /* If we have a negative constant such that negating it would 672 make the high part zero, we can (usually) eliminate one insn. */ 673 if (cbl && cbh && bh == -1 && bl != 0) { 674 bl = -bl; 675 bh = 0; 676 is_sub = !is_sub; 677 } 678 679 /* By operating on the high part first, we get to use the final 680 carry operation to move back from the temporary. */ 681 if (!cbh) { 682 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh); 683 } else if (bh != 0 || ah == rl) { 684 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh)); 685 } else { 686 th = ah; 687 } 688 689 /* Note that tcg optimization should eliminate the bl == 0 case. */ 690 if (is_sub) { 691 if (cbl) { 692 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl); 693 tcg_out_opc_imm(s, opc_addi, rl, al, -bl); 694 } else { 695 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl); 696 tcg_out_opc_reg(s, opc_sub, rl, al, bl); 697 } 698 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0); 699 } else { 700 if (cbl) { 701 tcg_out_opc_imm(s, opc_addi, rl, al, bl); 702 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); 703 } else if (al == bl) { 704 /* 705 * If the input regs overlap, this is a simple doubling 706 * and carry-out is the input msb. This special case is 707 * required when the output reg overlaps the input, 708 * but we might as well use it always. 709 */ 710 tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0); 711 tcg_out_opc_reg(s, opc_add, rl, al, al); 712 } else { 713 tcg_out_opc_reg(s, opc_add, rl, al, bl); 714 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, 715 rl, (rl == bl ? al : bl)); 716 } 717 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0); 718 } 719} 720 721static const struct { 722 RISCVInsn op; 723 bool swap; 724} tcg_brcond_to_riscv[] = { 725 [TCG_COND_EQ] = { OPC_BEQ, false }, 726 [TCG_COND_NE] = { OPC_BNE, false }, 727 [TCG_COND_LT] = { OPC_BLT, false }, 728 [TCG_COND_GE] = { OPC_BGE, false }, 729 [TCG_COND_LE] = { OPC_BGE, true }, 730 [TCG_COND_GT] = { OPC_BLT, true }, 731 [TCG_COND_LTU] = { OPC_BLTU, false }, 732 [TCG_COND_GEU] = { OPC_BGEU, false }, 733 [TCG_COND_LEU] = { OPC_BGEU, true }, 734 [TCG_COND_GTU] = { OPC_BLTU, true } 735}; 736 737static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 738 TCGReg arg2, TCGLabel *l) 739{ 740 RISCVInsn op = tcg_brcond_to_riscv[cond].op; 741 742 tcg_debug_assert(op != 0); 743 744 if (tcg_brcond_to_riscv[cond].swap) { 745 TCGReg t = arg1; 746 arg1 = arg2; 747 arg2 = t; 748 } 749 750 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); 751 tcg_out_opc_branch(s, op, arg1, arg2, 0); 752} 753 754static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 755 TCGReg arg1, TCGReg arg2) 756{ 757 switch (cond) { 758 case TCG_COND_EQ: 759 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2); 760 tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1); 761 break; 762 case TCG_COND_NE: 763 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2); 764 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret); 765 break; 766 case TCG_COND_LT: 767 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 768 break; 769 case TCG_COND_GE: 770 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 771 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 772 break; 773 case TCG_COND_LE: 774 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 775 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 776 break; 777 case TCG_COND_GT: 778 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 779 break; 780 case TCG_COND_LTU: 781 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 782 break; 783 case TCG_COND_GEU: 784 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 785 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 786 break; 787 case TCG_COND_LEU: 788 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 789 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 790 break; 791 case TCG_COND_GTU: 792 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 793 break; 794 default: 795 g_assert_not_reached(); 796 break; 797 } 798} 799 800static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 801 TCGReg bl, TCGReg bh, TCGLabel *l) 802{ 803 /* todo */ 804 g_assert_not_reached(); 805} 806 807static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 808 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 809{ 810 /* todo */ 811 g_assert_not_reached(); 812} 813 814static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 815{ 816 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 817 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 818 int ret; 819 820 tcg_debug_assert((offset & 1) == 0); 821 if (offset == sextreg(offset, 0, 20)) { 822 /* short jump: -2097150 to 2097152 */ 823 tcg_out_opc_jump(s, OPC_JAL, link, offset); 824 } else if (TCG_TARGET_REG_BITS == 32 || offset == (int32_t)offset) { 825 /* long jump: -2147483646 to 2147483648 */ 826 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); 827 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); 828 ret = reloc_call(s->code_ptr - 2, arg); 829 tcg_debug_assert(ret == true); 830 } else if (TCG_TARGET_REG_BITS == 64) { 831 /* far jump: 64-bit */ 832 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12); 833 tcg_target_long base = (tcg_target_long)arg - imm; 834 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); 835 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); 836 } else { 837 g_assert_not_reached(); 838 } 839} 840 841static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 842 const TCGHelperInfo *info) 843{ 844 tcg_out_call_int(s, arg, false); 845} 846 847static void tcg_out_mb(TCGContext *s, TCGArg a0) 848{ 849 tcg_insn_unit insn = OPC_FENCE; 850 851 if (a0 & TCG_MO_LD_LD) { 852 insn |= 0x02200000; 853 } 854 if (a0 & TCG_MO_ST_LD) { 855 insn |= 0x01200000; 856 } 857 if (a0 & TCG_MO_LD_ST) { 858 insn |= 0x02100000; 859 } 860 if (a0 & TCG_MO_ST_ST) { 861 insn |= 0x02200000; 862 } 863 tcg_out32(s, insn); 864} 865 866/* 867 * Load/store and TLB 868 */ 869 870#if defined(CONFIG_SOFTMMU) 871/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, 872 * MemOpIdx oi, uintptr_t ra) 873 */ 874static void * const qemu_ld_helpers[MO_SSIZE + 1] = { 875 [MO_UB] = helper_ret_ldub_mmu, 876 [MO_SB] = helper_ret_ldsb_mmu, 877#if HOST_BIG_ENDIAN 878 [MO_UW] = helper_be_lduw_mmu, 879 [MO_SW] = helper_be_ldsw_mmu, 880 [MO_UL] = helper_be_ldul_mmu, 881#if TCG_TARGET_REG_BITS == 64 882 [MO_SL] = helper_be_ldsl_mmu, 883#endif 884 [MO_UQ] = helper_be_ldq_mmu, 885#else 886 [MO_UW] = helper_le_lduw_mmu, 887 [MO_SW] = helper_le_ldsw_mmu, 888 [MO_UL] = helper_le_ldul_mmu, 889#if TCG_TARGET_REG_BITS == 64 890 [MO_SL] = helper_le_ldsl_mmu, 891#endif 892 [MO_UQ] = helper_le_ldq_mmu, 893#endif 894}; 895 896/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, 897 * uintxx_t val, MemOpIdx oi, 898 * uintptr_t ra) 899 */ 900static void * const qemu_st_helpers[MO_SIZE + 1] = { 901 [MO_8] = helper_ret_stb_mmu, 902#if HOST_BIG_ENDIAN 903 [MO_16] = helper_be_stw_mmu, 904 [MO_32] = helper_be_stl_mmu, 905 [MO_64] = helper_be_stq_mmu, 906#else 907 [MO_16] = helper_le_stw_mmu, 908 [MO_32] = helper_le_stl_mmu, 909 [MO_64] = helper_le_stq_mmu, 910#endif 911}; 912 913/* We don't support oversize guests */ 914QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); 915 916/* We expect to use a 12-bit negative offset from ENV. */ 917QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 918QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); 919 920static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 921{ 922 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); 923 bool ok = reloc_jimm20(s->code_ptr - 1, target); 924 tcg_debug_assert(ok); 925} 926 927static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl, 928 TCGReg addrh, MemOpIdx oi, 929 tcg_insn_unit **label_ptr, bool is_load) 930{ 931 MemOp opc = get_memop(oi); 932 unsigned s_bits = opc & MO_SIZE; 933 unsigned a_bits = get_alignment_bits(opc); 934 tcg_target_long compare_mask; 935 int mem_index = get_mmuidx(oi); 936 int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); 937 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 938 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 939 TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; 940 941 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); 942 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); 943 944 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, 945 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 946 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 947 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 948 949 /* Load the tlb comparator and the addend. */ 950 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, 951 is_load ? offsetof(CPUTLBEntry, addr_read) 952 : offsetof(CPUTLBEntry, addr_write)); 953 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 954 offsetof(CPUTLBEntry, addend)); 955 956 /* We don't support unaligned accesses. */ 957 if (a_bits < s_bits) { 958 a_bits = s_bits; 959 } 960 /* Clear the non-page, non-alignment bits from the address. */ 961 compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1); 962 if (compare_mask == sextreg(compare_mask, 0, 12)) { 963 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask); 964 } else { 965 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); 966 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl); 967 } 968 969 /* Compare masked address with the TLB entry. */ 970 label_ptr[0] = s->code_ptr; 971 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); 972 973 /* TLB Hit - translate address using addend. */ 974 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 975 tcg_out_ext32u(s, TCG_REG_TMP0, addrl); 976 addrl = TCG_REG_TMP0; 977 } 978 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); 979 return TCG_REG_TMP0; 980} 981 982static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, 983 TCGType ext, 984 TCGReg datalo, TCGReg datahi, 985 TCGReg addrlo, TCGReg addrhi, 986 void *raddr, tcg_insn_unit **label_ptr) 987{ 988 TCGLabelQemuLdst *label = new_ldst_label(s); 989 990 label->is_ld = is_ld; 991 label->oi = oi; 992 label->type = ext; 993 label->datalo_reg = datalo; 994 label->datahi_reg = datahi; 995 label->addrlo_reg = addrlo; 996 label->addrhi_reg = addrhi; 997 label->raddr = tcg_splitwx_to_rx(raddr); 998 label->label_ptr[0] = label_ptr[0]; 999} 1000 1001static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1002{ 1003 MemOpIdx oi = l->oi; 1004 MemOp opc = get_memop(oi); 1005 TCGReg a0 = tcg_target_call_iarg_regs[0]; 1006 TCGReg a1 = tcg_target_call_iarg_regs[1]; 1007 TCGReg a2 = tcg_target_call_iarg_regs[2]; 1008 TCGReg a3 = tcg_target_call_iarg_regs[3]; 1009 1010 /* We don't support oversize guests */ 1011 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1012 g_assert_not_reached(); 1013 } 1014 1015 /* resolve label address */ 1016 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1017 return false; 1018 } 1019 1020 /* call load helper */ 1021 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); 1022 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); 1023 tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); 1024 tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); 1025 1026 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1027 tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0); 1028 1029 tcg_out_goto(s, l->raddr); 1030 return true; 1031} 1032 1033static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1034{ 1035 MemOpIdx oi = l->oi; 1036 MemOp opc = get_memop(oi); 1037 MemOp s_bits = opc & MO_SIZE; 1038 TCGReg a0 = tcg_target_call_iarg_regs[0]; 1039 TCGReg a1 = tcg_target_call_iarg_regs[1]; 1040 TCGReg a2 = tcg_target_call_iarg_regs[2]; 1041 TCGReg a3 = tcg_target_call_iarg_regs[3]; 1042 TCGReg a4 = tcg_target_call_iarg_regs[4]; 1043 1044 /* We don't support oversize guests */ 1045 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1046 g_assert_not_reached(); 1047 } 1048 1049 /* resolve label address */ 1050 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1051 return false; 1052 } 1053 1054 /* call store helper */ 1055 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); 1056 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); 1057 tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg); 1058 switch (s_bits) { 1059 case MO_8: 1060 tcg_out_ext8u(s, a2, a2); 1061 break; 1062 case MO_16: 1063 tcg_out_ext16u(s, a2, a2); 1064 break; 1065 default: 1066 break; 1067 } 1068 tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); 1069 tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); 1070 1071 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1072 1073 tcg_out_goto(s, l->raddr); 1074 return true; 1075} 1076#else 1077 1078static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addr_reg, 1079 unsigned a_bits) 1080{ 1081 unsigned a_mask = (1 << a_bits) - 1; 1082 TCGLabelQemuLdst *l = new_ldst_label(s); 1083 1084 l->is_ld = is_ld; 1085 l->addrlo_reg = addr_reg; 1086 1087 /* We are expecting a_bits to max out at 7, so we can always use andi. */ 1088 tcg_debug_assert(a_bits < 12); 1089 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); 1090 1091 l->label_ptr[0] = s->code_ptr; 1092 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); 1093 1094 l->raddr = tcg_splitwx_to_rx(s->code_ptr); 1095} 1096 1097static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 1098{ 1099 /* resolve label address */ 1100 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1101 return false; 1102 } 1103 1104 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); 1105 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); 1106 1107 /* tail call, with the return address back inline. */ 1108 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (uintptr_t)l->raddr); 1109 tcg_out_call_int(s, (const void *)(l->is_ld ? helper_unaligned_ld 1110 : helper_unaligned_st), true); 1111 return true; 1112} 1113 1114static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1115{ 1116 return tcg_out_fail_alignment(s, l); 1117} 1118 1119static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1120{ 1121 return tcg_out_fail_alignment(s, l); 1122} 1123 1124#endif /* CONFIG_SOFTMMU */ 1125 1126static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1127 TCGReg base, MemOp opc, bool is_64) 1128{ 1129 /* Byte swapping is left to middle-end expansion. */ 1130 tcg_debug_assert((opc & MO_BSWAP) == 0); 1131 1132 switch (opc & (MO_SSIZE)) { 1133 case MO_UB: 1134 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1135 break; 1136 case MO_SB: 1137 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1138 break; 1139 case MO_UW: 1140 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1141 break; 1142 case MO_SW: 1143 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1144 break; 1145 case MO_UL: 1146 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1147 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1148 break; 1149 } 1150 /* FALLTHRU */ 1151 case MO_SL: 1152 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1153 break; 1154 case MO_UQ: 1155 /* Prefer to load from offset 0 first, but allow for overlap. */ 1156 if (TCG_TARGET_REG_BITS == 64) { 1157 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1158 } else if (lo != base) { 1159 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1160 tcg_out_opc_imm(s, OPC_LW, hi, base, 4); 1161 } else { 1162 tcg_out_opc_imm(s, OPC_LW, hi, base, 4); 1163 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1164 } 1165 break; 1166 default: 1167 g_assert_not_reached(); 1168 } 1169} 1170 1171static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) 1172{ 1173 TCGReg addr_regl, addr_regh __attribute__((unused)); 1174 TCGReg data_regl, data_regh; 1175 MemOpIdx oi; 1176 MemOp opc; 1177#if defined(CONFIG_SOFTMMU) 1178 tcg_insn_unit *label_ptr[1]; 1179#else 1180 unsigned a_bits; 1181#endif 1182 TCGReg base; 1183 1184 data_regl = *args++; 1185 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1186 addr_regl = *args++; 1187 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1188 oi = *args++; 1189 opc = get_memop(oi); 1190 1191#if defined(CONFIG_SOFTMMU) 1192 base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); 1193 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1194 add_qemu_ldst_label(s, 1, oi, 1195 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1196 data_regl, data_regh, addr_regl, addr_regh, 1197 s->code_ptr, label_ptr); 1198#else 1199 a_bits = get_alignment_bits(opc); 1200 if (a_bits) { 1201 tcg_out_test_alignment(s, true, addr_regl, a_bits); 1202 } 1203 base = addr_regl; 1204 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1205 tcg_out_ext32u(s, TCG_REG_TMP0, base); 1206 base = TCG_REG_TMP0; 1207 } 1208 if (guest_base != 0) { 1209 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base); 1210 base = TCG_REG_TMP0; 1211 } 1212 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1213#endif 1214} 1215 1216static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1217 TCGReg base, MemOp opc) 1218{ 1219 /* Byte swapping is left to middle-end expansion. */ 1220 tcg_debug_assert((opc & MO_BSWAP) == 0); 1221 1222 switch (opc & (MO_SSIZE)) { 1223 case MO_8: 1224 tcg_out_opc_store(s, OPC_SB, base, lo, 0); 1225 break; 1226 case MO_16: 1227 tcg_out_opc_store(s, OPC_SH, base, lo, 0); 1228 break; 1229 case MO_32: 1230 tcg_out_opc_store(s, OPC_SW, base, lo, 0); 1231 break; 1232 case MO_64: 1233 if (TCG_TARGET_REG_BITS == 64) { 1234 tcg_out_opc_store(s, OPC_SD, base, lo, 0); 1235 } else { 1236 tcg_out_opc_store(s, OPC_SW, base, lo, 0); 1237 tcg_out_opc_store(s, OPC_SW, base, hi, 4); 1238 } 1239 break; 1240 default: 1241 g_assert_not_reached(); 1242 } 1243} 1244 1245static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) 1246{ 1247 TCGReg addr_regl, addr_regh __attribute__((unused)); 1248 TCGReg data_regl, data_regh; 1249 MemOpIdx oi; 1250 MemOp opc; 1251#if defined(CONFIG_SOFTMMU) 1252 tcg_insn_unit *label_ptr[1]; 1253#else 1254 unsigned a_bits; 1255#endif 1256 TCGReg base; 1257 1258 data_regl = *args++; 1259 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1260 addr_regl = *args++; 1261 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1262 oi = *args++; 1263 opc = get_memop(oi); 1264 1265#if defined(CONFIG_SOFTMMU) 1266 base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); 1267 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1268 add_qemu_ldst_label(s, 0, oi, 1269 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1270 data_regl, data_regh, addr_regl, addr_regh, 1271 s->code_ptr, label_ptr); 1272#else 1273 a_bits = get_alignment_bits(opc); 1274 if (a_bits) { 1275 tcg_out_test_alignment(s, false, addr_regl, a_bits); 1276 } 1277 base = addr_regl; 1278 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1279 tcg_out_ext32u(s, TCG_REG_TMP0, base); 1280 base = TCG_REG_TMP0; 1281 } 1282 if (guest_base != 0) { 1283 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base); 1284 base = TCG_REG_TMP0; 1285 } 1286 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1287#endif 1288} 1289 1290static const tcg_insn_unit *tb_ret_addr; 1291 1292static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1293 const TCGArg args[TCG_MAX_OP_ARGS], 1294 const int const_args[TCG_MAX_OP_ARGS]) 1295{ 1296 TCGArg a0 = args[0]; 1297 TCGArg a1 = args[1]; 1298 TCGArg a2 = args[2]; 1299 int c2 = const_args[2]; 1300 1301 switch (opc) { 1302 case INDEX_op_exit_tb: 1303 /* Reuse the zeroing that exists for goto_ptr. */ 1304 if (a0 == 0) { 1305 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1306 } else { 1307 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1308 tcg_out_call_int(s, tb_ret_addr, true); 1309 } 1310 break; 1311 1312 case INDEX_op_goto_tb: 1313 assert(s->tb_jmp_insn_offset == 0); 1314 /* indirect jump method */ 1315 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, 1316 (uintptr_t)(s->tb_jmp_target_addr + a0)); 1317 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1318 set_jmp_reset_offset(s, a0); 1319 break; 1320 1321 case INDEX_op_goto_ptr: 1322 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); 1323 break; 1324 1325 case INDEX_op_br: 1326 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0); 1327 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); 1328 break; 1329 1330 case INDEX_op_ld8u_i32: 1331 case INDEX_op_ld8u_i64: 1332 tcg_out_ldst(s, OPC_LBU, a0, a1, a2); 1333 break; 1334 case INDEX_op_ld8s_i32: 1335 case INDEX_op_ld8s_i64: 1336 tcg_out_ldst(s, OPC_LB, a0, a1, a2); 1337 break; 1338 case INDEX_op_ld16u_i32: 1339 case INDEX_op_ld16u_i64: 1340 tcg_out_ldst(s, OPC_LHU, a0, a1, a2); 1341 break; 1342 case INDEX_op_ld16s_i32: 1343 case INDEX_op_ld16s_i64: 1344 tcg_out_ldst(s, OPC_LH, a0, a1, a2); 1345 break; 1346 case INDEX_op_ld32u_i64: 1347 tcg_out_ldst(s, OPC_LWU, a0, a1, a2); 1348 break; 1349 case INDEX_op_ld_i32: 1350 case INDEX_op_ld32s_i64: 1351 tcg_out_ldst(s, OPC_LW, a0, a1, a2); 1352 break; 1353 case INDEX_op_ld_i64: 1354 tcg_out_ldst(s, OPC_LD, a0, a1, a2); 1355 break; 1356 1357 case INDEX_op_st8_i32: 1358 case INDEX_op_st8_i64: 1359 tcg_out_ldst(s, OPC_SB, a0, a1, a2); 1360 break; 1361 case INDEX_op_st16_i32: 1362 case INDEX_op_st16_i64: 1363 tcg_out_ldst(s, OPC_SH, a0, a1, a2); 1364 break; 1365 case INDEX_op_st_i32: 1366 case INDEX_op_st32_i64: 1367 tcg_out_ldst(s, OPC_SW, a0, a1, a2); 1368 break; 1369 case INDEX_op_st_i64: 1370 tcg_out_ldst(s, OPC_SD, a0, a1, a2); 1371 break; 1372 1373 case INDEX_op_add_i32: 1374 if (c2) { 1375 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2); 1376 } else { 1377 tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2); 1378 } 1379 break; 1380 case INDEX_op_add_i64: 1381 if (c2) { 1382 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2); 1383 } else { 1384 tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2); 1385 } 1386 break; 1387 1388 case INDEX_op_sub_i32: 1389 if (c2) { 1390 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2); 1391 } else { 1392 tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2); 1393 } 1394 break; 1395 case INDEX_op_sub_i64: 1396 if (c2) { 1397 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2); 1398 } else { 1399 tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2); 1400 } 1401 break; 1402 1403 case INDEX_op_and_i32: 1404 case INDEX_op_and_i64: 1405 if (c2) { 1406 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1407 } else { 1408 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1409 } 1410 break; 1411 1412 case INDEX_op_or_i32: 1413 case INDEX_op_or_i64: 1414 if (c2) { 1415 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1416 } else { 1417 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1418 } 1419 break; 1420 1421 case INDEX_op_xor_i32: 1422 case INDEX_op_xor_i64: 1423 if (c2) { 1424 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 1425 } else { 1426 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 1427 } 1428 break; 1429 1430 case INDEX_op_not_i32: 1431 case INDEX_op_not_i64: 1432 tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1); 1433 break; 1434 1435 case INDEX_op_neg_i32: 1436 tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1); 1437 break; 1438 case INDEX_op_neg_i64: 1439 tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1); 1440 break; 1441 1442 case INDEX_op_mul_i32: 1443 tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2); 1444 break; 1445 case INDEX_op_mul_i64: 1446 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1447 break; 1448 1449 case INDEX_op_div_i32: 1450 tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2); 1451 break; 1452 case INDEX_op_div_i64: 1453 tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2); 1454 break; 1455 1456 case INDEX_op_divu_i32: 1457 tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2); 1458 break; 1459 case INDEX_op_divu_i64: 1460 tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2); 1461 break; 1462 1463 case INDEX_op_rem_i32: 1464 tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2); 1465 break; 1466 case INDEX_op_rem_i64: 1467 tcg_out_opc_reg(s, OPC_REM, a0, a1, a2); 1468 break; 1469 1470 case INDEX_op_remu_i32: 1471 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2); 1472 break; 1473 case INDEX_op_remu_i64: 1474 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2); 1475 break; 1476 1477 case INDEX_op_shl_i32: 1478 if (c2) { 1479 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f); 1480 } else { 1481 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2); 1482 } 1483 break; 1484 case INDEX_op_shl_i64: 1485 if (c2) { 1486 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f); 1487 } else { 1488 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2); 1489 } 1490 break; 1491 1492 case INDEX_op_shr_i32: 1493 if (c2) { 1494 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f); 1495 } else { 1496 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2); 1497 } 1498 break; 1499 case INDEX_op_shr_i64: 1500 if (c2) { 1501 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f); 1502 } else { 1503 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2); 1504 } 1505 break; 1506 1507 case INDEX_op_sar_i32: 1508 if (c2) { 1509 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f); 1510 } else { 1511 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2); 1512 } 1513 break; 1514 case INDEX_op_sar_i64: 1515 if (c2) { 1516 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f); 1517 } else { 1518 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2); 1519 } 1520 break; 1521 1522 case INDEX_op_add2_i32: 1523 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1524 const_args[4], const_args[5], false, true); 1525 break; 1526 case INDEX_op_add2_i64: 1527 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1528 const_args[4], const_args[5], false, false); 1529 break; 1530 case INDEX_op_sub2_i32: 1531 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1532 const_args[4], const_args[5], true, true); 1533 break; 1534 case INDEX_op_sub2_i64: 1535 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1536 const_args[4], const_args[5], true, false); 1537 break; 1538 1539 case INDEX_op_brcond_i32: 1540 case INDEX_op_brcond_i64: 1541 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1542 break; 1543 case INDEX_op_brcond2_i32: 1544 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 1545 break; 1546 1547 case INDEX_op_setcond_i32: 1548 case INDEX_op_setcond_i64: 1549 tcg_out_setcond(s, args[3], a0, a1, a2); 1550 break; 1551 case INDEX_op_setcond2_i32: 1552 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 1553 break; 1554 1555 case INDEX_op_qemu_ld_i32: 1556 tcg_out_qemu_ld(s, args, false); 1557 break; 1558 case INDEX_op_qemu_ld_i64: 1559 tcg_out_qemu_ld(s, args, true); 1560 break; 1561 case INDEX_op_qemu_st_i32: 1562 tcg_out_qemu_st(s, args, false); 1563 break; 1564 case INDEX_op_qemu_st_i64: 1565 tcg_out_qemu_st(s, args, true); 1566 break; 1567 1568 case INDEX_op_ext8u_i32: 1569 case INDEX_op_ext8u_i64: 1570 tcg_out_ext8u(s, a0, a1); 1571 break; 1572 1573 case INDEX_op_ext16u_i32: 1574 case INDEX_op_ext16u_i64: 1575 tcg_out_ext16u(s, a0, a1); 1576 break; 1577 1578 case INDEX_op_ext32u_i64: 1579 case INDEX_op_extu_i32_i64: 1580 tcg_out_ext32u(s, a0, a1); 1581 break; 1582 1583 case INDEX_op_ext8s_i32: 1584 case INDEX_op_ext8s_i64: 1585 tcg_out_ext8s(s, a0, a1); 1586 break; 1587 1588 case INDEX_op_ext16s_i32: 1589 case INDEX_op_ext16s_i64: 1590 tcg_out_ext16s(s, a0, a1); 1591 break; 1592 1593 case INDEX_op_ext32s_i64: 1594 case INDEX_op_extrl_i64_i32: 1595 case INDEX_op_ext_i32_i64: 1596 tcg_out_ext32s(s, a0, a1); 1597 break; 1598 1599 case INDEX_op_extrh_i64_i32: 1600 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32); 1601 break; 1602 1603 case INDEX_op_mulsh_i32: 1604 case INDEX_op_mulsh_i64: 1605 tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2); 1606 break; 1607 1608 case INDEX_op_muluh_i32: 1609 case INDEX_op_muluh_i64: 1610 tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2); 1611 break; 1612 1613 case INDEX_op_mb: 1614 tcg_out_mb(s, a0); 1615 break; 1616 1617 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1618 case INDEX_op_mov_i64: 1619 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1620 default: 1621 g_assert_not_reached(); 1622 } 1623} 1624 1625static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 1626{ 1627 switch (op) { 1628 case INDEX_op_goto_ptr: 1629 return C_O0_I1(r); 1630 1631 case INDEX_op_ld8u_i32: 1632 case INDEX_op_ld8s_i32: 1633 case INDEX_op_ld16u_i32: 1634 case INDEX_op_ld16s_i32: 1635 case INDEX_op_ld_i32: 1636 case INDEX_op_not_i32: 1637 case INDEX_op_neg_i32: 1638 case INDEX_op_ld8u_i64: 1639 case INDEX_op_ld8s_i64: 1640 case INDEX_op_ld16u_i64: 1641 case INDEX_op_ld16s_i64: 1642 case INDEX_op_ld32s_i64: 1643 case INDEX_op_ld32u_i64: 1644 case INDEX_op_ld_i64: 1645 case INDEX_op_not_i64: 1646 case INDEX_op_neg_i64: 1647 case INDEX_op_ext8u_i32: 1648 case INDEX_op_ext8u_i64: 1649 case INDEX_op_ext16u_i32: 1650 case INDEX_op_ext16u_i64: 1651 case INDEX_op_ext32u_i64: 1652 case INDEX_op_extu_i32_i64: 1653 case INDEX_op_ext8s_i32: 1654 case INDEX_op_ext8s_i64: 1655 case INDEX_op_ext16s_i32: 1656 case INDEX_op_ext16s_i64: 1657 case INDEX_op_ext32s_i64: 1658 case INDEX_op_extrl_i64_i32: 1659 case INDEX_op_extrh_i64_i32: 1660 case INDEX_op_ext_i32_i64: 1661 return C_O1_I1(r, r); 1662 1663 case INDEX_op_st8_i32: 1664 case INDEX_op_st16_i32: 1665 case INDEX_op_st_i32: 1666 case INDEX_op_st8_i64: 1667 case INDEX_op_st16_i64: 1668 case INDEX_op_st32_i64: 1669 case INDEX_op_st_i64: 1670 return C_O0_I2(rZ, r); 1671 1672 case INDEX_op_add_i32: 1673 case INDEX_op_and_i32: 1674 case INDEX_op_or_i32: 1675 case INDEX_op_xor_i32: 1676 case INDEX_op_add_i64: 1677 case INDEX_op_and_i64: 1678 case INDEX_op_or_i64: 1679 case INDEX_op_xor_i64: 1680 return C_O1_I2(r, r, rI); 1681 1682 case INDEX_op_sub_i32: 1683 case INDEX_op_sub_i64: 1684 return C_O1_I2(r, rZ, rN); 1685 1686 case INDEX_op_mul_i32: 1687 case INDEX_op_mulsh_i32: 1688 case INDEX_op_muluh_i32: 1689 case INDEX_op_div_i32: 1690 case INDEX_op_divu_i32: 1691 case INDEX_op_rem_i32: 1692 case INDEX_op_remu_i32: 1693 case INDEX_op_setcond_i32: 1694 case INDEX_op_mul_i64: 1695 case INDEX_op_mulsh_i64: 1696 case INDEX_op_muluh_i64: 1697 case INDEX_op_div_i64: 1698 case INDEX_op_divu_i64: 1699 case INDEX_op_rem_i64: 1700 case INDEX_op_remu_i64: 1701 case INDEX_op_setcond_i64: 1702 return C_O1_I2(r, rZ, rZ); 1703 1704 case INDEX_op_shl_i32: 1705 case INDEX_op_shr_i32: 1706 case INDEX_op_sar_i32: 1707 case INDEX_op_shl_i64: 1708 case INDEX_op_shr_i64: 1709 case INDEX_op_sar_i64: 1710 return C_O1_I2(r, r, ri); 1711 1712 case INDEX_op_brcond_i32: 1713 case INDEX_op_brcond_i64: 1714 return C_O0_I2(rZ, rZ); 1715 1716 case INDEX_op_add2_i32: 1717 case INDEX_op_add2_i64: 1718 case INDEX_op_sub2_i32: 1719 case INDEX_op_sub2_i64: 1720 return C_O2_I4(r, r, rZ, rZ, rM, rM); 1721 1722 case INDEX_op_brcond2_i32: 1723 return C_O0_I4(rZ, rZ, rZ, rZ); 1724 1725 case INDEX_op_setcond2_i32: 1726 return C_O1_I4(r, rZ, rZ, rZ, rZ); 1727 1728 case INDEX_op_qemu_ld_i32: 1729 return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 1730 ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); 1731 case INDEX_op_qemu_st_i32: 1732 return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS 1733 ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L)); 1734 case INDEX_op_qemu_ld_i64: 1735 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) 1736 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L) 1737 : C_O2_I2(r, r, L, L)); 1738 case INDEX_op_qemu_st_i64: 1739 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L) 1740 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L) 1741 : C_O0_I4(LZ, LZ, L, L)); 1742 1743 default: 1744 g_assert_not_reached(); 1745 } 1746} 1747 1748static const int tcg_target_callee_save_regs[] = { 1749 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 1750 TCG_REG_S1, 1751 TCG_REG_S2, 1752 TCG_REG_S3, 1753 TCG_REG_S4, 1754 TCG_REG_S5, 1755 TCG_REG_S6, 1756 TCG_REG_S7, 1757 TCG_REG_S8, 1758 TCG_REG_S9, 1759 TCG_REG_S10, 1760 TCG_REG_S11, 1761 TCG_REG_RA, /* should be last for ABI compliance */ 1762}; 1763 1764/* Stack frame parameters. */ 1765#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 1766#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 1767#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 1768#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 1769 + TCG_TARGET_STACK_ALIGN - 1) \ 1770 & -TCG_TARGET_STACK_ALIGN) 1771#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 1772 1773/* We're expecting to be able to use an immediate for frame allocation. */ 1774QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 1775 1776/* Generate global QEMU prologue and epilogue code */ 1777static void tcg_target_qemu_prologue(TCGContext *s) 1778{ 1779 int i; 1780 1781 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 1782 1783 /* TB prologue */ 1784 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 1785 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 1786 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 1787 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 1788 } 1789 1790#if !defined(CONFIG_SOFTMMU) 1791 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 1792 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 1793#endif 1794 1795 /* Call generated code */ 1796 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 1797 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 1798 1799 /* Return path for goto_ptr. Set return value to 0 */ 1800 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 1801 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 1802 1803 /* TB epilogue */ 1804 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 1805 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 1806 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 1807 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 1808 } 1809 1810 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 1811 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); 1812} 1813 1814static void tcg_target_init(TCGContext *s) 1815{ 1816 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 1817 if (TCG_TARGET_REG_BITS == 64) { 1818 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 1819 } 1820 1821 tcg_target_call_clobber_regs = -1u; 1822 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 1823 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 1824 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 1825 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 1826 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 1827 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 1828 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 1829 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 1830 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 1831 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 1832 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10); 1833 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11); 1834 1835 s->reserved_regs = 0; 1836 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 1837 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 1838 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 1839 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 1840 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 1841 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); 1842 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 1843} 1844 1845typedef struct { 1846 DebugFrameHeader h; 1847 uint8_t fde_def_cfa[4]; 1848 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 1849} DebugFrame; 1850 1851#define ELF_HOST_MACHINE EM_RISCV 1852 1853static const DebugFrame debug_frame = { 1854 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 1855 .h.cie.id = -1, 1856 .h.cie.version = 1, 1857 .h.cie.code_align = 1, 1858 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 1859 .h.cie.return_column = TCG_REG_RA, 1860 1861 /* Total FDE size does not include the "len" member. */ 1862 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 1863 1864 .fde_def_cfa = { 1865 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 1866 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 1867 (FRAME_SIZE >> 7) 1868 }, 1869 .fde_reg_ofs = { 1870 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */ 1871 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */ 1872 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */ 1873 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */ 1874 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */ 1875 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */ 1876 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */ 1877 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */ 1878 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */ 1879 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */ 1880 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */ 1881 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 1882 } 1883}; 1884 1885void tcg_register_jit(const void *buf, size_t buf_size) 1886{ 1887 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 1888} 1889