1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2018 SiFive, Inc 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef RISCV_TCG_TARGET_H 26 #define RISCV_TCG_TARGET_H 27 28 #define TCG_TARGET_INSN_UNIT_SIZE 4 29 #define TCG_TARGET_NB_REGS 32 30 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) 31 32 typedef enum { 33 TCG_REG_ZERO, 34 TCG_REG_RA, 35 TCG_REG_SP, 36 TCG_REG_GP, 37 TCG_REG_TP, 38 TCG_REG_T0, 39 TCG_REG_T1, 40 TCG_REG_T2, 41 TCG_REG_S0, 42 TCG_REG_S1, 43 TCG_REG_A0, 44 TCG_REG_A1, 45 TCG_REG_A2, 46 TCG_REG_A3, 47 TCG_REG_A4, 48 TCG_REG_A5, 49 TCG_REG_A6, 50 TCG_REG_A7, 51 TCG_REG_S2, 52 TCG_REG_S3, 53 TCG_REG_S4, 54 TCG_REG_S5, 55 TCG_REG_S6, 56 TCG_REG_S7, 57 TCG_REG_S8, 58 TCG_REG_S9, 59 TCG_REG_S10, 60 TCG_REG_S11, 61 TCG_REG_T3, 62 TCG_REG_T4, 63 TCG_REG_T5, 64 TCG_REG_T6, 65 66 /* aliases */ 67 TCG_AREG0 = TCG_REG_S0, 68 TCG_GUEST_BASE_REG = TCG_REG_S1, 69 TCG_REG_TMP0 = TCG_REG_T6, 70 TCG_REG_TMP1 = TCG_REG_T5, 71 TCG_REG_TMP2 = TCG_REG_T4, 72 } TCGReg; 73 74 /* used for function call generation */ 75 #define TCG_REG_CALL_STACK TCG_REG_SP 76 #define TCG_TARGET_STACK_ALIGN 16 77 #define TCG_TARGET_CALL_STACK_OFFSET 0 78 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 79 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 80 #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 81 #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 82 83 #if defined(__riscv_arch_test) && defined(__riscv_zbb) 84 # define have_zbb true 85 #else 86 extern bool have_zbb; 87 #endif 88 89 /* optional instructions */ 90 #define TCG_TARGET_HAS_negsetcond_i32 1 91 #define TCG_TARGET_HAS_div_i32 1 92 #define TCG_TARGET_HAS_rem_i32 1 93 #define TCG_TARGET_HAS_div2_i32 0 94 #define TCG_TARGET_HAS_rot_i32 have_zbb 95 #define TCG_TARGET_HAS_deposit_i32 0 96 #define TCG_TARGET_HAS_extract_i32 0 97 #define TCG_TARGET_HAS_sextract_i32 0 98 #define TCG_TARGET_HAS_extract2_i32 0 99 #define TCG_TARGET_HAS_add2_i32 1 100 #define TCG_TARGET_HAS_sub2_i32 1 101 #define TCG_TARGET_HAS_mulu2_i32 0 102 #define TCG_TARGET_HAS_muls2_i32 0 103 #define TCG_TARGET_HAS_muluh_i32 0 104 #define TCG_TARGET_HAS_mulsh_i32 0 105 #define TCG_TARGET_HAS_ext8s_i32 1 106 #define TCG_TARGET_HAS_ext16s_i32 1 107 #define TCG_TARGET_HAS_ext8u_i32 1 108 #define TCG_TARGET_HAS_ext16u_i32 1 109 #define TCG_TARGET_HAS_bswap16_i32 have_zbb 110 #define TCG_TARGET_HAS_bswap32_i32 have_zbb 111 #define TCG_TARGET_HAS_not_i32 1 112 #define TCG_TARGET_HAS_andc_i32 have_zbb 113 #define TCG_TARGET_HAS_orc_i32 have_zbb 114 #define TCG_TARGET_HAS_eqv_i32 have_zbb 115 #define TCG_TARGET_HAS_nand_i32 0 116 #define TCG_TARGET_HAS_nor_i32 0 117 #define TCG_TARGET_HAS_clz_i32 have_zbb 118 #define TCG_TARGET_HAS_ctz_i32 have_zbb 119 #define TCG_TARGET_HAS_ctpop_i32 have_zbb 120 #define TCG_TARGET_HAS_brcond2 1 121 #define TCG_TARGET_HAS_setcond2 1 122 #define TCG_TARGET_HAS_qemu_st8_i32 0 123 124 #define TCG_TARGET_HAS_negsetcond_i64 1 125 #define TCG_TARGET_HAS_div_i64 1 126 #define TCG_TARGET_HAS_rem_i64 1 127 #define TCG_TARGET_HAS_div2_i64 0 128 #define TCG_TARGET_HAS_rot_i64 have_zbb 129 #define TCG_TARGET_HAS_deposit_i64 0 130 #define TCG_TARGET_HAS_extract_i64 0 131 #define TCG_TARGET_HAS_sextract_i64 0 132 #define TCG_TARGET_HAS_extract2_i64 0 133 #define TCG_TARGET_HAS_extr_i64_i32 1 134 #define TCG_TARGET_HAS_ext8s_i64 1 135 #define TCG_TARGET_HAS_ext16s_i64 1 136 #define TCG_TARGET_HAS_ext32s_i64 1 137 #define TCG_TARGET_HAS_ext8u_i64 1 138 #define TCG_TARGET_HAS_ext16u_i64 1 139 #define TCG_TARGET_HAS_ext32u_i64 1 140 #define TCG_TARGET_HAS_bswap16_i64 have_zbb 141 #define TCG_TARGET_HAS_bswap32_i64 have_zbb 142 #define TCG_TARGET_HAS_bswap64_i64 have_zbb 143 #define TCG_TARGET_HAS_not_i64 1 144 #define TCG_TARGET_HAS_andc_i64 have_zbb 145 #define TCG_TARGET_HAS_orc_i64 have_zbb 146 #define TCG_TARGET_HAS_eqv_i64 have_zbb 147 #define TCG_TARGET_HAS_nand_i64 0 148 #define TCG_TARGET_HAS_nor_i64 0 149 #define TCG_TARGET_HAS_clz_i64 have_zbb 150 #define TCG_TARGET_HAS_ctz_i64 have_zbb 151 #define TCG_TARGET_HAS_ctpop_i64 have_zbb 152 #define TCG_TARGET_HAS_add2_i64 1 153 #define TCG_TARGET_HAS_sub2_i64 1 154 #define TCG_TARGET_HAS_mulu2_i64 0 155 #define TCG_TARGET_HAS_muls2_i64 0 156 #define TCG_TARGET_HAS_muluh_i64 1 157 #define TCG_TARGET_HAS_mulsh_i64 1 158 159 #define TCG_TARGET_HAS_qemu_ldst_i128 0 160 161 #define TCG_TARGET_DEFAULT_MO (0) 162 163 #define TCG_TARGET_NEED_LDST_LABELS 164 #define TCG_TARGET_NEED_POOL_LABELS 165 166 #endif 167