1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 /* define it to use liveness analysis (better code) */ 26 #define USE_TCG_OPTIMIZATIONS 27 28 #include "qemu/osdep.h" 29 30 /* Define to jump the ELF file used to communicate with GDB. */ 31 #undef DEBUG_JIT 32 33 #include "qemu/error-report.h" 34 #include "qemu/cutils.h" 35 #include "qemu/host-utils.h" 36 #include "qemu/qemu-print.h" 37 #include "qemu/cacheflush.h" 38 #include "qemu/cacheinfo.h" 39 #include "qemu/timer.h" 40 41 /* Note: the long term plan is to reduce the dependencies on the QEMU 42 CPU definitions. Currently they are used for qemu_ld/st 43 instructions */ 44 #define NO_CPU_IO_DEFS 45 46 #include "exec/exec-all.h" 47 #include "tcg/tcg-op.h" 48 49 #if UINTPTR_MAX == UINT32_MAX 50 # define ELF_CLASS ELFCLASS32 51 #else 52 # define ELF_CLASS ELFCLASS64 53 #endif 54 #if HOST_BIG_ENDIAN 55 # define ELF_DATA ELFDATA2MSB 56 #else 57 # define ELF_DATA ELFDATA2LSB 58 #endif 59 60 #include "elf.h" 61 #include "exec/log.h" 62 #include "tcg/tcg-ldst.h" 63 #include "tcg/tcg-temp-internal.h" 64 #include "tcg-internal.h" 65 #include "accel/tcg/perf.h" 66 67 /* Forward declarations for functions declared in tcg-target.c.inc and 68 used here. */ 69 static void tcg_target_init(TCGContext *s); 70 static void tcg_target_qemu_prologue(TCGContext *s); 71 static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 72 intptr_t value, intptr_t addend); 73 74 /* The CIE and FDE header definitions will be common to all hosts. */ 75 typedef struct { 76 uint32_t len __attribute__((aligned((sizeof(void *))))); 77 uint32_t id; 78 uint8_t version; 79 char augmentation[1]; 80 uint8_t code_align; 81 uint8_t data_align; 82 uint8_t return_column; 83 } DebugFrameCIE; 84 85 typedef struct QEMU_PACKED { 86 uint32_t len __attribute__((aligned((sizeof(void *))))); 87 uint32_t cie_offset; 88 uintptr_t func_start; 89 uintptr_t func_len; 90 } DebugFrameFDEHeader; 91 92 typedef struct QEMU_PACKED { 93 DebugFrameCIE cie; 94 DebugFrameFDEHeader fde; 95 } DebugFrameHeader; 96 97 static void tcg_register_jit_int(const void *buf, size_t size, 98 const void *debug_frame, 99 size_t debug_frame_size) 100 __attribute__((unused)); 101 102 /* Forward declarations for functions declared and used in tcg-target.c.inc. */ 103 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, 104 intptr_t arg2); 105 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 106 static void tcg_out_movi(TCGContext *s, TCGType type, 107 TCGReg ret, tcg_target_long arg); 108 static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 109 static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); 110 static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); 111 static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg); 112 static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg); 113 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg); 114 static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); 115 static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); 116 static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg); 117 static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); 118 static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 119 __attribute__((unused)); 120 static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); 121 static void tcg_out_goto_tb(TCGContext *s, int which); 122 static void tcg_out_op(TCGContext *s, TCGOpcode opc, 123 const TCGArg args[TCG_MAX_OP_ARGS], 124 const int const_args[TCG_MAX_OP_ARGS]); 125 #if TCG_TARGET_MAYBE_vec 126 static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 127 TCGReg dst, TCGReg src); 128 static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 129 TCGReg dst, TCGReg base, intptr_t offset); 130 static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 131 TCGReg dst, int64_t arg); 132 static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 133 unsigned vecl, unsigned vece, 134 const TCGArg args[TCG_MAX_OP_ARGS], 135 const int const_args[TCG_MAX_OP_ARGS]); 136 #else 137 static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 138 TCGReg dst, TCGReg src) 139 { 140 g_assert_not_reached(); 141 } 142 static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 143 TCGReg dst, TCGReg base, intptr_t offset) 144 { 145 g_assert_not_reached(); 146 } 147 static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 148 TCGReg dst, int64_t arg) 149 { 150 g_assert_not_reached(); 151 } 152 static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 153 unsigned vecl, unsigned vece, 154 const TCGArg args[TCG_MAX_OP_ARGS], 155 const int const_args[TCG_MAX_OP_ARGS]) 156 { 157 g_assert_not_reached(); 158 } 159 #endif 160 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, 161 intptr_t arg2); 162 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 163 TCGReg base, intptr_t ofs); 164 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, 165 const TCGHelperInfo *info); 166 static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); 167 static bool tcg_target_const_match(int64_t val, TCGType type, int ct); 168 #ifdef TCG_TARGET_NEED_LDST_LABELS 169 static int tcg_out_ldst_finalize(TCGContext *s); 170 #endif 171 172 TCGContext tcg_init_ctx; 173 __thread TCGContext *tcg_ctx; 174 175 TCGContext **tcg_ctxs; 176 unsigned int tcg_cur_ctxs; 177 unsigned int tcg_max_ctxs; 178 TCGv_env cpu_env = 0; 179 const void *tcg_code_gen_epilogue; 180 uintptr_t tcg_splitwx_diff; 181 182 #ifndef CONFIG_TCG_INTERPRETER 183 tcg_prologue_fn *tcg_qemu_tb_exec; 184 #endif 185 186 static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; 187 static TCGRegSet tcg_target_call_clobber_regs; 188 189 #if TCG_TARGET_INSN_UNIT_SIZE == 1 190 static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) 191 { 192 *s->code_ptr++ = v; 193 } 194 195 static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, 196 uint8_t v) 197 { 198 *p = v; 199 } 200 #endif 201 202 #if TCG_TARGET_INSN_UNIT_SIZE <= 2 203 static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) 204 { 205 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 206 *s->code_ptr++ = v; 207 } else { 208 tcg_insn_unit *p = s->code_ptr; 209 memcpy(p, &v, sizeof(v)); 210 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE); 211 } 212 } 213 214 static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, 215 uint16_t v) 216 { 217 if (TCG_TARGET_INSN_UNIT_SIZE == 2) { 218 *p = v; 219 } else { 220 memcpy(p, &v, sizeof(v)); 221 } 222 } 223 #endif 224 225 #if TCG_TARGET_INSN_UNIT_SIZE <= 4 226 static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) 227 { 228 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 229 *s->code_ptr++ = v; 230 } else { 231 tcg_insn_unit *p = s->code_ptr; 232 memcpy(p, &v, sizeof(v)); 233 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE); 234 } 235 } 236 237 static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, 238 uint32_t v) 239 { 240 if (TCG_TARGET_INSN_UNIT_SIZE == 4) { 241 *p = v; 242 } else { 243 memcpy(p, &v, sizeof(v)); 244 } 245 } 246 #endif 247 248 #if TCG_TARGET_INSN_UNIT_SIZE <= 8 249 static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) 250 { 251 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 252 *s->code_ptr++ = v; 253 } else { 254 tcg_insn_unit *p = s->code_ptr; 255 memcpy(p, &v, sizeof(v)); 256 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE); 257 } 258 } 259 260 static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, 261 uint64_t v) 262 { 263 if (TCG_TARGET_INSN_UNIT_SIZE == 8) { 264 *p = v; 265 } else { 266 memcpy(p, &v, sizeof(v)); 267 } 268 } 269 #endif 270 271 /* label relocation processing */ 272 273 static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, 274 TCGLabel *l, intptr_t addend) 275 { 276 TCGRelocation *r = tcg_malloc(sizeof(TCGRelocation)); 277 278 r->type = type; 279 r->ptr = code_ptr; 280 r->addend = addend; 281 QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next); 282 } 283 284 static void tcg_out_label(TCGContext *s, TCGLabel *l) 285 { 286 tcg_debug_assert(!l->has_value); 287 l->has_value = 1; 288 l->u.value_ptr = tcg_splitwx_to_rx(s->code_ptr); 289 } 290 291 TCGLabel *gen_new_label(void) 292 { 293 TCGContext *s = tcg_ctx; 294 TCGLabel *l = tcg_malloc(sizeof(TCGLabel)); 295 296 memset(l, 0, sizeof(TCGLabel)); 297 l->id = s->nb_labels++; 298 QSIMPLEQ_INIT(&l->branches); 299 QSIMPLEQ_INIT(&l->relocs); 300 301 QSIMPLEQ_INSERT_TAIL(&s->labels, l, next); 302 303 return l; 304 } 305 306 static bool tcg_resolve_relocs(TCGContext *s) 307 { 308 TCGLabel *l; 309 310 QSIMPLEQ_FOREACH(l, &s->labels, next) { 311 TCGRelocation *r; 312 uintptr_t value = l->u.value; 313 314 QSIMPLEQ_FOREACH(r, &l->relocs, next) { 315 if (!patch_reloc(r->ptr, r->type, value, r->addend)) { 316 return false; 317 } 318 } 319 } 320 return true; 321 } 322 323 static void set_jmp_reset_offset(TCGContext *s, int which) 324 { 325 /* 326 * We will check for overflow at the end of the opcode loop in 327 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. 328 */ 329 s->gen_tb->jmp_reset_offset[which] = tcg_current_code_size(s); 330 } 331 332 static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContext *s, int which) 333 { 334 /* 335 * We will check for overflow at the end of the opcode loop in 336 * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. 337 */ 338 s->gen_tb->jmp_insn_offset[which] = tcg_current_code_size(s); 339 } 340 341 static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGContext *s, int which) 342 { 343 /* 344 * Return the read-execute version of the pointer, for the benefit 345 * of any pc-relative addressing mode. 346 */ 347 return (uintptr_t)tcg_splitwx_to_rx(&s->gen_tb->jmp_target_addr[which]); 348 } 349 350 /* Signal overflow, starting over with fewer guest insns. */ 351 static G_NORETURN 352 void tcg_raise_tb_overflow(TCGContext *s) 353 { 354 siglongjmp(s->jmp_trans, -2); 355 } 356 357 /** 358 * tcg_out_movext -- move and extend 359 * @s: tcg context 360 * @dst_type: integral type for destination 361 * @dst: destination register 362 * @src_type: integral type for source 363 * @src_ext: extension to apply to source 364 * @src: source register 365 * 366 * Move or extend @src into @dst, depending on @src_ext and the types. 367 */ 368 static void __attribute__((unused)) 369 tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, 370 TCGType src_type, MemOp src_ext, TCGReg src) 371 { 372 switch (src_ext) { 373 case MO_UB: 374 tcg_out_ext8u(s, dst, src); 375 break; 376 case MO_SB: 377 tcg_out_ext8s(s, dst_type, dst, src); 378 break; 379 case MO_UW: 380 tcg_out_ext16u(s, dst, src); 381 break; 382 case MO_SW: 383 tcg_out_ext16s(s, dst_type, dst, src); 384 break; 385 case MO_UL: 386 case MO_SL: 387 if (dst_type == TCG_TYPE_I32) { 388 if (src_type == TCG_TYPE_I32) { 389 tcg_out_mov(s, TCG_TYPE_I32, dst, src); 390 } else { 391 tcg_out_extrl_i64_i32(s, dst, src); 392 } 393 } else if (src_type == TCG_TYPE_I32) { 394 if (src_ext & MO_SIGN) { 395 tcg_out_exts_i32_i64(s, dst, src); 396 } else { 397 tcg_out_extu_i32_i64(s, dst, src); 398 } 399 } else { 400 if (src_ext & MO_SIGN) { 401 tcg_out_ext32s(s, dst, src); 402 } else { 403 tcg_out_ext32u(s, dst, src); 404 } 405 } 406 break; 407 case MO_UQ: 408 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 409 if (dst_type == TCG_TYPE_I32) { 410 tcg_out_extrl_i64_i32(s, dst, src); 411 } else { 412 tcg_out_mov(s, TCG_TYPE_I64, dst, src); 413 } 414 break; 415 default: 416 g_assert_not_reached(); 417 } 418 } 419 420 #define C_PFX1(P, A) P##A 421 #define C_PFX2(P, A, B) P##A##_##B 422 #define C_PFX3(P, A, B, C) P##A##_##B##_##C 423 #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D 424 #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E 425 #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F 426 427 /* Define an enumeration for the various combinations. */ 428 429 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1), 430 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2), 431 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3), 432 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4), 433 434 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1), 435 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2), 436 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3), 437 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4), 438 439 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2), 440 441 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1), 442 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2), 443 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3), 444 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4), 445 446 typedef enum { 447 #include "tcg-target-con-set.h" 448 } TCGConstraintSetIndex; 449 450 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode); 451 452 #undef C_O0_I1 453 #undef C_O0_I2 454 #undef C_O0_I3 455 #undef C_O0_I4 456 #undef C_O1_I1 457 #undef C_O1_I2 458 #undef C_O1_I3 459 #undef C_O1_I4 460 #undef C_N1_I2 461 #undef C_O2_I1 462 #undef C_O2_I2 463 #undef C_O2_I3 464 #undef C_O2_I4 465 466 /* Put all of the constraint sets into an array, indexed by the enum. */ 467 468 #define C_O0_I1(I1) { .args_ct_str = { #I1 } }, 469 #define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } }, 470 #define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } }, 471 #define C_O0_I4(I1, I2, I3, I4) { .args_ct_str = { #I1, #I2, #I3, #I4 } }, 472 473 #define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } }, 474 #define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } }, 475 #define C_O1_I3(O1, I1, I2, I3) { .args_ct_str = { #O1, #I1, #I2, #I3 } }, 476 #define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } }, 477 478 #define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } }, 479 480 #define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } }, 481 #define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2 } }, 482 #define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } }, 483 #define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } }, 484 485 static const TCGTargetOpDef constraint_sets[] = { 486 #include "tcg-target-con-set.h" 487 }; 488 489 490 #undef C_O0_I1 491 #undef C_O0_I2 492 #undef C_O0_I3 493 #undef C_O0_I4 494 #undef C_O1_I1 495 #undef C_O1_I2 496 #undef C_O1_I3 497 #undef C_O1_I4 498 #undef C_N1_I2 499 #undef C_O2_I1 500 #undef C_O2_I2 501 #undef C_O2_I3 502 #undef C_O2_I4 503 504 /* Expand the enumerator to be returned from tcg_target_op_def(). */ 505 506 #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1) 507 #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2) 508 #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3) 509 #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4) 510 511 #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1) 512 #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2) 513 #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3) 514 #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4) 515 516 #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2) 517 518 #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1) 519 #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2) 520 #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3) 521 #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) 522 523 #include "tcg-target.c.inc" 524 525 static void alloc_tcg_plugin_context(TCGContext *s) 526 { 527 #ifdef CONFIG_PLUGIN 528 s->plugin_tb = g_new0(struct qemu_plugin_tb, 1); 529 s->plugin_tb->insns = 530 g_ptr_array_new_with_free_func(qemu_plugin_insn_cleanup_fn); 531 #endif 532 } 533 534 /* 535 * All TCG threads except the parent (i.e. the one that called tcg_context_init 536 * and registered the target's TCG globals) must register with this function 537 * before initiating translation. 538 * 539 * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation 540 * of tcg_region_init() for the reasoning behind this. 541 * 542 * In softmmu each caller registers its context in tcg_ctxs[]. Note that in 543 * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial context 544 * is not used anymore for translation once this function is called. 545 * 546 * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iterates 547 * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode. 548 */ 549 #ifdef CONFIG_USER_ONLY 550 void tcg_register_thread(void) 551 { 552 tcg_ctx = &tcg_init_ctx; 553 } 554 #else 555 void tcg_register_thread(void) 556 { 557 TCGContext *s = g_malloc(sizeof(*s)); 558 unsigned int i, n; 559 560 *s = tcg_init_ctx; 561 562 /* Relink mem_base. */ 563 for (i = 0, n = tcg_init_ctx.nb_globals; i < n; ++i) { 564 if (tcg_init_ctx.temps[i].mem_base) { 565 ptrdiff_t b = tcg_init_ctx.temps[i].mem_base - tcg_init_ctx.temps; 566 tcg_debug_assert(b >= 0 && b < n); 567 s->temps[i].mem_base = &s->temps[b]; 568 } 569 } 570 571 /* Claim an entry in tcg_ctxs */ 572 n = qatomic_fetch_inc(&tcg_cur_ctxs); 573 g_assert(n < tcg_max_ctxs); 574 qatomic_set(&tcg_ctxs[n], s); 575 576 if (n > 0) { 577 alloc_tcg_plugin_context(s); 578 tcg_region_initial_alloc(s); 579 } 580 581 tcg_ctx = s; 582 } 583 #endif /* !CONFIG_USER_ONLY */ 584 585 /* pool based memory allocation */ 586 void *tcg_malloc_internal(TCGContext *s, int size) 587 { 588 TCGPool *p; 589 int pool_size; 590 591 if (size > TCG_POOL_CHUNK_SIZE) { 592 /* big malloc: insert a new pool (XXX: could optimize) */ 593 p = g_malloc(sizeof(TCGPool) + size); 594 p->size = size; 595 p->next = s->pool_first_large; 596 s->pool_first_large = p; 597 return p->data; 598 } else { 599 p = s->pool_current; 600 if (!p) { 601 p = s->pool_first; 602 if (!p) 603 goto new_pool; 604 } else { 605 if (!p->next) { 606 new_pool: 607 pool_size = TCG_POOL_CHUNK_SIZE; 608 p = g_malloc(sizeof(TCGPool) + pool_size); 609 p->size = pool_size; 610 p->next = NULL; 611 if (s->pool_current) { 612 s->pool_current->next = p; 613 } else { 614 s->pool_first = p; 615 } 616 } else { 617 p = p->next; 618 } 619 } 620 } 621 s->pool_current = p; 622 s->pool_cur = p->data + size; 623 s->pool_end = p->data + p->size; 624 return p->data; 625 } 626 627 void tcg_pool_reset(TCGContext *s) 628 { 629 TCGPool *p, *t; 630 for (p = s->pool_first_large; p; p = t) { 631 t = p->next; 632 g_free(p); 633 } 634 s->pool_first_large = NULL; 635 s->pool_cur = s->pool_end = NULL; 636 s->pool_current = NULL; 637 } 638 639 #include "exec/helper-proto.h" 640 641 static TCGHelperInfo all_helpers[] = { 642 #include "exec/helper-tcg.h" 643 }; 644 static GHashTable *helper_table; 645 646 #ifdef CONFIG_TCG_INTERPRETER 647 static ffi_type *typecode_to_ffi(int argmask) 648 { 649 /* 650 * libffi does not support __int128_t, so we have forced Int128 651 * to use the structure definition instead of the builtin type. 652 */ 653 static ffi_type *ffi_type_i128_elements[3] = { 654 &ffi_type_uint64, 655 &ffi_type_uint64, 656 NULL 657 }; 658 static ffi_type ffi_type_i128 = { 659 .size = 16, 660 .alignment = __alignof__(Int128), 661 .type = FFI_TYPE_STRUCT, 662 .elements = ffi_type_i128_elements, 663 }; 664 665 switch (argmask) { 666 case dh_typecode_void: 667 return &ffi_type_void; 668 case dh_typecode_i32: 669 return &ffi_type_uint32; 670 case dh_typecode_s32: 671 return &ffi_type_sint32; 672 case dh_typecode_i64: 673 return &ffi_type_uint64; 674 case dh_typecode_s64: 675 return &ffi_type_sint64; 676 case dh_typecode_ptr: 677 return &ffi_type_pointer; 678 case dh_typecode_i128: 679 return &ffi_type_i128; 680 } 681 g_assert_not_reached(); 682 } 683 684 static void init_ffi_layouts(void) 685 { 686 /* g_direct_hash/equal for direct comparisons on uint32_t. */ 687 GHashTable *ffi_table = g_hash_table_new(NULL, NULL); 688 689 for (int i = 0; i < ARRAY_SIZE(all_helpers); ++i) { 690 TCGHelperInfo *info = &all_helpers[i]; 691 unsigned typemask = info->typemask; 692 gpointer hash = (gpointer)(uintptr_t)typemask; 693 struct { 694 ffi_cif cif; 695 ffi_type *args[]; 696 } *ca; 697 ffi_status status; 698 int nargs; 699 ffi_cif *cif; 700 701 cif = g_hash_table_lookup(ffi_table, hash); 702 if (cif) { 703 info->cif = cif; 704 continue; 705 } 706 707 /* Ignoring the return type, find the last non-zero field. */ 708 nargs = 32 - clz32(typemask >> 3); 709 nargs = DIV_ROUND_UP(nargs, 3); 710 assert(nargs <= MAX_CALL_IARGS); 711 712 ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); 713 ca->cif.rtype = typecode_to_ffi(typemask & 7); 714 ca->cif.nargs = nargs; 715 716 if (nargs != 0) { 717 ca->cif.arg_types = ca->args; 718 for (int j = 0; j < nargs; ++j) { 719 int typecode = extract32(typemask, (j + 1) * 3, 3); 720 ca->args[j] = typecode_to_ffi(typecode); 721 } 722 } 723 724 status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, 725 ca->cif.rtype, ca->cif.arg_types); 726 assert(status == FFI_OK); 727 728 cif = &ca->cif; 729 info->cif = cif; 730 g_hash_table_insert(ffi_table, hash, (gpointer)cif); 731 } 732 733 g_hash_table_destroy(ffi_table); 734 } 735 #endif /* CONFIG_TCG_INTERPRETER */ 736 737 typedef struct TCGCumulativeArgs { 738 int arg_idx; /* tcg_gen_callN args[] */ 739 int info_in_idx; /* TCGHelperInfo in[] */ 740 int arg_slot; /* regs+stack slot */ 741 int ref_slot; /* stack slots for references */ 742 } TCGCumulativeArgs; 743 744 static void layout_arg_even(TCGCumulativeArgs *cum) 745 { 746 cum->arg_slot += cum->arg_slot & 1; 747 } 748 749 static void layout_arg_1(TCGCumulativeArgs *cum, TCGHelperInfo *info, 750 TCGCallArgumentKind kind) 751 { 752 TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; 753 754 *loc = (TCGCallArgumentLoc){ 755 .kind = kind, 756 .arg_idx = cum->arg_idx, 757 .arg_slot = cum->arg_slot, 758 }; 759 cum->info_in_idx++; 760 cum->arg_slot++; 761 } 762 763 static void layout_arg_normal_n(TCGCumulativeArgs *cum, 764 TCGHelperInfo *info, int n) 765 { 766 TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; 767 768 for (int i = 0; i < n; ++i) { 769 /* Layout all using the same arg_idx, adjusting the subindex. */ 770 loc[i] = (TCGCallArgumentLoc){ 771 .kind = TCG_CALL_ARG_NORMAL, 772 .arg_idx = cum->arg_idx, 773 .tmp_subindex = i, 774 .arg_slot = cum->arg_slot + i, 775 }; 776 } 777 cum->info_in_idx += n; 778 cum->arg_slot += n; 779 } 780 781 static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info) 782 { 783 TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; 784 int n = 128 / TCG_TARGET_REG_BITS; 785 786 /* The first subindex carries the pointer. */ 787 layout_arg_1(cum, info, TCG_CALL_ARG_BY_REF); 788 789 /* 790 * The callee is allowed to clobber memory associated with 791 * structure pass by-reference. Therefore we must make copies. 792 * Allocate space from "ref_slot", which will be adjusted to 793 * follow the parameters on the stack. 794 */ 795 loc[0].ref_slot = cum->ref_slot; 796 797 /* 798 * Subsequent words also go into the reference slot, but 799 * do not accumulate into the regular arguments. 800 */ 801 for (int i = 1; i < n; ++i) { 802 loc[i] = (TCGCallArgumentLoc){ 803 .kind = TCG_CALL_ARG_BY_REF_N, 804 .arg_idx = cum->arg_idx, 805 .tmp_subindex = i, 806 .ref_slot = cum->ref_slot + i, 807 }; 808 } 809 cum->info_in_idx += n; 810 cum->ref_slot += n; 811 } 812 813 static void init_call_layout(TCGHelperInfo *info) 814 { 815 int max_reg_slots = ARRAY_SIZE(tcg_target_call_iarg_regs); 816 int max_stk_slots = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); 817 unsigned typemask = info->typemask; 818 unsigned typecode; 819 TCGCumulativeArgs cum = { }; 820 821 /* 822 * Parse and place any function return value. 823 */ 824 typecode = typemask & 7; 825 switch (typecode) { 826 case dh_typecode_void: 827 info->nr_out = 0; 828 break; 829 case dh_typecode_i32: 830 case dh_typecode_s32: 831 case dh_typecode_ptr: 832 info->nr_out = 1; 833 info->out_kind = TCG_CALL_RET_NORMAL; 834 break; 835 case dh_typecode_i64: 836 case dh_typecode_s64: 837 info->nr_out = 64 / TCG_TARGET_REG_BITS; 838 info->out_kind = TCG_CALL_RET_NORMAL; 839 /* Query the last register now to trigger any assert early. */ 840 tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); 841 break; 842 case dh_typecode_i128: 843 info->nr_out = 128 / TCG_TARGET_REG_BITS; 844 info->out_kind = TCG_TARGET_CALL_RET_I128; 845 switch (TCG_TARGET_CALL_RET_I128) { 846 case TCG_CALL_RET_NORMAL: 847 /* Query the last register now to trigger any assert early. */ 848 tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); 849 break; 850 case TCG_CALL_RET_BY_VEC: 851 /* Query the single register now to trigger any assert early. */ 852 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0); 853 break; 854 case TCG_CALL_RET_BY_REF: 855 /* 856 * Allocate the first argument to the output. 857 * We don't need to store this anywhere, just make it 858 * unavailable for use in the input loop below. 859 */ 860 cum.arg_slot = 1; 861 break; 862 default: 863 qemu_build_not_reached(); 864 } 865 break; 866 default: 867 g_assert_not_reached(); 868 } 869 870 /* 871 * Parse and place function arguments. 872 */ 873 for (typemask >>= 3; typemask; typemask >>= 3, cum.arg_idx++) { 874 TCGCallArgumentKind kind; 875 TCGType type; 876 877 typecode = typemask & 7; 878 switch (typecode) { 879 case dh_typecode_i32: 880 case dh_typecode_s32: 881 type = TCG_TYPE_I32; 882 break; 883 case dh_typecode_i64: 884 case dh_typecode_s64: 885 type = TCG_TYPE_I64; 886 break; 887 case dh_typecode_ptr: 888 type = TCG_TYPE_PTR; 889 break; 890 case dh_typecode_i128: 891 type = TCG_TYPE_I128; 892 break; 893 default: 894 g_assert_not_reached(); 895 } 896 897 switch (type) { 898 case TCG_TYPE_I32: 899 switch (TCG_TARGET_CALL_ARG_I32) { 900 case TCG_CALL_ARG_EVEN: 901 layout_arg_even(&cum); 902 /* fall through */ 903 case TCG_CALL_ARG_NORMAL: 904 layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); 905 break; 906 case TCG_CALL_ARG_EXTEND: 907 kind = TCG_CALL_ARG_EXTEND_U + (typecode & 1); 908 layout_arg_1(&cum, info, kind); 909 break; 910 default: 911 qemu_build_not_reached(); 912 } 913 break; 914 915 case TCG_TYPE_I64: 916 switch (TCG_TARGET_CALL_ARG_I64) { 917 case TCG_CALL_ARG_EVEN: 918 layout_arg_even(&cum); 919 /* fall through */ 920 case TCG_CALL_ARG_NORMAL: 921 if (TCG_TARGET_REG_BITS == 32) { 922 layout_arg_normal_n(&cum, info, 2); 923 } else { 924 layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); 925 } 926 break; 927 default: 928 qemu_build_not_reached(); 929 } 930 break; 931 932 case TCG_TYPE_I128: 933 switch (TCG_TARGET_CALL_ARG_I128) { 934 case TCG_CALL_ARG_EVEN: 935 layout_arg_even(&cum); 936 /* fall through */ 937 case TCG_CALL_ARG_NORMAL: 938 layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); 939 break; 940 case TCG_CALL_ARG_BY_REF: 941 layout_arg_by_ref(&cum, info); 942 break; 943 default: 944 qemu_build_not_reached(); 945 } 946 break; 947 948 default: 949 g_assert_not_reached(); 950 } 951 } 952 info->nr_in = cum.info_in_idx; 953 954 /* Validate that we didn't overrun the input array. */ 955 assert(cum.info_in_idx <= ARRAY_SIZE(info->in)); 956 /* Validate the backend has enough argument space. */ 957 assert(cum.arg_slot <= max_reg_slots + max_stk_slots); 958 959 /* 960 * Relocate the "ref_slot" area to the end of the parameters. 961 * Minimizing this stack offset helps code size for x86, 962 * which has a signed 8-bit offset encoding. 963 */ 964 if (cum.ref_slot != 0) { 965 int ref_base = 0; 966 967 if (cum.arg_slot > max_reg_slots) { 968 int align = __alignof(Int128) / sizeof(tcg_target_long); 969 970 ref_base = cum.arg_slot - max_reg_slots; 971 if (align > 1) { 972 ref_base = ROUND_UP(ref_base, align); 973 } 974 } 975 assert(ref_base + cum.ref_slot <= max_stk_slots); 976 977 if (ref_base != 0) { 978 for (int i = cum.info_in_idx - 1; i >= 0; --i) { 979 TCGCallArgumentLoc *loc = &info->in[i]; 980 switch (loc->kind) { 981 case TCG_CALL_ARG_BY_REF: 982 case TCG_CALL_ARG_BY_REF_N: 983 loc->ref_slot += ref_base; 984 break; 985 default: 986 break; 987 } 988 } 989 } 990 } 991 } 992 993 static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; 994 static void process_op_defs(TCGContext *s); 995 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 996 TCGReg reg, const char *name); 997 998 static void tcg_context_init(unsigned max_cpus) 999 { 1000 TCGContext *s = &tcg_init_ctx; 1001 int op, total_args, n, i; 1002 TCGOpDef *def; 1003 TCGArgConstraint *args_ct; 1004 TCGTemp *ts; 1005 1006 memset(s, 0, sizeof(*s)); 1007 s->nb_globals = 0; 1008 1009 /* Count total number of arguments and allocate the corresponding 1010 space */ 1011 total_args = 0; 1012 for(op = 0; op < NB_OPS; op++) { 1013 def = &tcg_op_defs[op]; 1014 n = def->nb_iargs + def->nb_oargs; 1015 total_args += n; 1016 } 1017 1018 args_ct = g_new0(TCGArgConstraint, total_args); 1019 1020 for(op = 0; op < NB_OPS; op++) { 1021 def = &tcg_op_defs[op]; 1022 def->args_ct = args_ct; 1023 n = def->nb_iargs + def->nb_oargs; 1024 args_ct += n; 1025 } 1026 1027 /* Register helpers. */ 1028 /* Use g_direct_hash/equal for direct pointer comparisons on func. */ 1029 helper_table = g_hash_table_new(NULL, NULL); 1030 1031 for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { 1032 init_call_layout(&all_helpers[i]); 1033 g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, 1034 (gpointer)&all_helpers[i]); 1035 } 1036 1037 #ifdef CONFIG_TCG_INTERPRETER 1038 init_ffi_layouts(); 1039 #endif 1040 1041 tcg_target_init(s); 1042 process_op_defs(s); 1043 1044 /* Reverse the order of the saved registers, assuming they're all at 1045 the start of tcg_target_reg_alloc_order. */ 1046 for (n = 0; n < ARRAY_SIZE(tcg_target_reg_alloc_order); ++n) { 1047 int r = tcg_target_reg_alloc_order[n]; 1048 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, r)) { 1049 break; 1050 } 1051 } 1052 for (i = 0; i < n; ++i) { 1053 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[n - 1 - i]; 1054 } 1055 for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { 1056 indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i]; 1057 } 1058 1059 alloc_tcg_plugin_context(s); 1060 1061 tcg_ctx = s; 1062 /* 1063 * In user-mode we simply share the init context among threads, since we 1064 * use a single region. See the documentation tcg_region_init() for the 1065 * reasoning behind this. 1066 * In softmmu we will have at most max_cpus TCG threads. 1067 */ 1068 #ifdef CONFIG_USER_ONLY 1069 tcg_ctxs = &tcg_ctx; 1070 tcg_cur_ctxs = 1; 1071 tcg_max_ctxs = 1; 1072 #else 1073 tcg_max_ctxs = max_cpus; 1074 tcg_ctxs = g_new0(TCGContext *, max_cpus); 1075 #endif 1076 1077 tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); 1078 ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); 1079 cpu_env = temp_tcgv_ptr(ts); 1080 } 1081 1082 void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus) 1083 { 1084 tcg_context_init(max_cpus); 1085 tcg_region_init(tb_size, splitwx, max_cpus); 1086 } 1087 1088 /* 1089 * Allocate TBs right before their corresponding translated code, making 1090 * sure that TBs and code are on different cache lines. 1091 */ 1092 TranslationBlock *tcg_tb_alloc(TCGContext *s) 1093 { 1094 uintptr_t align = qemu_icache_linesize; 1095 TranslationBlock *tb; 1096 void *next; 1097 1098 retry: 1099 tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); 1100 next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); 1101 1102 if (unlikely(next > s->code_gen_highwater)) { 1103 if (tcg_region_alloc(s)) { 1104 return NULL; 1105 } 1106 goto retry; 1107 } 1108 qatomic_set(&s->code_gen_ptr, next); 1109 s->data_gen_ptr = NULL; 1110 return tb; 1111 } 1112 1113 void tcg_prologue_init(TCGContext *s) 1114 { 1115 size_t prologue_size; 1116 1117 s->code_ptr = s->code_gen_ptr; 1118 s->code_buf = s->code_gen_ptr; 1119 s->data_gen_ptr = NULL; 1120 1121 #ifndef CONFIG_TCG_INTERPRETER 1122 tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(s->code_ptr); 1123 #endif 1124 1125 #ifdef TCG_TARGET_NEED_POOL_LABELS 1126 s->pool_labels = NULL; 1127 #endif 1128 1129 qemu_thread_jit_write(); 1130 /* Generate the prologue. */ 1131 tcg_target_qemu_prologue(s); 1132 1133 #ifdef TCG_TARGET_NEED_POOL_LABELS 1134 /* Allow the prologue to put e.g. guest_base into a pool entry. */ 1135 { 1136 int result = tcg_out_pool_finalize(s); 1137 tcg_debug_assert(result == 0); 1138 } 1139 #endif 1140 1141 prologue_size = tcg_current_code_size(s); 1142 perf_report_prologue(s->code_gen_ptr, prologue_size); 1143 1144 #ifndef CONFIG_TCG_INTERPRETER 1145 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), 1146 (uintptr_t)s->code_buf, prologue_size); 1147 #endif 1148 1149 #ifdef DEBUG_DISAS 1150 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { 1151 FILE *logfile = qemu_log_trylock(); 1152 if (logfile) { 1153 fprintf(logfile, "PROLOGUE: [size=%zu]\n", prologue_size); 1154 if (s->data_gen_ptr) { 1155 size_t code_size = s->data_gen_ptr - s->code_gen_ptr; 1156 size_t data_size = prologue_size - code_size; 1157 size_t i; 1158 1159 disas(logfile, s->code_gen_ptr, code_size); 1160 1161 for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { 1162 if (sizeof(tcg_target_ulong) == 8) { 1163 fprintf(logfile, 1164 "0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", 1165 (uintptr_t)s->data_gen_ptr + i, 1166 *(uint64_t *)(s->data_gen_ptr + i)); 1167 } else { 1168 fprintf(logfile, 1169 "0x%08" PRIxPTR ": .long 0x%08x\n", 1170 (uintptr_t)s->data_gen_ptr + i, 1171 *(uint32_t *)(s->data_gen_ptr + i)); 1172 } 1173 } 1174 } else { 1175 disas(logfile, s->code_gen_ptr, prologue_size); 1176 } 1177 fprintf(logfile, "\n"); 1178 qemu_log_unlock(logfile); 1179 } 1180 } 1181 #endif 1182 1183 #ifndef CONFIG_TCG_INTERPRETER 1184 /* 1185 * Assert that goto_ptr is implemented completely, setting an epilogue. 1186 * For tci, we use NULL as the signal to return from the interpreter, 1187 * so skip this check. 1188 */ 1189 tcg_debug_assert(tcg_code_gen_epilogue != NULL); 1190 #endif 1191 1192 tcg_region_prologue_set(s); 1193 } 1194 1195 void tcg_func_start(TCGContext *s) 1196 { 1197 tcg_pool_reset(s); 1198 s->nb_temps = s->nb_globals; 1199 1200 /* No temps have been previously allocated for size or locality. */ 1201 memset(s->free_temps, 0, sizeof(s->free_temps)); 1202 1203 /* No constant temps have been previously allocated. */ 1204 for (int i = 0; i < TCG_TYPE_COUNT; ++i) { 1205 if (s->const_table[i]) { 1206 g_hash_table_remove_all(s->const_table[i]); 1207 } 1208 } 1209 1210 s->nb_ops = 0; 1211 s->nb_labels = 0; 1212 s->current_frame_offset = s->frame_start; 1213 1214 #ifdef CONFIG_DEBUG_TCG 1215 s->goto_tb_issue_mask = 0; 1216 #endif 1217 1218 QTAILQ_INIT(&s->ops); 1219 QTAILQ_INIT(&s->free_ops); 1220 QSIMPLEQ_INIT(&s->labels); 1221 } 1222 1223 static TCGTemp *tcg_temp_alloc(TCGContext *s) 1224 { 1225 int n = s->nb_temps++; 1226 1227 if (n >= TCG_MAX_TEMPS) { 1228 tcg_raise_tb_overflow(s); 1229 } 1230 return memset(&s->temps[n], 0, sizeof(TCGTemp)); 1231 } 1232 1233 static TCGTemp *tcg_global_alloc(TCGContext *s) 1234 { 1235 TCGTemp *ts; 1236 1237 tcg_debug_assert(s->nb_globals == s->nb_temps); 1238 tcg_debug_assert(s->nb_globals < TCG_MAX_TEMPS); 1239 s->nb_globals++; 1240 ts = tcg_temp_alloc(s); 1241 ts->kind = TEMP_GLOBAL; 1242 1243 return ts; 1244 } 1245 1246 static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, 1247 TCGReg reg, const char *name) 1248 { 1249 TCGTemp *ts; 1250 1251 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1252 1253 ts = tcg_global_alloc(s); 1254 ts->base_type = type; 1255 ts->type = type; 1256 ts->kind = TEMP_FIXED; 1257 ts->reg = reg; 1258 ts->name = name; 1259 tcg_regset_set_reg(s->reserved_regs, reg); 1260 1261 return ts; 1262 } 1263 1264 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) 1265 { 1266 s->frame_start = start; 1267 s->frame_end = start + size; 1268 s->frame_temp 1269 = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); 1270 } 1271 1272 TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, 1273 intptr_t offset, const char *name) 1274 { 1275 TCGContext *s = tcg_ctx; 1276 TCGTemp *base_ts = tcgv_ptr_temp(base); 1277 TCGTemp *ts = tcg_global_alloc(s); 1278 int indirect_reg = 0; 1279 1280 switch (base_ts->kind) { 1281 case TEMP_FIXED: 1282 break; 1283 case TEMP_GLOBAL: 1284 /* We do not support double-indirect registers. */ 1285 tcg_debug_assert(!base_ts->indirect_reg); 1286 base_ts->indirect_base = 1; 1287 s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 1288 ? 2 : 1); 1289 indirect_reg = 1; 1290 break; 1291 default: 1292 g_assert_not_reached(); 1293 } 1294 1295 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 1296 TCGTemp *ts2 = tcg_global_alloc(s); 1297 char buf[64]; 1298 1299 ts->base_type = TCG_TYPE_I64; 1300 ts->type = TCG_TYPE_I32; 1301 ts->indirect_reg = indirect_reg; 1302 ts->mem_allocated = 1; 1303 ts->mem_base = base_ts; 1304 ts->mem_offset = offset; 1305 pstrcpy(buf, sizeof(buf), name); 1306 pstrcat(buf, sizeof(buf), "_0"); 1307 ts->name = strdup(buf); 1308 1309 tcg_debug_assert(ts2 == ts + 1); 1310 ts2->base_type = TCG_TYPE_I64; 1311 ts2->type = TCG_TYPE_I32; 1312 ts2->indirect_reg = indirect_reg; 1313 ts2->mem_allocated = 1; 1314 ts2->mem_base = base_ts; 1315 ts2->mem_offset = offset + 4; 1316 ts2->temp_subindex = 1; 1317 pstrcpy(buf, sizeof(buf), name); 1318 pstrcat(buf, sizeof(buf), "_1"); 1319 ts2->name = strdup(buf); 1320 } else { 1321 ts->base_type = type; 1322 ts->type = type; 1323 ts->indirect_reg = indirect_reg; 1324 ts->mem_allocated = 1; 1325 ts->mem_base = base_ts; 1326 ts->mem_offset = offset; 1327 ts->name = name; 1328 } 1329 return ts; 1330 } 1331 1332 TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind) 1333 { 1334 TCGContext *s = tcg_ctx; 1335 TCGTemp *ts; 1336 int n; 1337 1338 if (kind == TEMP_EBB) { 1339 int idx = find_first_bit(s->free_temps[type].l, TCG_MAX_TEMPS); 1340 1341 if (idx < TCG_MAX_TEMPS) { 1342 /* There is already an available temp with the right type. */ 1343 clear_bit(idx, s->free_temps[type].l); 1344 1345 ts = &s->temps[idx]; 1346 ts->temp_allocated = 1; 1347 tcg_debug_assert(ts->base_type == type); 1348 tcg_debug_assert(ts->kind == kind); 1349 return ts; 1350 } 1351 } else { 1352 tcg_debug_assert(kind == TEMP_TB); 1353 } 1354 1355 switch (type) { 1356 case TCG_TYPE_I32: 1357 case TCG_TYPE_V64: 1358 case TCG_TYPE_V128: 1359 case TCG_TYPE_V256: 1360 n = 1; 1361 break; 1362 case TCG_TYPE_I64: 1363 n = 64 / TCG_TARGET_REG_BITS; 1364 break; 1365 case TCG_TYPE_I128: 1366 n = 128 / TCG_TARGET_REG_BITS; 1367 break; 1368 default: 1369 g_assert_not_reached(); 1370 } 1371 1372 ts = tcg_temp_alloc(s); 1373 ts->base_type = type; 1374 ts->temp_allocated = 1; 1375 ts->kind = kind; 1376 1377 if (n == 1) { 1378 ts->type = type; 1379 } else { 1380 ts->type = TCG_TYPE_REG; 1381 1382 for (int i = 1; i < n; ++i) { 1383 TCGTemp *ts2 = tcg_temp_alloc(s); 1384 1385 tcg_debug_assert(ts2 == ts + i); 1386 ts2->base_type = type; 1387 ts2->type = TCG_TYPE_REG; 1388 ts2->temp_allocated = 1; 1389 ts2->temp_subindex = i; 1390 ts2->kind = kind; 1391 } 1392 } 1393 return ts; 1394 } 1395 1396 TCGv_vec tcg_temp_new_vec(TCGType type) 1397 { 1398 TCGTemp *t; 1399 1400 #ifdef CONFIG_DEBUG_TCG 1401 switch (type) { 1402 case TCG_TYPE_V64: 1403 assert(TCG_TARGET_HAS_v64); 1404 break; 1405 case TCG_TYPE_V128: 1406 assert(TCG_TARGET_HAS_v128); 1407 break; 1408 case TCG_TYPE_V256: 1409 assert(TCG_TARGET_HAS_v256); 1410 break; 1411 default: 1412 g_assert_not_reached(); 1413 } 1414 #endif 1415 1416 t = tcg_temp_new_internal(type, TEMP_EBB); 1417 return temp_tcgv_vec(t); 1418 } 1419 1420 /* Create a new temp of the same type as an existing temp. */ 1421 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) 1422 { 1423 TCGTemp *t = tcgv_vec_temp(match); 1424 1425 tcg_debug_assert(t->temp_allocated != 0); 1426 1427 t = tcg_temp_new_internal(t->base_type, TEMP_EBB); 1428 return temp_tcgv_vec(t); 1429 } 1430 1431 void tcg_temp_free_internal(TCGTemp *ts) 1432 { 1433 TCGContext *s = tcg_ctx; 1434 1435 switch (ts->kind) { 1436 case TEMP_CONST: 1437 case TEMP_TB: 1438 /* Silently ignore free. */ 1439 break; 1440 case TEMP_EBB: 1441 tcg_debug_assert(ts->temp_allocated != 0); 1442 ts->temp_allocated = 0; 1443 set_bit(temp_idx(ts), s->free_temps[ts->base_type].l); 1444 break; 1445 default: 1446 /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */ 1447 g_assert_not_reached(); 1448 } 1449 } 1450 1451 TCGTemp *tcg_constant_internal(TCGType type, int64_t val) 1452 { 1453 TCGContext *s = tcg_ctx; 1454 GHashTable *h = s->const_table[type]; 1455 TCGTemp *ts; 1456 1457 if (h == NULL) { 1458 h = g_hash_table_new(g_int64_hash, g_int64_equal); 1459 s->const_table[type] = h; 1460 } 1461 1462 ts = g_hash_table_lookup(h, &val); 1463 if (ts == NULL) { 1464 int64_t *val_ptr; 1465 1466 ts = tcg_temp_alloc(s); 1467 1468 if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { 1469 TCGTemp *ts2 = tcg_temp_alloc(s); 1470 1471 tcg_debug_assert(ts2 == ts + 1); 1472 1473 ts->base_type = TCG_TYPE_I64; 1474 ts->type = TCG_TYPE_I32; 1475 ts->kind = TEMP_CONST; 1476 ts->temp_allocated = 1; 1477 1478 ts2->base_type = TCG_TYPE_I64; 1479 ts2->type = TCG_TYPE_I32; 1480 ts2->kind = TEMP_CONST; 1481 ts2->temp_allocated = 1; 1482 ts2->temp_subindex = 1; 1483 1484 /* 1485 * Retain the full value of the 64-bit constant in the low 1486 * part, so that the hash table works. Actual uses will 1487 * truncate the value to the low part. 1488 */ 1489 ts[HOST_BIG_ENDIAN].val = val; 1490 ts[!HOST_BIG_ENDIAN].val = val >> 32; 1491 val_ptr = &ts[HOST_BIG_ENDIAN].val; 1492 } else { 1493 ts->base_type = type; 1494 ts->type = type; 1495 ts->kind = TEMP_CONST; 1496 ts->temp_allocated = 1; 1497 ts->val = val; 1498 val_ptr = &ts->val; 1499 } 1500 g_hash_table_insert(h, val_ptr, ts); 1501 } 1502 1503 return ts; 1504 } 1505 1506 TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) 1507 { 1508 val = dup_const(vece, val); 1509 return temp_tcgv_vec(tcg_constant_internal(type, val)); 1510 } 1511 1512 TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val) 1513 { 1514 TCGTemp *t = tcgv_vec_temp(match); 1515 1516 tcg_debug_assert(t->temp_allocated != 0); 1517 return tcg_constant_vec(t->base_type, vece, val); 1518 } 1519 1520 /* Return true if OP may appear in the opcode stream. 1521 Test the runtime variable that controls each opcode. */ 1522 bool tcg_op_supported(TCGOpcode op) 1523 { 1524 const bool have_vec 1525 = TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256; 1526 1527 switch (op) { 1528 case INDEX_op_discard: 1529 case INDEX_op_set_label: 1530 case INDEX_op_call: 1531 case INDEX_op_br: 1532 case INDEX_op_mb: 1533 case INDEX_op_insn_start: 1534 case INDEX_op_exit_tb: 1535 case INDEX_op_goto_tb: 1536 case INDEX_op_goto_ptr: 1537 case INDEX_op_qemu_ld_i32: 1538 case INDEX_op_qemu_st_i32: 1539 case INDEX_op_qemu_ld_i64: 1540 case INDEX_op_qemu_st_i64: 1541 return true; 1542 1543 case INDEX_op_qemu_st8_i32: 1544 return TCG_TARGET_HAS_qemu_st8_i32; 1545 1546 case INDEX_op_mov_i32: 1547 case INDEX_op_setcond_i32: 1548 case INDEX_op_brcond_i32: 1549 case INDEX_op_ld8u_i32: 1550 case INDEX_op_ld8s_i32: 1551 case INDEX_op_ld16u_i32: 1552 case INDEX_op_ld16s_i32: 1553 case INDEX_op_ld_i32: 1554 case INDEX_op_st8_i32: 1555 case INDEX_op_st16_i32: 1556 case INDEX_op_st_i32: 1557 case INDEX_op_add_i32: 1558 case INDEX_op_sub_i32: 1559 case INDEX_op_mul_i32: 1560 case INDEX_op_and_i32: 1561 case INDEX_op_or_i32: 1562 case INDEX_op_xor_i32: 1563 case INDEX_op_shl_i32: 1564 case INDEX_op_shr_i32: 1565 case INDEX_op_sar_i32: 1566 return true; 1567 1568 case INDEX_op_movcond_i32: 1569 return TCG_TARGET_HAS_movcond_i32; 1570 case INDEX_op_div_i32: 1571 case INDEX_op_divu_i32: 1572 return TCG_TARGET_HAS_div_i32; 1573 case INDEX_op_rem_i32: 1574 case INDEX_op_remu_i32: 1575 return TCG_TARGET_HAS_rem_i32; 1576 case INDEX_op_div2_i32: 1577 case INDEX_op_divu2_i32: 1578 return TCG_TARGET_HAS_div2_i32; 1579 case INDEX_op_rotl_i32: 1580 case INDEX_op_rotr_i32: 1581 return TCG_TARGET_HAS_rot_i32; 1582 case INDEX_op_deposit_i32: 1583 return TCG_TARGET_HAS_deposit_i32; 1584 case INDEX_op_extract_i32: 1585 return TCG_TARGET_HAS_extract_i32; 1586 case INDEX_op_sextract_i32: 1587 return TCG_TARGET_HAS_sextract_i32; 1588 case INDEX_op_extract2_i32: 1589 return TCG_TARGET_HAS_extract2_i32; 1590 case INDEX_op_add2_i32: 1591 return TCG_TARGET_HAS_add2_i32; 1592 case INDEX_op_sub2_i32: 1593 return TCG_TARGET_HAS_sub2_i32; 1594 case INDEX_op_mulu2_i32: 1595 return TCG_TARGET_HAS_mulu2_i32; 1596 case INDEX_op_muls2_i32: 1597 return TCG_TARGET_HAS_muls2_i32; 1598 case INDEX_op_muluh_i32: 1599 return TCG_TARGET_HAS_muluh_i32; 1600 case INDEX_op_mulsh_i32: 1601 return TCG_TARGET_HAS_mulsh_i32; 1602 case INDEX_op_ext8s_i32: 1603 return TCG_TARGET_HAS_ext8s_i32; 1604 case INDEX_op_ext16s_i32: 1605 return TCG_TARGET_HAS_ext16s_i32; 1606 case INDEX_op_ext8u_i32: 1607 return TCG_TARGET_HAS_ext8u_i32; 1608 case INDEX_op_ext16u_i32: 1609 return TCG_TARGET_HAS_ext16u_i32; 1610 case INDEX_op_bswap16_i32: 1611 return TCG_TARGET_HAS_bswap16_i32; 1612 case INDEX_op_bswap32_i32: 1613 return TCG_TARGET_HAS_bswap32_i32; 1614 case INDEX_op_not_i32: 1615 return TCG_TARGET_HAS_not_i32; 1616 case INDEX_op_neg_i32: 1617 return TCG_TARGET_HAS_neg_i32; 1618 case INDEX_op_andc_i32: 1619 return TCG_TARGET_HAS_andc_i32; 1620 case INDEX_op_orc_i32: 1621 return TCG_TARGET_HAS_orc_i32; 1622 case INDEX_op_eqv_i32: 1623 return TCG_TARGET_HAS_eqv_i32; 1624 case INDEX_op_nand_i32: 1625 return TCG_TARGET_HAS_nand_i32; 1626 case INDEX_op_nor_i32: 1627 return TCG_TARGET_HAS_nor_i32; 1628 case INDEX_op_clz_i32: 1629 return TCG_TARGET_HAS_clz_i32; 1630 case INDEX_op_ctz_i32: 1631 return TCG_TARGET_HAS_ctz_i32; 1632 case INDEX_op_ctpop_i32: 1633 return TCG_TARGET_HAS_ctpop_i32; 1634 1635 case INDEX_op_brcond2_i32: 1636 case INDEX_op_setcond2_i32: 1637 return TCG_TARGET_REG_BITS == 32; 1638 1639 case INDEX_op_mov_i64: 1640 case INDEX_op_setcond_i64: 1641 case INDEX_op_brcond_i64: 1642 case INDEX_op_ld8u_i64: 1643 case INDEX_op_ld8s_i64: 1644 case INDEX_op_ld16u_i64: 1645 case INDEX_op_ld16s_i64: 1646 case INDEX_op_ld32u_i64: 1647 case INDEX_op_ld32s_i64: 1648 case INDEX_op_ld_i64: 1649 case INDEX_op_st8_i64: 1650 case INDEX_op_st16_i64: 1651 case INDEX_op_st32_i64: 1652 case INDEX_op_st_i64: 1653 case INDEX_op_add_i64: 1654 case INDEX_op_sub_i64: 1655 case INDEX_op_mul_i64: 1656 case INDEX_op_and_i64: 1657 case INDEX_op_or_i64: 1658 case INDEX_op_xor_i64: 1659 case INDEX_op_shl_i64: 1660 case INDEX_op_shr_i64: 1661 case INDEX_op_sar_i64: 1662 case INDEX_op_ext_i32_i64: 1663 case INDEX_op_extu_i32_i64: 1664 return TCG_TARGET_REG_BITS == 64; 1665 1666 case INDEX_op_movcond_i64: 1667 return TCG_TARGET_HAS_movcond_i64; 1668 case INDEX_op_div_i64: 1669 case INDEX_op_divu_i64: 1670 return TCG_TARGET_HAS_div_i64; 1671 case INDEX_op_rem_i64: 1672 case INDEX_op_remu_i64: 1673 return TCG_TARGET_HAS_rem_i64; 1674 case INDEX_op_div2_i64: 1675 case INDEX_op_divu2_i64: 1676 return TCG_TARGET_HAS_div2_i64; 1677 case INDEX_op_rotl_i64: 1678 case INDEX_op_rotr_i64: 1679 return TCG_TARGET_HAS_rot_i64; 1680 case INDEX_op_deposit_i64: 1681 return TCG_TARGET_HAS_deposit_i64; 1682 case INDEX_op_extract_i64: 1683 return TCG_TARGET_HAS_extract_i64; 1684 case INDEX_op_sextract_i64: 1685 return TCG_TARGET_HAS_sextract_i64; 1686 case INDEX_op_extract2_i64: 1687 return TCG_TARGET_HAS_extract2_i64; 1688 case INDEX_op_extrl_i64_i32: 1689 return TCG_TARGET_HAS_extrl_i64_i32; 1690 case INDEX_op_extrh_i64_i32: 1691 return TCG_TARGET_HAS_extrh_i64_i32; 1692 case INDEX_op_ext8s_i64: 1693 return TCG_TARGET_HAS_ext8s_i64; 1694 case INDEX_op_ext16s_i64: 1695 return TCG_TARGET_HAS_ext16s_i64; 1696 case INDEX_op_ext32s_i64: 1697 return TCG_TARGET_HAS_ext32s_i64; 1698 case INDEX_op_ext8u_i64: 1699 return TCG_TARGET_HAS_ext8u_i64; 1700 case INDEX_op_ext16u_i64: 1701 return TCG_TARGET_HAS_ext16u_i64; 1702 case INDEX_op_ext32u_i64: 1703 return TCG_TARGET_HAS_ext32u_i64; 1704 case INDEX_op_bswap16_i64: 1705 return TCG_TARGET_HAS_bswap16_i64; 1706 case INDEX_op_bswap32_i64: 1707 return TCG_TARGET_HAS_bswap32_i64; 1708 case INDEX_op_bswap64_i64: 1709 return TCG_TARGET_HAS_bswap64_i64; 1710 case INDEX_op_not_i64: 1711 return TCG_TARGET_HAS_not_i64; 1712 case INDEX_op_neg_i64: 1713 return TCG_TARGET_HAS_neg_i64; 1714 case INDEX_op_andc_i64: 1715 return TCG_TARGET_HAS_andc_i64; 1716 case INDEX_op_orc_i64: 1717 return TCG_TARGET_HAS_orc_i64; 1718 case INDEX_op_eqv_i64: 1719 return TCG_TARGET_HAS_eqv_i64; 1720 case INDEX_op_nand_i64: 1721 return TCG_TARGET_HAS_nand_i64; 1722 case INDEX_op_nor_i64: 1723 return TCG_TARGET_HAS_nor_i64; 1724 case INDEX_op_clz_i64: 1725 return TCG_TARGET_HAS_clz_i64; 1726 case INDEX_op_ctz_i64: 1727 return TCG_TARGET_HAS_ctz_i64; 1728 case INDEX_op_ctpop_i64: 1729 return TCG_TARGET_HAS_ctpop_i64; 1730 case INDEX_op_add2_i64: 1731 return TCG_TARGET_HAS_add2_i64; 1732 case INDEX_op_sub2_i64: 1733 return TCG_TARGET_HAS_sub2_i64; 1734 case INDEX_op_mulu2_i64: 1735 return TCG_TARGET_HAS_mulu2_i64; 1736 case INDEX_op_muls2_i64: 1737 return TCG_TARGET_HAS_muls2_i64; 1738 case INDEX_op_muluh_i64: 1739 return TCG_TARGET_HAS_muluh_i64; 1740 case INDEX_op_mulsh_i64: 1741 return TCG_TARGET_HAS_mulsh_i64; 1742 1743 case INDEX_op_mov_vec: 1744 case INDEX_op_dup_vec: 1745 case INDEX_op_dupm_vec: 1746 case INDEX_op_ld_vec: 1747 case INDEX_op_st_vec: 1748 case INDEX_op_add_vec: 1749 case INDEX_op_sub_vec: 1750 case INDEX_op_and_vec: 1751 case INDEX_op_or_vec: 1752 case INDEX_op_xor_vec: 1753 case INDEX_op_cmp_vec: 1754 return have_vec; 1755 case INDEX_op_dup2_vec: 1756 return have_vec && TCG_TARGET_REG_BITS == 32; 1757 case INDEX_op_not_vec: 1758 return have_vec && TCG_TARGET_HAS_not_vec; 1759 case INDEX_op_neg_vec: 1760 return have_vec && TCG_TARGET_HAS_neg_vec; 1761 case INDEX_op_abs_vec: 1762 return have_vec && TCG_TARGET_HAS_abs_vec; 1763 case INDEX_op_andc_vec: 1764 return have_vec && TCG_TARGET_HAS_andc_vec; 1765 case INDEX_op_orc_vec: 1766 return have_vec && TCG_TARGET_HAS_orc_vec; 1767 case INDEX_op_nand_vec: 1768 return have_vec && TCG_TARGET_HAS_nand_vec; 1769 case INDEX_op_nor_vec: 1770 return have_vec && TCG_TARGET_HAS_nor_vec; 1771 case INDEX_op_eqv_vec: 1772 return have_vec && TCG_TARGET_HAS_eqv_vec; 1773 case INDEX_op_mul_vec: 1774 return have_vec && TCG_TARGET_HAS_mul_vec; 1775 case INDEX_op_shli_vec: 1776 case INDEX_op_shri_vec: 1777 case INDEX_op_sari_vec: 1778 return have_vec && TCG_TARGET_HAS_shi_vec; 1779 case INDEX_op_shls_vec: 1780 case INDEX_op_shrs_vec: 1781 case INDEX_op_sars_vec: 1782 return have_vec && TCG_TARGET_HAS_shs_vec; 1783 case INDEX_op_shlv_vec: 1784 case INDEX_op_shrv_vec: 1785 case INDEX_op_sarv_vec: 1786 return have_vec && TCG_TARGET_HAS_shv_vec; 1787 case INDEX_op_rotli_vec: 1788 return have_vec && TCG_TARGET_HAS_roti_vec; 1789 case INDEX_op_rotls_vec: 1790 return have_vec && TCG_TARGET_HAS_rots_vec; 1791 case INDEX_op_rotlv_vec: 1792 case INDEX_op_rotrv_vec: 1793 return have_vec && TCG_TARGET_HAS_rotv_vec; 1794 case INDEX_op_ssadd_vec: 1795 case INDEX_op_usadd_vec: 1796 case INDEX_op_sssub_vec: 1797 case INDEX_op_ussub_vec: 1798 return have_vec && TCG_TARGET_HAS_sat_vec; 1799 case INDEX_op_smin_vec: 1800 case INDEX_op_umin_vec: 1801 case INDEX_op_smax_vec: 1802 case INDEX_op_umax_vec: 1803 return have_vec && TCG_TARGET_HAS_minmax_vec; 1804 case INDEX_op_bitsel_vec: 1805 return have_vec && TCG_TARGET_HAS_bitsel_vec; 1806 case INDEX_op_cmpsel_vec: 1807 return have_vec && TCG_TARGET_HAS_cmpsel_vec; 1808 1809 default: 1810 tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); 1811 return true; 1812 } 1813 } 1814 1815 static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs); 1816 1817 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) 1818 { 1819 const TCGHelperInfo *info; 1820 TCGv_i64 extend_free[MAX_CALL_IARGS]; 1821 int n_extend = 0; 1822 TCGOp *op; 1823 int i, n, pi = 0, total_args; 1824 1825 info = g_hash_table_lookup(helper_table, (gpointer)func); 1826 total_args = info->nr_out + info->nr_in + 2; 1827 op = tcg_op_alloc(INDEX_op_call, total_args); 1828 1829 #ifdef CONFIG_PLUGIN 1830 /* Flag helpers that may affect guest state */ 1831 if (tcg_ctx->plugin_insn && 1832 !(info->flags & TCG_CALL_PLUGIN) && 1833 !(info->flags & TCG_CALL_NO_SIDE_EFFECTS)) { 1834 tcg_ctx->plugin_insn->calls_helpers = true; 1835 } 1836 #endif 1837 1838 TCGOP_CALLO(op) = n = info->nr_out; 1839 switch (n) { 1840 case 0: 1841 tcg_debug_assert(ret == NULL); 1842 break; 1843 case 1: 1844 tcg_debug_assert(ret != NULL); 1845 op->args[pi++] = temp_arg(ret); 1846 break; 1847 case 2: 1848 case 4: 1849 tcg_debug_assert(ret != NULL); 1850 tcg_debug_assert(ret->base_type == ret->type + ctz32(n)); 1851 tcg_debug_assert(ret->temp_subindex == 0); 1852 for (i = 0; i < n; ++i) { 1853 op->args[pi++] = temp_arg(ret + i); 1854 } 1855 break; 1856 default: 1857 g_assert_not_reached(); 1858 } 1859 1860 TCGOP_CALLI(op) = n = info->nr_in; 1861 for (i = 0; i < n; i++) { 1862 const TCGCallArgumentLoc *loc = &info->in[i]; 1863 TCGTemp *ts = args[loc->arg_idx] + loc->tmp_subindex; 1864 1865 switch (loc->kind) { 1866 case TCG_CALL_ARG_NORMAL: 1867 case TCG_CALL_ARG_BY_REF: 1868 case TCG_CALL_ARG_BY_REF_N: 1869 op->args[pi++] = temp_arg(ts); 1870 break; 1871 1872 case TCG_CALL_ARG_EXTEND_U: 1873 case TCG_CALL_ARG_EXTEND_S: 1874 { 1875 TCGv_i64 temp = tcg_temp_ebb_new_i64(); 1876 TCGv_i32 orig = temp_tcgv_i32(ts); 1877 1878 if (loc->kind == TCG_CALL_ARG_EXTEND_S) { 1879 tcg_gen_ext_i32_i64(temp, orig); 1880 } else { 1881 tcg_gen_extu_i32_i64(temp, orig); 1882 } 1883 op->args[pi++] = tcgv_i64_arg(temp); 1884 extend_free[n_extend++] = temp; 1885 } 1886 break; 1887 1888 default: 1889 g_assert_not_reached(); 1890 } 1891 } 1892 op->args[pi++] = (uintptr_t)func; 1893 op->args[pi++] = (uintptr_t)info; 1894 tcg_debug_assert(pi == total_args); 1895 1896 QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); 1897 1898 tcg_debug_assert(n_extend < ARRAY_SIZE(extend_free)); 1899 for (i = 0; i < n_extend; ++i) { 1900 tcg_temp_free_i64(extend_free[i]); 1901 } 1902 } 1903 1904 static void tcg_reg_alloc_start(TCGContext *s) 1905 { 1906 int i, n; 1907 1908 for (i = 0, n = s->nb_temps; i < n; i++) { 1909 TCGTemp *ts = &s->temps[i]; 1910 TCGTempVal val = TEMP_VAL_MEM; 1911 1912 switch (ts->kind) { 1913 case TEMP_CONST: 1914 val = TEMP_VAL_CONST; 1915 break; 1916 case TEMP_FIXED: 1917 val = TEMP_VAL_REG; 1918 break; 1919 case TEMP_GLOBAL: 1920 break; 1921 case TEMP_EBB: 1922 val = TEMP_VAL_DEAD; 1923 /* fall through */ 1924 case TEMP_TB: 1925 ts->mem_allocated = 0; 1926 break; 1927 default: 1928 g_assert_not_reached(); 1929 } 1930 ts->val_type = val; 1931 } 1932 1933 memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); 1934 } 1935 1936 static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, 1937 TCGTemp *ts) 1938 { 1939 int idx = temp_idx(ts); 1940 1941 switch (ts->kind) { 1942 case TEMP_FIXED: 1943 case TEMP_GLOBAL: 1944 pstrcpy(buf, buf_size, ts->name); 1945 break; 1946 case TEMP_TB: 1947 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); 1948 break; 1949 case TEMP_EBB: 1950 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); 1951 break; 1952 case TEMP_CONST: 1953 switch (ts->type) { 1954 case TCG_TYPE_I32: 1955 snprintf(buf, buf_size, "$0x%x", (int32_t)ts->val); 1956 break; 1957 #if TCG_TARGET_REG_BITS > 32 1958 case TCG_TYPE_I64: 1959 snprintf(buf, buf_size, "$0x%" PRIx64, ts->val); 1960 break; 1961 #endif 1962 case TCG_TYPE_V64: 1963 case TCG_TYPE_V128: 1964 case TCG_TYPE_V256: 1965 snprintf(buf, buf_size, "v%d$0x%" PRIx64, 1966 64 << (ts->type - TCG_TYPE_V64), ts->val); 1967 break; 1968 default: 1969 g_assert_not_reached(); 1970 } 1971 break; 1972 } 1973 return buf; 1974 } 1975 1976 static char *tcg_get_arg_str(TCGContext *s, char *buf, 1977 int buf_size, TCGArg arg) 1978 { 1979 return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); 1980 } 1981 1982 static const char * const cond_name[] = 1983 { 1984 [TCG_COND_NEVER] = "never", 1985 [TCG_COND_ALWAYS] = "always", 1986 [TCG_COND_EQ] = "eq", 1987 [TCG_COND_NE] = "ne", 1988 [TCG_COND_LT] = "lt", 1989 [TCG_COND_GE] = "ge", 1990 [TCG_COND_LE] = "le", 1991 [TCG_COND_GT] = "gt", 1992 [TCG_COND_LTU] = "ltu", 1993 [TCG_COND_GEU] = "geu", 1994 [TCG_COND_LEU] = "leu", 1995 [TCG_COND_GTU] = "gtu" 1996 }; 1997 1998 static const char * const ldst_name[] = 1999 { 2000 [MO_UB] = "ub", 2001 [MO_SB] = "sb", 2002 [MO_LEUW] = "leuw", 2003 [MO_LESW] = "lesw", 2004 [MO_LEUL] = "leul", 2005 [MO_LESL] = "lesl", 2006 [MO_LEUQ] = "leq", 2007 [MO_BEUW] = "beuw", 2008 [MO_BESW] = "besw", 2009 [MO_BEUL] = "beul", 2010 [MO_BESL] = "besl", 2011 [MO_BEUQ] = "beq", 2012 }; 2013 2014 static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { 2015 #ifdef TARGET_ALIGNED_ONLY 2016 [MO_UNALN >> MO_ASHIFT] = "un+", 2017 [MO_ALIGN >> MO_ASHIFT] = "", 2018 #else 2019 [MO_UNALN >> MO_ASHIFT] = "", 2020 [MO_ALIGN >> MO_ASHIFT] = "al+", 2021 #endif 2022 [MO_ALIGN_2 >> MO_ASHIFT] = "al2+", 2023 [MO_ALIGN_4 >> MO_ASHIFT] = "al4+", 2024 [MO_ALIGN_8 >> MO_ASHIFT] = "al8+", 2025 [MO_ALIGN_16 >> MO_ASHIFT] = "al16+", 2026 [MO_ALIGN_32 >> MO_ASHIFT] = "al32+", 2027 [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", 2028 }; 2029 2030 static const char bswap_flag_name[][6] = { 2031 [TCG_BSWAP_IZ] = "iz", 2032 [TCG_BSWAP_OZ] = "oz", 2033 [TCG_BSWAP_OS] = "os", 2034 [TCG_BSWAP_IZ | TCG_BSWAP_OZ] = "iz,oz", 2035 [TCG_BSWAP_IZ | TCG_BSWAP_OS] = "iz,os", 2036 }; 2037 2038 static inline bool tcg_regset_single(TCGRegSet d) 2039 { 2040 return (d & (d - 1)) == 0; 2041 } 2042 2043 static inline TCGReg tcg_regset_first(TCGRegSet d) 2044 { 2045 if (TCG_TARGET_NB_REGS <= 32) { 2046 return ctz32(d); 2047 } else { 2048 return ctz64(d); 2049 } 2050 } 2051 2052 /* Return only the number of characters output -- no error return. */ 2053 #define ne_fprintf(...) \ 2054 ({ int ret_ = fprintf(__VA_ARGS__); ret_ >= 0 ? ret_ : 0; }) 2055 2056 static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) 2057 { 2058 char buf[128]; 2059 TCGOp *op; 2060 2061 QTAILQ_FOREACH(op, &s->ops, link) { 2062 int i, k, nb_oargs, nb_iargs, nb_cargs; 2063 const TCGOpDef *def; 2064 TCGOpcode c; 2065 int col = 0; 2066 2067 c = op->opc; 2068 def = &tcg_op_defs[c]; 2069 2070 if (c == INDEX_op_insn_start) { 2071 nb_oargs = 0; 2072 col += ne_fprintf(f, "\n ----"); 2073 2074 for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { 2075 target_ulong a; 2076 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 2077 a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]); 2078 #else 2079 a = op->args[i]; 2080 #endif 2081 col += ne_fprintf(f, " " TARGET_FMT_lx, a); 2082 } 2083 } else if (c == INDEX_op_call) { 2084 const TCGHelperInfo *info = tcg_call_info(op); 2085 void *func = tcg_call_func(op); 2086 2087 /* variable number of arguments */ 2088 nb_oargs = TCGOP_CALLO(op); 2089 nb_iargs = TCGOP_CALLI(op); 2090 nb_cargs = def->nb_cargs; 2091 2092 col += ne_fprintf(f, " %s ", def->name); 2093 2094 /* 2095 * Print the function name from TCGHelperInfo, if available. 2096 * Note that plugins have a template function for the info, 2097 * but the actual function pointer comes from the plugin. 2098 */ 2099 if (func == info->func) { 2100 col += ne_fprintf(f, "%s", info->name); 2101 } else { 2102 col += ne_fprintf(f, "plugin(%p)", func); 2103 } 2104 2105 col += ne_fprintf(f, ",$0x%x,$%d", info->flags, nb_oargs); 2106 for (i = 0; i < nb_oargs; i++) { 2107 col += ne_fprintf(f, ",%s", tcg_get_arg_str(s, buf, sizeof(buf), 2108 op->args[i])); 2109 } 2110 for (i = 0; i < nb_iargs; i++) { 2111 TCGArg arg = op->args[nb_oargs + i]; 2112 const char *t = tcg_get_arg_str(s, buf, sizeof(buf), arg); 2113 col += ne_fprintf(f, ",%s", t); 2114 } 2115 } else { 2116 col += ne_fprintf(f, " %s ", def->name); 2117 2118 nb_oargs = def->nb_oargs; 2119 nb_iargs = def->nb_iargs; 2120 nb_cargs = def->nb_cargs; 2121 2122 if (def->flags & TCG_OPF_VECTOR) { 2123 col += ne_fprintf(f, "v%d,e%d,", 64 << TCGOP_VECL(op), 2124 8 << TCGOP_VECE(op)); 2125 } 2126 2127 k = 0; 2128 for (i = 0; i < nb_oargs; i++) { 2129 const char *sep = k ? "," : ""; 2130 col += ne_fprintf(f, "%s%s", sep, 2131 tcg_get_arg_str(s, buf, sizeof(buf), 2132 op->args[k++])); 2133 } 2134 for (i = 0; i < nb_iargs; i++) { 2135 const char *sep = k ? "," : ""; 2136 col += ne_fprintf(f, "%s%s", sep, 2137 tcg_get_arg_str(s, buf, sizeof(buf), 2138 op->args[k++])); 2139 } 2140 switch (c) { 2141 case INDEX_op_brcond_i32: 2142 case INDEX_op_setcond_i32: 2143 case INDEX_op_movcond_i32: 2144 case INDEX_op_brcond2_i32: 2145 case INDEX_op_setcond2_i32: 2146 case INDEX_op_brcond_i64: 2147 case INDEX_op_setcond_i64: 2148 case INDEX_op_movcond_i64: 2149 case INDEX_op_cmp_vec: 2150 case INDEX_op_cmpsel_vec: 2151 if (op->args[k] < ARRAY_SIZE(cond_name) 2152 && cond_name[op->args[k]]) { 2153 col += ne_fprintf(f, ",%s", cond_name[op->args[k++]]); 2154 } else { 2155 col += ne_fprintf(f, ",$0x%" TCG_PRIlx, op->args[k++]); 2156 } 2157 i = 1; 2158 break; 2159 case INDEX_op_qemu_ld_i32: 2160 case INDEX_op_qemu_st_i32: 2161 case INDEX_op_qemu_st8_i32: 2162 case INDEX_op_qemu_ld_i64: 2163 case INDEX_op_qemu_st_i64: 2164 { 2165 MemOpIdx oi = op->args[k++]; 2166 MemOp op = get_memop(oi); 2167 unsigned ix = get_mmuidx(oi); 2168 2169 if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) { 2170 col += ne_fprintf(f, ",$0x%x,%u", op, ix); 2171 } else { 2172 const char *s_al, *s_op; 2173 s_al = alignment_name[(op & MO_AMASK) >> MO_ASHIFT]; 2174 s_op = ldst_name[op & (MO_BSWAP | MO_SSIZE)]; 2175 col += ne_fprintf(f, ",%s%s,%u", s_al, s_op, ix); 2176 } 2177 i = 1; 2178 } 2179 break; 2180 case INDEX_op_bswap16_i32: 2181 case INDEX_op_bswap16_i64: 2182 case INDEX_op_bswap32_i32: 2183 case INDEX_op_bswap32_i64: 2184 case INDEX_op_bswap64_i64: 2185 { 2186 TCGArg flags = op->args[k]; 2187 const char *name = NULL; 2188 2189 if (flags < ARRAY_SIZE(bswap_flag_name)) { 2190 name = bswap_flag_name[flags]; 2191 } 2192 if (name) { 2193 col += ne_fprintf(f, ",%s", name); 2194 } else { 2195 col += ne_fprintf(f, ",$0x%" TCG_PRIlx, flags); 2196 } 2197 i = k = 1; 2198 } 2199 break; 2200 default: 2201 i = 0; 2202 break; 2203 } 2204 switch (c) { 2205 case INDEX_op_set_label: 2206 case INDEX_op_br: 2207 case INDEX_op_brcond_i32: 2208 case INDEX_op_brcond_i64: 2209 case INDEX_op_brcond2_i32: 2210 col += ne_fprintf(f, "%s$L%d", k ? "," : "", 2211 arg_label(op->args[k])->id); 2212 i++, k++; 2213 break; 2214 case INDEX_op_mb: 2215 { 2216 TCGBar membar = op->args[k]; 2217 const char *b_op, *m_op; 2218 2219 switch (membar & TCG_BAR_SC) { 2220 case 0: 2221 b_op = "none"; 2222 break; 2223 case TCG_BAR_LDAQ: 2224 b_op = "acq"; 2225 break; 2226 case TCG_BAR_STRL: 2227 b_op = "rel"; 2228 break; 2229 case TCG_BAR_SC: 2230 b_op = "seq"; 2231 break; 2232 default: 2233 g_assert_not_reached(); 2234 } 2235 2236 switch (membar & TCG_MO_ALL) { 2237 case 0: 2238 m_op = "none"; 2239 break; 2240 case TCG_MO_LD_LD: 2241 m_op = "rr"; 2242 break; 2243 case TCG_MO_LD_ST: 2244 m_op = "rw"; 2245 break; 2246 case TCG_MO_ST_LD: 2247 m_op = "wr"; 2248 break; 2249 case TCG_MO_ST_ST: 2250 m_op = "ww"; 2251 break; 2252 case TCG_MO_LD_LD | TCG_MO_LD_ST: 2253 m_op = "rr+rw"; 2254 break; 2255 case TCG_MO_LD_LD | TCG_MO_ST_LD: 2256 m_op = "rr+wr"; 2257 break; 2258 case TCG_MO_LD_LD | TCG_MO_ST_ST: 2259 m_op = "rr+ww"; 2260 break; 2261 case TCG_MO_LD_ST | TCG_MO_ST_LD: 2262 m_op = "rw+wr"; 2263 break; 2264 case TCG_MO_LD_ST | TCG_MO_ST_ST: 2265 m_op = "rw+ww"; 2266 break; 2267 case TCG_MO_ST_LD | TCG_MO_ST_ST: 2268 m_op = "wr+ww"; 2269 break; 2270 case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_LD: 2271 m_op = "rr+rw+wr"; 2272 break; 2273 case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST: 2274 m_op = "rr+rw+ww"; 2275 break; 2276 case TCG_MO_LD_LD | TCG_MO_ST_LD | TCG_MO_ST_ST: 2277 m_op = "rr+wr+ww"; 2278 break; 2279 case TCG_MO_LD_ST | TCG_MO_ST_LD | TCG_MO_ST_ST: 2280 m_op = "rw+wr+ww"; 2281 break; 2282 case TCG_MO_ALL: 2283 m_op = "all"; 2284 break; 2285 default: 2286 g_assert_not_reached(); 2287 } 2288 2289 col += ne_fprintf(f, "%s%s:%s", (k ? "," : ""), b_op, m_op); 2290 i++, k++; 2291 } 2292 break; 2293 default: 2294 break; 2295 } 2296 for (; i < nb_cargs; i++, k++) { 2297 col += ne_fprintf(f, "%s$0x%" TCG_PRIlx, k ? "," : "", 2298 op->args[k]); 2299 } 2300 } 2301 2302 if (have_prefs || op->life) { 2303 for (; col < 40; ++col) { 2304 putc(' ', f); 2305 } 2306 } 2307 2308 if (op->life) { 2309 unsigned life = op->life; 2310 2311 if (life & (SYNC_ARG * 3)) { 2312 ne_fprintf(f, " sync:"); 2313 for (i = 0; i < 2; ++i) { 2314 if (life & (SYNC_ARG << i)) { 2315 ne_fprintf(f, " %d", i); 2316 } 2317 } 2318 } 2319 life /= DEAD_ARG; 2320 if (life) { 2321 ne_fprintf(f, " dead:"); 2322 for (i = 0; life; ++i, life >>= 1) { 2323 if (life & 1) { 2324 ne_fprintf(f, " %d", i); 2325 } 2326 } 2327 } 2328 } 2329 2330 if (have_prefs) { 2331 for (i = 0; i < nb_oargs; ++i) { 2332 TCGRegSet set = output_pref(op, i); 2333 2334 if (i == 0) { 2335 ne_fprintf(f, " pref="); 2336 } else { 2337 ne_fprintf(f, ","); 2338 } 2339 if (set == 0) { 2340 ne_fprintf(f, "none"); 2341 } else if (set == MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) { 2342 ne_fprintf(f, "all"); 2343 #ifdef CONFIG_DEBUG_TCG 2344 } else if (tcg_regset_single(set)) { 2345 TCGReg reg = tcg_regset_first(set); 2346 ne_fprintf(f, "%s", tcg_target_reg_names[reg]); 2347 #endif 2348 } else if (TCG_TARGET_NB_REGS <= 32) { 2349 ne_fprintf(f, "0x%x", (uint32_t)set); 2350 } else { 2351 ne_fprintf(f, "0x%" PRIx64, (uint64_t)set); 2352 } 2353 } 2354 } 2355 2356 putc('\n', f); 2357 } 2358 } 2359 2360 /* we give more priority to constraints with less registers */ 2361 static int get_constraint_priority(const TCGOpDef *def, int k) 2362 { 2363 const TCGArgConstraint *arg_ct = &def->args_ct[k]; 2364 int n = ctpop64(arg_ct->regs); 2365 2366 /* 2367 * Sort constraints of a single register first, which includes output 2368 * aliases (which must exactly match the input already allocated). 2369 */ 2370 if (n == 1 || arg_ct->oalias) { 2371 return INT_MAX; 2372 } 2373 2374 /* 2375 * Sort register pairs next, first then second immediately after. 2376 * Arbitrarily sort multiple pairs by the index of the first reg; 2377 * there shouldn't be many pairs. 2378 */ 2379 switch (arg_ct->pair) { 2380 case 1: 2381 case 3: 2382 return (k + 1) * 2; 2383 case 2: 2384 return (arg_ct->pair_index + 1) * 2 - 1; 2385 } 2386 2387 /* Finally, sort by decreasing register count. */ 2388 assert(n > 1); 2389 return -n; 2390 } 2391 2392 /* sort from highest priority to lowest */ 2393 static void sort_constraints(TCGOpDef *def, int start, int n) 2394 { 2395 int i, j; 2396 TCGArgConstraint *a = def->args_ct; 2397 2398 for (i = 0; i < n; i++) { 2399 a[start + i].sort_index = start + i; 2400 } 2401 if (n <= 1) { 2402 return; 2403 } 2404 for (i = 0; i < n - 1; i++) { 2405 for (j = i + 1; j < n; j++) { 2406 int p1 = get_constraint_priority(def, a[start + i].sort_index); 2407 int p2 = get_constraint_priority(def, a[start + j].sort_index); 2408 if (p1 < p2) { 2409 int tmp = a[start + i].sort_index; 2410 a[start + i].sort_index = a[start + j].sort_index; 2411 a[start + j].sort_index = tmp; 2412 } 2413 } 2414 } 2415 } 2416 2417 static void process_op_defs(TCGContext *s) 2418 { 2419 TCGOpcode op; 2420 2421 for (op = 0; op < NB_OPS; op++) { 2422 TCGOpDef *def = &tcg_op_defs[op]; 2423 const TCGTargetOpDef *tdefs; 2424 bool saw_alias_pair = false; 2425 int i, o, i2, o2, nb_args; 2426 2427 if (def->flags & TCG_OPF_NOT_PRESENT) { 2428 continue; 2429 } 2430 2431 nb_args = def->nb_iargs + def->nb_oargs; 2432 if (nb_args == 0) { 2433 continue; 2434 } 2435 2436 /* 2437 * Macro magic should make it impossible, but double-check that 2438 * the array index is in range. Since the signness of an enum 2439 * is implementation defined, force the result to unsigned. 2440 */ 2441 unsigned con_set = tcg_target_op_def(op); 2442 tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets)); 2443 tdefs = &constraint_sets[con_set]; 2444 2445 for (i = 0; i < nb_args; i++) { 2446 const char *ct_str = tdefs->args_ct_str[i]; 2447 bool input_p = i >= def->nb_oargs; 2448 2449 /* Incomplete TCGTargetOpDef entry. */ 2450 tcg_debug_assert(ct_str != NULL); 2451 2452 switch (*ct_str) { 2453 case '0' ... '9': 2454 o = *ct_str - '0'; 2455 tcg_debug_assert(input_p); 2456 tcg_debug_assert(o < def->nb_oargs); 2457 tcg_debug_assert(def->args_ct[o].regs != 0); 2458 tcg_debug_assert(!def->args_ct[o].oalias); 2459 def->args_ct[i] = def->args_ct[o]; 2460 /* The output sets oalias. */ 2461 def->args_ct[o].oalias = 1; 2462 def->args_ct[o].alias_index = i; 2463 /* The input sets ialias. */ 2464 def->args_ct[i].ialias = 1; 2465 def->args_ct[i].alias_index = o; 2466 if (def->args_ct[i].pair) { 2467 saw_alias_pair = true; 2468 } 2469 tcg_debug_assert(ct_str[1] == '\0'); 2470 continue; 2471 2472 case '&': 2473 tcg_debug_assert(!input_p); 2474 def->args_ct[i].newreg = true; 2475 ct_str++; 2476 break; 2477 2478 case 'p': /* plus */ 2479 /* Allocate to the register after the previous. */ 2480 tcg_debug_assert(i > (input_p ? def->nb_oargs : 0)); 2481 o = i - 1; 2482 tcg_debug_assert(!def->args_ct[o].pair); 2483 tcg_debug_assert(!def->args_ct[o].ct); 2484 def->args_ct[i] = (TCGArgConstraint){ 2485 .pair = 2, 2486 .pair_index = o, 2487 .regs = def->args_ct[o].regs << 1, 2488 }; 2489 def->args_ct[o].pair = 1; 2490 def->args_ct[o].pair_index = i; 2491 tcg_debug_assert(ct_str[1] == '\0'); 2492 continue; 2493 2494 case 'm': /* minus */ 2495 /* Allocate to the register before the previous. */ 2496 tcg_debug_assert(i > (input_p ? def->nb_oargs : 0)); 2497 o = i - 1; 2498 tcg_debug_assert(!def->args_ct[o].pair); 2499 tcg_debug_assert(!def->args_ct[o].ct); 2500 def->args_ct[i] = (TCGArgConstraint){ 2501 .pair = 1, 2502 .pair_index = o, 2503 .regs = def->args_ct[o].regs >> 1, 2504 }; 2505 def->args_ct[o].pair = 2; 2506 def->args_ct[o].pair_index = i; 2507 tcg_debug_assert(ct_str[1] == '\0'); 2508 continue; 2509 } 2510 2511 do { 2512 switch (*ct_str) { 2513 case 'i': 2514 def->args_ct[i].ct |= TCG_CT_CONST; 2515 break; 2516 2517 /* Include all of the target-specific constraints. */ 2518 2519 #undef CONST 2520 #define CONST(CASE, MASK) \ 2521 case CASE: def->args_ct[i].ct |= MASK; break; 2522 #define REGS(CASE, MASK) \ 2523 case CASE: def->args_ct[i].regs |= MASK; break; 2524 2525 #include "tcg-target-con-str.h" 2526 2527 #undef REGS 2528 #undef CONST 2529 default: 2530 case '0' ... '9': 2531 case '&': 2532 case 'p': 2533 case 'm': 2534 /* Typo in TCGTargetOpDef constraint. */ 2535 g_assert_not_reached(); 2536 } 2537 } while (*++ct_str != '\0'); 2538 } 2539 2540 /* TCGTargetOpDef entry with too much information? */ 2541 tcg_debug_assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL); 2542 2543 /* 2544 * Fix up output pairs that are aliased with inputs. 2545 * When we created the alias, we copied pair from the output. 2546 * There are three cases: 2547 * (1a) Pairs of inputs alias pairs of outputs. 2548 * (1b) One input aliases the first of a pair of outputs. 2549 * (2) One input aliases the second of a pair of outputs. 2550 * 2551 * Case 1a is handled by making sure that the pair_index'es are 2552 * properly updated so that they appear the same as a pair of inputs. 2553 * 2554 * Case 1b is handled by setting the pair_index of the input to 2555 * itself, simply so it doesn't point to an unrelated argument. 2556 * Since we don't encounter the "second" during the input allocation 2557 * phase, nothing happens with the second half of the input pair. 2558 * 2559 * Case 2 is handled by setting the second input to pair=3, the 2560 * first output to pair=3, and the pair_index'es to match. 2561 */ 2562 if (saw_alias_pair) { 2563 for (i = def->nb_oargs; i < nb_args; i++) { 2564 /* 2565 * Since [0-9pm] must be alone in the constraint string, 2566 * the only way they can both be set is if the pair comes 2567 * from the output alias. 2568 */ 2569 if (!def->args_ct[i].ialias) { 2570 continue; 2571 } 2572 switch (def->args_ct[i].pair) { 2573 case 0: 2574 break; 2575 case 1: 2576 o = def->args_ct[i].alias_index; 2577 o2 = def->args_ct[o].pair_index; 2578 tcg_debug_assert(def->args_ct[o].pair == 1); 2579 tcg_debug_assert(def->args_ct[o2].pair == 2); 2580 if (def->args_ct[o2].oalias) { 2581 /* Case 1a */ 2582 i2 = def->args_ct[o2].alias_index; 2583 tcg_debug_assert(def->args_ct[i2].pair == 2); 2584 def->args_ct[i2].pair_index = i; 2585 def->args_ct[i].pair_index = i2; 2586 } else { 2587 /* Case 1b */ 2588 def->args_ct[i].pair_index = i; 2589 } 2590 break; 2591 case 2: 2592 o = def->args_ct[i].alias_index; 2593 o2 = def->args_ct[o].pair_index; 2594 tcg_debug_assert(def->args_ct[o].pair == 2); 2595 tcg_debug_assert(def->args_ct[o2].pair == 1); 2596 if (def->args_ct[o2].oalias) { 2597 /* Case 1a */ 2598 i2 = def->args_ct[o2].alias_index; 2599 tcg_debug_assert(def->args_ct[i2].pair == 1); 2600 def->args_ct[i2].pair_index = i; 2601 def->args_ct[i].pair_index = i2; 2602 } else { 2603 /* Case 2 */ 2604 def->args_ct[i].pair = 3; 2605 def->args_ct[o2].pair = 3; 2606 def->args_ct[i].pair_index = o2; 2607 def->args_ct[o2].pair_index = i; 2608 } 2609 break; 2610 default: 2611 g_assert_not_reached(); 2612 } 2613 } 2614 } 2615 2616 /* sort the constraints (XXX: this is just an heuristic) */ 2617 sort_constraints(def, 0, def->nb_oargs); 2618 sort_constraints(def, def->nb_oargs, def->nb_iargs); 2619 } 2620 } 2621 2622 static void remove_label_use(TCGOp *op, int idx) 2623 { 2624 TCGLabel *label = arg_label(op->args[idx]); 2625 TCGLabelUse *use; 2626 2627 QSIMPLEQ_FOREACH(use, &label->branches, next) { 2628 if (use->op == op) { 2629 QSIMPLEQ_REMOVE(&label->branches, use, TCGLabelUse, next); 2630 return; 2631 } 2632 } 2633 g_assert_not_reached(); 2634 } 2635 2636 void tcg_op_remove(TCGContext *s, TCGOp *op) 2637 { 2638 switch (op->opc) { 2639 case INDEX_op_br: 2640 remove_label_use(op, 0); 2641 break; 2642 case INDEX_op_brcond_i32: 2643 case INDEX_op_brcond_i64: 2644 remove_label_use(op, 3); 2645 break; 2646 case INDEX_op_brcond2_i32: 2647 remove_label_use(op, 5); 2648 break; 2649 default: 2650 break; 2651 } 2652 2653 QTAILQ_REMOVE(&s->ops, op, link); 2654 QTAILQ_INSERT_TAIL(&s->free_ops, op, link); 2655 s->nb_ops--; 2656 2657 #ifdef CONFIG_PROFILER 2658 qatomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1); 2659 #endif 2660 } 2661 2662 void tcg_remove_ops_after(TCGOp *op) 2663 { 2664 TCGContext *s = tcg_ctx; 2665 2666 while (true) { 2667 TCGOp *last = tcg_last_op(); 2668 if (last == op) { 2669 return; 2670 } 2671 tcg_op_remove(s, last); 2672 } 2673 } 2674 2675 static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs) 2676 { 2677 TCGContext *s = tcg_ctx; 2678 TCGOp *op = NULL; 2679 2680 if (unlikely(!QTAILQ_EMPTY(&s->free_ops))) { 2681 QTAILQ_FOREACH(op, &s->free_ops, link) { 2682 if (nargs <= op->nargs) { 2683 QTAILQ_REMOVE(&s->free_ops, op, link); 2684 nargs = op->nargs; 2685 goto found; 2686 } 2687 } 2688 } 2689 2690 /* Most opcodes have 3 or 4 operands: reduce fragmentation. */ 2691 nargs = MAX(4, nargs); 2692 op = tcg_malloc(sizeof(TCGOp) + sizeof(TCGArg) * nargs); 2693 2694 found: 2695 memset(op, 0, offsetof(TCGOp, link)); 2696 op->opc = opc; 2697 op->nargs = nargs; 2698 2699 /* Check for bitfield overflow. */ 2700 tcg_debug_assert(op->nargs == nargs); 2701 2702 s->nb_ops++; 2703 return op; 2704 } 2705 2706 TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs) 2707 { 2708 TCGOp *op = tcg_op_alloc(opc, nargs); 2709 QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); 2710 return op; 2711 } 2712 2713 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, 2714 TCGOpcode opc, unsigned nargs) 2715 { 2716 TCGOp *new_op = tcg_op_alloc(opc, nargs); 2717 QTAILQ_INSERT_BEFORE(old_op, new_op, link); 2718 return new_op; 2719 } 2720 2721 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, 2722 TCGOpcode opc, unsigned nargs) 2723 { 2724 TCGOp *new_op = tcg_op_alloc(opc, nargs); 2725 QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link); 2726 return new_op; 2727 } 2728 2729 static void move_label_uses(TCGLabel *to, TCGLabel *from) 2730 { 2731 TCGLabelUse *u; 2732 2733 QSIMPLEQ_FOREACH(u, &from->branches, next) { 2734 TCGOp *op = u->op; 2735 switch (op->opc) { 2736 case INDEX_op_br: 2737 op->args[0] = label_arg(to); 2738 break; 2739 case INDEX_op_brcond_i32: 2740 case INDEX_op_brcond_i64: 2741 op->args[3] = label_arg(to); 2742 break; 2743 case INDEX_op_brcond2_i32: 2744 op->args[5] = label_arg(to); 2745 break; 2746 default: 2747 g_assert_not_reached(); 2748 } 2749 } 2750 2751 QSIMPLEQ_CONCAT(&to->branches, &from->branches); 2752 } 2753 2754 /* Reachable analysis : remove unreachable code. */ 2755 static void __attribute__((noinline)) 2756 reachable_code_pass(TCGContext *s) 2757 { 2758 TCGOp *op, *op_next, *op_prev; 2759 bool dead = false; 2760 2761 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { 2762 bool remove = dead; 2763 TCGLabel *label; 2764 2765 switch (op->opc) { 2766 case INDEX_op_set_label: 2767 label = arg_label(op->args[0]); 2768 2769 /* 2770 * Note that the first op in the TB is always a load, 2771 * so there is always something before a label. 2772 */ 2773 op_prev = QTAILQ_PREV(op, link); 2774 2775 /* 2776 * If we find two sequential labels, move all branches to 2777 * reference the second label and remove the first label. 2778 * Do this before branch to next optimization, so that the 2779 * middle label is out of the way. 2780 */ 2781 if (op_prev->opc == INDEX_op_set_label) { 2782 move_label_uses(label, arg_label(op_prev->args[0])); 2783 tcg_op_remove(s, op_prev); 2784 op_prev = QTAILQ_PREV(op, link); 2785 } 2786 2787 /* 2788 * Optimization can fold conditional branches to unconditional. 2789 * If we find a label which is preceded by an unconditional 2790 * branch to next, remove the branch. We couldn't do this when 2791 * processing the branch because any dead code between the branch 2792 * and label had not yet been removed. 2793 */ 2794 if (op_prev->opc == INDEX_op_br && 2795 label == arg_label(op_prev->args[0])) { 2796 tcg_op_remove(s, op_prev); 2797 /* Fall through means insns become live again. */ 2798 dead = false; 2799 } 2800 2801 if (QSIMPLEQ_EMPTY(&label->branches)) { 2802 /* 2803 * While there is an occasional backward branch, virtually 2804 * all branches generated by the translators are forward. 2805 * Which means that generally we will have already removed 2806 * all references to the label that will be, and there is 2807 * little to be gained by iterating. 2808 */ 2809 remove = true; 2810 } else { 2811 /* Once we see a label, insns become live again. */ 2812 dead = false; 2813 remove = false; 2814 } 2815 break; 2816 2817 case INDEX_op_br: 2818 case INDEX_op_exit_tb: 2819 case INDEX_op_goto_ptr: 2820 /* Unconditional branches; everything following is dead. */ 2821 dead = true; 2822 break; 2823 2824 case INDEX_op_call: 2825 /* Notice noreturn helper calls, raising exceptions. */ 2826 if (tcg_call_flags(op) & TCG_CALL_NO_RETURN) { 2827 dead = true; 2828 } 2829 break; 2830 2831 case INDEX_op_insn_start: 2832 /* Never remove -- we need to keep these for unwind. */ 2833 remove = false; 2834 break; 2835 2836 default: 2837 break; 2838 } 2839 2840 if (remove) { 2841 tcg_op_remove(s, op); 2842 } 2843 } 2844 } 2845 2846 #define TS_DEAD 1 2847 #define TS_MEM 2 2848 2849 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) 2850 #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n))) 2851 2852 /* For liveness_pass_1, the register preferences for a given temp. */ 2853 static inline TCGRegSet *la_temp_pref(TCGTemp *ts) 2854 { 2855 return ts->state_ptr; 2856 } 2857 2858 /* For liveness_pass_1, reset the preferences for a given temp to the 2859 * maximal regset for its type. 2860 */ 2861 static inline void la_reset_pref(TCGTemp *ts) 2862 { 2863 *la_temp_pref(ts) 2864 = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); 2865 } 2866 2867 /* liveness analysis: end of function: all temps are dead, and globals 2868 should be in memory. */ 2869 static void la_func_end(TCGContext *s, int ng, int nt) 2870 { 2871 int i; 2872 2873 for (i = 0; i < ng; ++i) { 2874 s->temps[i].state = TS_DEAD | TS_MEM; 2875 la_reset_pref(&s->temps[i]); 2876 } 2877 for (i = ng; i < nt; ++i) { 2878 s->temps[i].state = TS_DEAD; 2879 la_reset_pref(&s->temps[i]); 2880 } 2881 } 2882 2883 /* liveness analysis: end of basic block: all temps are dead, globals 2884 and local temps should be in memory. */ 2885 static void la_bb_end(TCGContext *s, int ng, int nt) 2886 { 2887 int i; 2888 2889 for (i = 0; i < nt; ++i) { 2890 TCGTemp *ts = &s->temps[i]; 2891 int state; 2892 2893 switch (ts->kind) { 2894 case TEMP_FIXED: 2895 case TEMP_GLOBAL: 2896 case TEMP_TB: 2897 state = TS_DEAD | TS_MEM; 2898 break; 2899 case TEMP_EBB: 2900 case TEMP_CONST: 2901 state = TS_DEAD; 2902 break; 2903 default: 2904 g_assert_not_reached(); 2905 } 2906 ts->state = state; 2907 la_reset_pref(ts); 2908 } 2909 } 2910 2911 /* liveness analysis: sync globals back to memory. */ 2912 static void la_global_sync(TCGContext *s, int ng) 2913 { 2914 int i; 2915 2916 for (i = 0; i < ng; ++i) { 2917 int state = s->temps[i].state; 2918 s->temps[i].state = state | TS_MEM; 2919 if (state == TS_DEAD) { 2920 /* If the global was previously dead, reset prefs. */ 2921 la_reset_pref(&s->temps[i]); 2922 } 2923 } 2924 } 2925 2926 /* 2927 * liveness analysis: conditional branch: all temps are dead unless 2928 * explicitly live-across-conditional-branch, globals and local temps 2929 * should be synced. 2930 */ 2931 static void la_bb_sync(TCGContext *s, int ng, int nt) 2932 { 2933 la_global_sync(s, ng); 2934 2935 for (int i = ng; i < nt; ++i) { 2936 TCGTemp *ts = &s->temps[i]; 2937 int state; 2938 2939 switch (ts->kind) { 2940 case TEMP_TB: 2941 state = ts->state; 2942 ts->state = state | TS_MEM; 2943 if (state != TS_DEAD) { 2944 continue; 2945 } 2946 break; 2947 case TEMP_EBB: 2948 case TEMP_CONST: 2949 continue; 2950 default: 2951 g_assert_not_reached(); 2952 } 2953 la_reset_pref(&s->temps[i]); 2954 } 2955 } 2956 2957 /* liveness analysis: sync globals back to memory and kill. */ 2958 static void la_global_kill(TCGContext *s, int ng) 2959 { 2960 int i; 2961 2962 for (i = 0; i < ng; i++) { 2963 s->temps[i].state = TS_DEAD | TS_MEM; 2964 la_reset_pref(&s->temps[i]); 2965 } 2966 } 2967 2968 /* liveness analysis: note live globals crossing calls. */ 2969 static void la_cross_call(TCGContext *s, int nt) 2970 { 2971 TCGRegSet mask = ~tcg_target_call_clobber_regs; 2972 int i; 2973 2974 for (i = 0; i < nt; i++) { 2975 TCGTemp *ts = &s->temps[i]; 2976 if (!(ts->state & TS_DEAD)) { 2977 TCGRegSet *pset = la_temp_pref(ts); 2978 TCGRegSet set = *pset; 2979 2980 set &= mask; 2981 /* If the combination is not possible, restart. */ 2982 if (set == 0) { 2983 set = tcg_target_available_regs[ts->type] & mask; 2984 } 2985 *pset = set; 2986 } 2987 } 2988 } 2989 2990 /* 2991 * Liveness analysis: Verify the lifetime of TEMP_TB, and reduce 2992 * to TEMP_EBB, if possible. 2993 */ 2994 static void __attribute__((noinline)) 2995 liveness_pass_0(TCGContext *s) 2996 { 2997 void * const multiple_ebb = (void *)(uintptr_t)-1; 2998 int nb_temps = s->nb_temps; 2999 TCGOp *op, *ebb; 3000 3001 for (int i = s->nb_globals; i < nb_temps; ++i) { 3002 s->temps[i].state_ptr = NULL; 3003 } 3004 3005 /* 3006 * Represent each EBB by the op at which it begins. In the case of 3007 * the first EBB, this is the first op, otherwise it is a label. 3008 * Collect the uses of each TEMP_TB: NULL for unused, EBB for use 3009 * within a single EBB, else MULTIPLE_EBB. 3010 */ 3011 ebb = QTAILQ_FIRST(&s->ops); 3012 QTAILQ_FOREACH(op, &s->ops, link) { 3013 const TCGOpDef *def; 3014 int nb_oargs, nb_iargs; 3015 3016 switch (op->opc) { 3017 case INDEX_op_set_label: 3018 ebb = op; 3019 continue; 3020 case INDEX_op_discard: 3021 continue; 3022 case INDEX_op_call: 3023 nb_oargs = TCGOP_CALLO(op); 3024 nb_iargs = TCGOP_CALLI(op); 3025 break; 3026 default: 3027 def = &tcg_op_defs[op->opc]; 3028 nb_oargs = def->nb_oargs; 3029 nb_iargs = def->nb_iargs; 3030 break; 3031 } 3032 3033 for (int i = 0; i < nb_oargs + nb_iargs; ++i) { 3034 TCGTemp *ts = arg_temp(op->args[i]); 3035 3036 if (ts->kind != TEMP_TB) { 3037 continue; 3038 } 3039 if (ts->state_ptr == NULL) { 3040 ts->state_ptr = ebb; 3041 } else if (ts->state_ptr != ebb) { 3042 ts->state_ptr = multiple_ebb; 3043 } 3044 } 3045 } 3046 3047 /* 3048 * For TEMP_TB that turned out not to be used beyond one EBB, 3049 * reduce the liveness to TEMP_EBB. 3050 */ 3051 for (int i = s->nb_globals; i < nb_temps; ++i) { 3052 TCGTemp *ts = &s->temps[i]; 3053 if (ts->kind == TEMP_TB && ts->state_ptr != multiple_ebb) { 3054 ts->kind = TEMP_EBB; 3055 } 3056 } 3057 } 3058 3059 /* Liveness analysis : update the opc_arg_life array to tell if a 3060 given input arguments is dead. Instructions updating dead 3061 temporaries are removed. */ 3062 static void __attribute__((noinline)) 3063 liveness_pass_1(TCGContext *s) 3064 { 3065 int nb_globals = s->nb_globals; 3066 int nb_temps = s->nb_temps; 3067 TCGOp *op, *op_prev; 3068 TCGRegSet *prefs; 3069 int i; 3070 3071 prefs = tcg_malloc(sizeof(TCGRegSet) * nb_temps); 3072 for (i = 0; i < nb_temps; ++i) { 3073 s->temps[i].state_ptr = prefs + i; 3074 } 3075 3076 /* ??? Should be redundant with the exit_tb that ends the TB. */ 3077 la_func_end(s, nb_globals, nb_temps); 3078 3079 QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, link, op_prev) { 3080 int nb_iargs, nb_oargs; 3081 TCGOpcode opc_new, opc_new2; 3082 bool have_opc_new2; 3083 TCGLifeData arg_life = 0; 3084 TCGTemp *ts; 3085 TCGOpcode opc = op->opc; 3086 const TCGOpDef *def = &tcg_op_defs[opc]; 3087 3088 switch (opc) { 3089 case INDEX_op_call: 3090 { 3091 const TCGHelperInfo *info = tcg_call_info(op); 3092 int call_flags = tcg_call_flags(op); 3093 3094 nb_oargs = TCGOP_CALLO(op); 3095 nb_iargs = TCGOP_CALLI(op); 3096 3097 /* pure functions can be removed if their result is unused */ 3098 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { 3099 for (i = 0; i < nb_oargs; i++) { 3100 ts = arg_temp(op->args[i]); 3101 if (ts->state != TS_DEAD) { 3102 goto do_not_remove_call; 3103 } 3104 } 3105 goto do_remove; 3106 } 3107 do_not_remove_call: 3108 3109 /* Output args are dead. */ 3110 for (i = 0; i < nb_oargs; i++) { 3111 ts = arg_temp(op->args[i]); 3112 if (ts->state & TS_DEAD) { 3113 arg_life |= DEAD_ARG << i; 3114 } 3115 if (ts->state & TS_MEM) { 3116 arg_life |= SYNC_ARG << i; 3117 } 3118 ts->state = TS_DEAD; 3119 la_reset_pref(ts); 3120 } 3121 3122 /* Not used -- it will be tcg_target_call_oarg_reg(). */ 3123 memset(op->output_pref, 0, sizeof(op->output_pref)); 3124 3125 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | 3126 TCG_CALL_NO_READ_GLOBALS))) { 3127 la_global_kill(s, nb_globals); 3128 } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { 3129 la_global_sync(s, nb_globals); 3130 } 3131 3132 /* Record arguments that die in this helper. */ 3133 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 3134 ts = arg_temp(op->args[i]); 3135 if (ts->state & TS_DEAD) { 3136 arg_life |= DEAD_ARG << i; 3137 } 3138 } 3139 3140 /* For all live registers, remove call-clobbered prefs. */ 3141 la_cross_call(s, nb_temps); 3142 3143 /* 3144 * Input arguments are live for preceding opcodes. 3145 * 3146 * For those arguments that die, and will be allocated in 3147 * registers, clear the register set for that arg, to be 3148 * filled in below. For args that will be on the stack, 3149 * reset to any available reg. Process arguments in reverse 3150 * order so that if a temp is used more than once, the stack 3151 * reset to max happens before the register reset to 0. 3152 */ 3153 for (i = nb_iargs - 1; i >= 0; i--) { 3154 const TCGCallArgumentLoc *loc = &info->in[i]; 3155 ts = arg_temp(op->args[nb_oargs + i]); 3156 3157 if (ts->state & TS_DEAD) { 3158 switch (loc->kind) { 3159 case TCG_CALL_ARG_NORMAL: 3160 case TCG_CALL_ARG_EXTEND_U: 3161 case TCG_CALL_ARG_EXTEND_S: 3162 if (REG_P(loc)) { 3163 *la_temp_pref(ts) = 0; 3164 break; 3165 } 3166 /* fall through */ 3167 default: 3168 *la_temp_pref(ts) = 3169 tcg_target_available_regs[ts->type]; 3170 break; 3171 } 3172 ts->state &= ~TS_DEAD; 3173 } 3174 } 3175 3176 /* 3177 * For each input argument, add its input register to prefs. 3178 * If a temp is used once, this produces a single set bit; 3179 * if a temp is used multiple times, this produces a set. 3180 */ 3181 for (i = 0; i < nb_iargs; i++) { 3182 const TCGCallArgumentLoc *loc = &info->in[i]; 3183 ts = arg_temp(op->args[nb_oargs + i]); 3184 3185 switch (loc->kind) { 3186 case TCG_CALL_ARG_NORMAL: 3187 case TCG_CALL_ARG_EXTEND_U: 3188 case TCG_CALL_ARG_EXTEND_S: 3189 if (REG_P(loc)) { 3190 tcg_regset_set_reg(*la_temp_pref(ts), 3191 tcg_target_call_iarg_regs[loc->arg_slot]); 3192 } 3193 break; 3194 default: 3195 break; 3196 } 3197 } 3198 } 3199 break; 3200 case INDEX_op_insn_start: 3201 break; 3202 case INDEX_op_discard: 3203 /* mark the temporary as dead */ 3204 ts = arg_temp(op->args[0]); 3205 ts->state = TS_DEAD; 3206 la_reset_pref(ts); 3207 break; 3208 3209 case INDEX_op_add2_i32: 3210 opc_new = INDEX_op_add_i32; 3211 goto do_addsub2; 3212 case INDEX_op_sub2_i32: 3213 opc_new = INDEX_op_sub_i32; 3214 goto do_addsub2; 3215 case INDEX_op_add2_i64: 3216 opc_new = INDEX_op_add_i64; 3217 goto do_addsub2; 3218 case INDEX_op_sub2_i64: 3219 opc_new = INDEX_op_sub_i64; 3220 do_addsub2: 3221 nb_iargs = 4; 3222 nb_oargs = 2; 3223 /* Test if the high part of the operation is dead, but not 3224 the low part. The result can be optimized to a simple 3225 add or sub. This happens often for x86_64 guest when the 3226 cpu mode is set to 32 bit. */ 3227 if (arg_temp(op->args[1])->state == TS_DEAD) { 3228 if (arg_temp(op->args[0])->state == TS_DEAD) { 3229 goto do_remove; 3230 } 3231 /* Replace the opcode and adjust the args in place, 3232 leaving 3 unused args at the end. */ 3233 op->opc = opc = opc_new; 3234 op->args[1] = op->args[2]; 3235 op->args[2] = op->args[4]; 3236 /* Fall through and mark the single-word operation live. */ 3237 nb_iargs = 2; 3238 nb_oargs = 1; 3239 } 3240 goto do_not_remove; 3241 3242 case INDEX_op_mulu2_i32: 3243 opc_new = INDEX_op_mul_i32; 3244 opc_new2 = INDEX_op_muluh_i32; 3245 have_opc_new2 = TCG_TARGET_HAS_muluh_i32; 3246 goto do_mul2; 3247 case INDEX_op_muls2_i32: 3248 opc_new = INDEX_op_mul_i32; 3249 opc_new2 = INDEX_op_mulsh_i32; 3250 have_opc_new2 = TCG_TARGET_HAS_mulsh_i32; 3251 goto do_mul2; 3252 case INDEX_op_mulu2_i64: 3253 opc_new = INDEX_op_mul_i64; 3254 opc_new2 = INDEX_op_muluh_i64; 3255 have_opc_new2 = TCG_TARGET_HAS_muluh_i64; 3256 goto do_mul2; 3257 case INDEX_op_muls2_i64: 3258 opc_new = INDEX_op_mul_i64; 3259 opc_new2 = INDEX_op_mulsh_i64; 3260 have_opc_new2 = TCG_TARGET_HAS_mulsh_i64; 3261 goto do_mul2; 3262 do_mul2: 3263 nb_iargs = 2; 3264 nb_oargs = 2; 3265 if (arg_temp(op->args[1])->state == TS_DEAD) { 3266 if (arg_temp(op->args[0])->state == TS_DEAD) { 3267 /* Both parts of the operation are dead. */ 3268 goto do_remove; 3269 } 3270 /* The high part of the operation is dead; generate the low. */ 3271 op->opc = opc = opc_new; 3272 op->args[1] = op->args[2]; 3273 op->args[2] = op->args[3]; 3274 } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) { 3275 /* The low part of the operation is dead; generate the high. */ 3276 op->opc = opc = opc_new2; 3277 op->args[0] = op->args[1]; 3278 op->args[1] = op->args[2]; 3279 op->args[2] = op->args[3]; 3280 } else { 3281 goto do_not_remove; 3282 } 3283 /* Mark the single-word operation live. */ 3284 nb_oargs = 1; 3285 goto do_not_remove; 3286 3287 default: 3288 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */ 3289 nb_iargs = def->nb_iargs; 3290 nb_oargs = def->nb_oargs; 3291 3292 /* Test if the operation can be removed because all 3293 its outputs are dead. We assume that nb_oargs == 0 3294 implies side effects */ 3295 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) { 3296 for (i = 0; i < nb_oargs; i++) { 3297 if (arg_temp(op->args[i])->state != TS_DEAD) { 3298 goto do_not_remove; 3299 } 3300 } 3301 goto do_remove; 3302 } 3303 goto do_not_remove; 3304 3305 do_remove: 3306 tcg_op_remove(s, op); 3307 break; 3308 3309 do_not_remove: 3310 for (i = 0; i < nb_oargs; i++) { 3311 ts = arg_temp(op->args[i]); 3312 3313 /* Remember the preference of the uses that followed. */ 3314 if (i < ARRAY_SIZE(op->output_pref)) { 3315 op->output_pref[i] = *la_temp_pref(ts); 3316 } 3317 3318 /* Output args are dead. */ 3319 if (ts->state & TS_DEAD) { 3320 arg_life |= DEAD_ARG << i; 3321 } 3322 if (ts->state & TS_MEM) { 3323 arg_life |= SYNC_ARG << i; 3324 } 3325 ts->state = TS_DEAD; 3326 la_reset_pref(ts); 3327 } 3328 3329 /* If end of basic block, update. */ 3330 if (def->flags & TCG_OPF_BB_EXIT) { 3331 la_func_end(s, nb_globals, nb_temps); 3332 } else if (def->flags & TCG_OPF_COND_BRANCH) { 3333 la_bb_sync(s, nb_globals, nb_temps); 3334 } else if (def->flags & TCG_OPF_BB_END) { 3335 la_bb_end(s, nb_globals, nb_temps); 3336 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 3337 la_global_sync(s, nb_globals); 3338 if (def->flags & TCG_OPF_CALL_CLOBBER) { 3339 la_cross_call(s, nb_temps); 3340 } 3341 } 3342 3343 /* Record arguments that die in this opcode. */ 3344 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 3345 ts = arg_temp(op->args[i]); 3346 if (ts->state & TS_DEAD) { 3347 arg_life |= DEAD_ARG << i; 3348 } 3349 } 3350 3351 /* Input arguments are live for preceding opcodes. */ 3352 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 3353 ts = arg_temp(op->args[i]); 3354 if (ts->state & TS_DEAD) { 3355 /* For operands that were dead, initially allow 3356 all regs for the type. */ 3357 *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; 3358 ts->state &= ~TS_DEAD; 3359 } 3360 } 3361 3362 /* Incorporate constraints for this operand. */ 3363 switch (opc) { 3364 case INDEX_op_mov_i32: 3365 case INDEX_op_mov_i64: 3366 /* Note that these are TCG_OPF_NOT_PRESENT and do not 3367 have proper constraints. That said, special case 3368 moves to propagate preferences backward. */ 3369 if (IS_DEAD_ARG(1)) { 3370 *la_temp_pref(arg_temp(op->args[0])) 3371 = *la_temp_pref(arg_temp(op->args[1])); 3372 } 3373 break; 3374 3375 default: 3376 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 3377 const TCGArgConstraint *ct = &def->args_ct[i]; 3378 TCGRegSet set, *pset; 3379 3380 ts = arg_temp(op->args[i]); 3381 pset = la_temp_pref(ts); 3382 set = *pset; 3383 3384 set &= ct->regs; 3385 if (ct->ialias) { 3386 set &= output_pref(op, ct->alias_index); 3387 } 3388 /* If the combination is not possible, restart. */ 3389 if (set == 0) { 3390 set = ct->regs; 3391 } 3392 *pset = set; 3393 } 3394 break; 3395 } 3396 break; 3397 } 3398 op->life = arg_life; 3399 } 3400 } 3401 3402 /* Liveness analysis: Convert indirect regs to direct temporaries. */ 3403 static bool __attribute__((noinline)) 3404 liveness_pass_2(TCGContext *s) 3405 { 3406 int nb_globals = s->nb_globals; 3407 int nb_temps, i; 3408 bool changes = false; 3409 TCGOp *op, *op_next; 3410 3411 /* Create a temporary for each indirect global. */ 3412 for (i = 0; i < nb_globals; ++i) { 3413 TCGTemp *its = &s->temps[i]; 3414 if (its->indirect_reg) { 3415 TCGTemp *dts = tcg_temp_alloc(s); 3416 dts->type = its->type; 3417 dts->base_type = its->base_type; 3418 dts->temp_subindex = its->temp_subindex; 3419 dts->kind = TEMP_EBB; 3420 its->state_ptr = dts; 3421 } else { 3422 its->state_ptr = NULL; 3423 } 3424 /* All globals begin dead. */ 3425 its->state = TS_DEAD; 3426 } 3427 for (nb_temps = s->nb_temps; i < nb_temps; ++i) { 3428 TCGTemp *its = &s->temps[i]; 3429 its->state_ptr = NULL; 3430 its->state = TS_DEAD; 3431 } 3432 3433 QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { 3434 TCGOpcode opc = op->opc; 3435 const TCGOpDef *def = &tcg_op_defs[opc]; 3436 TCGLifeData arg_life = op->life; 3437 int nb_iargs, nb_oargs, call_flags; 3438 TCGTemp *arg_ts, *dir_ts; 3439 3440 if (opc == INDEX_op_call) { 3441 nb_oargs = TCGOP_CALLO(op); 3442 nb_iargs = TCGOP_CALLI(op); 3443 call_flags = tcg_call_flags(op); 3444 } else { 3445 nb_iargs = def->nb_iargs; 3446 nb_oargs = def->nb_oargs; 3447 3448 /* Set flags similar to how calls require. */ 3449 if (def->flags & TCG_OPF_COND_BRANCH) { 3450 /* Like reading globals: sync_globals */ 3451 call_flags = TCG_CALL_NO_WRITE_GLOBALS; 3452 } else if (def->flags & TCG_OPF_BB_END) { 3453 /* Like writing globals: save_globals */ 3454 call_flags = 0; 3455 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { 3456 /* Like reading globals: sync_globals */ 3457 call_flags = TCG_CALL_NO_WRITE_GLOBALS; 3458 } else { 3459 /* No effect on globals. */ 3460 call_flags = (TCG_CALL_NO_READ_GLOBALS | 3461 TCG_CALL_NO_WRITE_GLOBALS); 3462 } 3463 } 3464 3465 /* Make sure that input arguments are available. */ 3466 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 3467 arg_ts = arg_temp(op->args[i]); 3468 dir_ts = arg_ts->state_ptr; 3469 if (dir_ts && arg_ts->state == TS_DEAD) { 3470 TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 3471 ? INDEX_op_ld_i32 3472 : INDEX_op_ld_i64); 3473 TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3); 3474 3475 lop->args[0] = temp_arg(dir_ts); 3476 lop->args[1] = temp_arg(arg_ts->mem_base); 3477 lop->args[2] = arg_ts->mem_offset; 3478 3479 /* Loaded, but synced with memory. */ 3480 arg_ts->state = TS_MEM; 3481 } 3482 } 3483 3484 /* Perform input replacement, and mark inputs that became dead. 3485 No action is required except keeping temp_state up to date 3486 so that we reload when needed. */ 3487 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 3488 arg_ts = arg_temp(op->args[i]); 3489 dir_ts = arg_ts->state_ptr; 3490 if (dir_ts) { 3491 op->args[i] = temp_arg(dir_ts); 3492 changes = true; 3493 if (IS_DEAD_ARG(i)) { 3494 arg_ts->state = TS_DEAD; 3495 } 3496 } 3497 } 3498 3499 /* Liveness analysis should ensure that the following are 3500 all correct, for call sites and basic block end points. */ 3501 if (call_flags & TCG_CALL_NO_READ_GLOBALS) { 3502 /* Nothing to do */ 3503 } else if (call_flags & TCG_CALL_NO_WRITE_GLOBALS) { 3504 for (i = 0; i < nb_globals; ++i) { 3505 /* Liveness should see that globals are synced back, 3506 that is, either TS_DEAD or TS_MEM. */ 3507 arg_ts = &s->temps[i]; 3508 tcg_debug_assert(arg_ts->state_ptr == 0 3509 || arg_ts->state != 0); 3510 } 3511 } else { 3512 for (i = 0; i < nb_globals; ++i) { 3513 /* Liveness should see that globals are saved back, 3514 that is, TS_DEAD, waiting to be reloaded. */ 3515 arg_ts = &s->temps[i]; 3516 tcg_debug_assert(arg_ts->state_ptr == 0 3517 || arg_ts->state == TS_DEAD); 3518 } 3519 } 3520 3521 /* Outputs become available. */ 3522 if (opc == INDEX_op_mov_i32 || opc == INDEX_op_mov_i64) { 3523 arg_ts = arg_temp(op->args[0]); 3524 dir_ts = arg_ts->state_ptr; 3525 if (dir_ts) { 3526 op->args[0] = temp_arg(dir_ts); 3527 changes = true; 3528 3529 /* The output is now live and modified. */ 3530 arg_ts->state = 0; 3531 3532 if (NEED_SYNC_ARG(0)) { 3533 TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 3534 ? INDEX_op_st_i32 3535 : INDEX_op_st_i64); 3536 TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3); 3537 TCGTemp *out_ts = dir_ts; 3538 3539 if (IS_DEAD_ARG(0)) { 3540 out_ts = arg_temp(op->args[1]); 3541 arg_ts->state = TS_DEAD; 3542 tcg_op_remove(s, op); 3543 } else { 3544 arg_ts->state = TS_MEM; 3545 } 3546 3547 sop->args[0] = temp_arg(out_ts); 3548 sop->args[1] = temp_arg(arg_ts->mem_base); 3549 sop->args[2] = arg_ts->mem_offset; 3550 } else { 3551 tcg_debug_assert(!IS_DEAD_ARG(0)); 3552 } 3553 } 3554 } else { 3555 for (i = 0; i < nb_oargs; i++) { 3556 arg_ts = arg_temp(op->args[i]); 3557 dir_ts = arg_ts->state_ptr; 3558 if (!dir_ts) { 3559 continue; 3560 } 3561 op->args[i] = temp_arg(dir_ts); 3562 changes = true; 3563 3564 /* The output is now live and modified. */ 3565 arg_ts->state = 0; 3566 3567 /* Sync outputs upon their last write. */ 3568 if (NEED_SYNC_ARG(i)) { 3569 TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 3570 ? INDEX_op_st_i32 3571 : INDEX_op_st_i64); 3572 TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3); 3573 3574 sop->args[0] = temp_arg(dir_ts); 3575 sop->args[1] = temp_arg(arg_ts->mem_base); 3576 sop->args[2] = arg_ts->mem_offset; 3577 3578 arg_ts->state = TS_MEM; 3579 } 3580 /* Drop outputs that are dead. */ 3581 if (IS_DEAD_ARG(i)) { 3582 arg_ts->state = TS_DEAD; 3583 } 3584 } 3585 } 3586 } 3587 3588 return changes; 3589 } 3590 3591 static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) 3592 { 3593 intptr_t off; 3594 int size, align; 3595 3596 /* When allocating an object, look at the full type. */ 3597 size = tcg_type_size(ts->base_type); 3598 switch (ts->base_type) { 3599 case TCG_TYPE_I32: 3600 align = 4; 3601 break; 3602 case TCG_TYPE_I64: 3603 case TCG_TYPE_V64: 3604 align = 8; 3605 break; 3606 case TCG_TYPE_I128: 3607 case TCG_TYPE_V128: 3608 case TCG_TYPE_V256: 3609 /* 3610 * Note that we do not require aligned storage for V256, 3611 * and that we provide alignment for I128 to match V128, 3612 * even if that's above what the host ABI requires. 3613 */ 3614 align = 16; 3615 break; 3616 default: 3617 g_assert_not_reached(); 3618 } 3619 3620 /* 3621 * Assume the stack is sufficiently aligned. 3622 * This affects e.g. ARM NEON, where we have 8 byte stack alignment 3623 * and do not require 16 byte vector alignment. This seems slightly 3624 * easier than fully parameterizing the above switch statement. 3625 */ 3626 align = MIN(TCG_TARGET_STACK_ALIGN, align); 3627 off = ROUND_UP(s->current_frame_offset, align); 3628 3629 /* If we've exhausted the stack frame, restart with a smaller TB. */ 3630 if (off + size > s->frame_end) { 3631 tcg_raise_tb_overflow(s); 3632 } 3633 s->current_frame_offset = off + size; 3634 #if defined(__sparc__) 3635 off += TCG_TARGET_STACK_BIAS; 3636 #endif 3637 3638 /* If the object was subdivided, assign memory to all the parts. */ 3639 if (ts->base_type != ts->type) { 3640 int part_size = tcg_type_size(ts->type); 3641 int part_count = size / part_size; 3642 3643 /* 3644 * Each part is allocated sequentially in tcg_temp_new_internal. 3645 * Jump back to the first part by subtracting the current index. 3646 */ 3647 ts -= ts->temp_subindex; 3648 for (int i = 0; i < part_count; ++i) { 3649 ts[i].mem_offset = off + i * part_size; 3650 ts[i].mem_base = s->frame_temp; 3651 ts[i].mem_allocated = 1; 3652 } 3653 } else { 3654 ts->mem_offset = off; 3655 ts->mem_base = s->frame_temp; 3656 ts->mem_allocated = 1; 3657 } 3658 } 3659 3660 /* Assign @reg to @ts, and update reg_to_temp[]. */ 3661 static void set_temp_val_reg(TCGContext *s, TCGTemp *ts, TCGReg reg) 3662 { 3663 if (ts->val_type == TEMP_VAL_REG) { 3664 TCGReg old = ts->reg; 3665 tcg_debug_assert(s->reg_to_temp[old] == ts); 3666 if (old == reg) { 3667 return; 3668 } 3669 s->reg_to_temp[old] = NULL; 3670 } 3671 tcg_debug_assert(s->reg_to_temp[reg] == NULL); 3672 s->reg_to_temp[reg] = ts; 3673 ts->val_type = TEMP_VAL_REG; 3674 ts->reg = reg; 3675 } 3676 3677 /* Assign a non-register value type to @ts, and update reg_to_temp[]. */ 3678 static void set_temp_val_nonreg(TCGContext *s, TCGTemp *ts, TCGTempVal type) 3679 { 3680 tcg_debug_assert(type != TEMP_VAL_REG); 3681 if (ts->val_type == TEMP_VAL_REG) { 3682 TCGReg reg = ts->reg; 3683 tcg_debug_assert(s->reg_to_temp[reg] == ts); 3684 s->reg_to_temp[reg] = NULL; 3685 } 3686 ts->val_type = type; 3687 } 3688 3689 static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); 3690 3691 /* Mark a temporary as free or dead. If 'free_or_dead' is negative, 3692 mark it free; otherwise mark it dead. */ 3693 static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) 3694 { 3695 TCGTempVal new_type; 3696 3697 switch (ts->kind) { 3698 case TEMP_FIXED: 3699 return; 3700 case TEMP_GLOBAL: 3701 case TEMP_TB: 3702 new_type = TEMP_VAL_MEM; 3703 break; 3704 case TEMP_EBB: 3705 new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD; 3706 break; 3707 case TEMP_CONST: 3708 new_type = TEMP_VAL_CONST; 3709 break; 3710 default: 3711 g_assert_not_reached(); 3712 } 3713 set_temp_val_nonreg(s, ts, new_type); 3714 } 3715 3716 /* Mark a temporary as dead. */ 3717 static inline void temp_dead(TCGContext *s, TCGTemp *ts) 3718 { 3719 temp_free_or_dead(s, ts, 1); 3720 } 3721 3722 /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary 3723 registers needs to be allocated to store a constant. If 'free_or_dead' 3724 is non-zero, subsequently release the temporary; if it is positive, the 3725 temp is dead; if it is negative, the temp is free. */ 3726 static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, 3727 TCGRegSet preferred_regs, int free_or_dead) 3728 { 3729 if (!temp_readonly(ts) && !ts->mem_coherent) { 3730 if (!ts->mem_allocated) { 3731 temp_allocate_frame(s, ts); 3732 } 3733 switch (ts->val_type) { 3734 case TEMP_VAL_CONST: 3735 /* If we're going to free the temp immediately, then we won't 3736 require it later in a register, so attempt to store the 3737 constant to memory directly. */ 3738 if (free_or_dead 3739 && tcg_out_sti(s, ts->type, ts->val, 3740 ts->mem_base->reg, ts->mem_offset)) { 3741 break; 3742 } 3743 temp_load(s, ts, tcg_target_available_regs[ts->type], 3744 allocated_regs, preferred_regs); 3745 /* fallthrough */ 3746 3747 case TEMP_VAL_REG: 3748 tcg_out_st(s, ts->type, ts->reg, 3749 ts->mem_base->reg, ts->mem_offset); 3750 break; 3751 3752 case TEMP_VAL_MEM: 3753 break; 3754 3755 case TEMP_VAL_DEAD: 3756 default: 3757 g_assert_not_reached(); 3758 } 3759 ts->mem_coherent = 1; 3760 } 3761 if (free_or_dead) { 3762 temp_free_or_dead(s, ts, free_or_dead); 3763 } 3764 } 3765 3766 /* free register 'reg' by spilling the corresponding temporary if necessary */ 3767 static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) 3768 { 3769 TCGTemp *ts = s->reg_to_temp[reg]; 3770 if (ts != NULL) { 3771 temp_sync(s, ts, allocated_regs, 0, -1); 3772 } 3773 } 3774 3775 /** 3776 * tcg_reg_alloc: 3777 * @required_regs: Set of registers in which we must allocate. 3778 * @allocated_regs: Set of registers which must be avoided. 3779 * @preferred_regs: Set of registers we should prefer. 3780 * @rev: True if we search the registers in "indirect" order. 3781 * 3782 * The allocated register must be in @required_regs & ~@allocated_regs, 3783 * but if we can put it in @preferred_regs we may save a move later. 3784 */ 3785 static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, 3786 TCGRegSet allocated_regs, 3787 TCGRegSet preferred_regs, bool rev) 3788 { 3789 int i, j, f, n = ARRAY_SIZE(tcg_target_reg_alloc_order); 3790 TCGRegSet reg_ct[2]; 3791 const int *order; 3792 3793 reg_ct[1] = required_regs & ~allocated_regs; 3794 tcg_debug_assert(reg_ct[1] != 0); 3795 reg_ct[0] = reg_ct[1] & preferred_regs; 3796 3797 /* Skip the preferred_regs option if it cannot be satisfied, 3798 or if the preference made no difference. */ 3799 f = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; 3800 3801 order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; 3802 3803 /* Try free registers, preferences first. */ 3804 for (j = f; j < 2; j++) { 3805 TCGRegSet set = reg_ct[j]; 3806 3807 if (tcg_regset_single(set)) { 3808 /* One register in the set. */ 3809 TCGReg reg = tcg_regset_first(set); 3810 if (s->reg_to_temp[reg] == NULL) { 3811 return reg; 3812 } 3813 } else { 3814 for (i = 0; i < n; i++) { 3815 TCGReg reg = order[i]; 3816 if (s->reg_to_temp[reg] == NULL && 3817 tcg_regset_test_reg(set, reg)) { 3818 return reg; 3819 } 3820 } 3821 } 3822 } 3823 3824 /* We must spill something. */ 3825 for (j = f; j < 2; j++) { 3826 TCGRegSet set = reg_ct[j]; 3827 3828 if (tcg_regset_single(set)) { 3829 /* One register in the set. */ 3830 TCGReg reg = tcg_regset_first(set); 3831 tcg_reg_free(s, reg, allocated_regs); 3832 return reg; 3833 } else { 3834 for (i = 0; i < n; i++) { 3835 TCGReg reg = order[i]; 3836 if (tcg_regset_test_reg(set, reg)) { 3837 tcg_reg_free(s, reg, allocated_regs); 3838 return reg; 3839 } 3840 } 3841 } 3842 } 3843 3844 g_assert_not_reached(); 3845 } 3846 3847 static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRegSet required_regs, 3848 TCGRegSet allocated_regs, 3849 TCGRegSet preferred_regs, bool rev) 3850 { 3851 int i, j, k, fmin, n = ARRAY_SIZE(tcg_target_reg_alloc_order); 3852 TCGRegSet reg_ct[2]; 3853 const int *order; 3854 3855 /* Ensure that if I is not in allocated_regs, I+1 is not either. */ 3856 reg_ct[1] = required_regs & ~(allocated_regs | (allocated_regs >> 1)); 3857 tcg_debug_assert(reg_ct[1] != 0); 3858 reg_ct[0] = reg_ct[1] & preferred_regs; 3859 3860 order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; 3861 3862 /* 3863 * Skip the preferred_regs option if it cannot be satisfied, 3864 * or if the preference made no difference. 3865 */ 3866 k = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; 3867 3868 /* 3869 * Minimize the number of flushes by looking for 2 free registers first, 3870 * then a single flush, then two flushes. 3871 */ 3872 for (fmin = 2; fmin >= 0; fmin--) { 3873 for (j = k; j < 2; j++) { 3874 TCGRegSet set = reg_ct[j]; 3875 3876 for (i = 0; i < n; i++) { 3877 TCGReg reg = order[i]; 3878 3879 if (tcg_regset_test_reg(set, reg)) { 3880 int f = !s->reg_to_temp[reg] + !s->reg_to_temp[reg + 1]; 3881 if (f >= fmin) { 3882 tcg_reg_free(s, reg, allocated_regs); 3883 tcg_reg_free(s, reg + 1, allocated_regs); 3884 return reg; 3885 } 3886 } 3887 } 3888 } 3889 } 3890 g_assert_not_reached(); 3891 } 3892 3893 /* Make sure the temporary is in a register. If needed, allocate the register 3894 from DESIRED while avoiding ALLOCATED. */ 3895 static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, 3896 TCGRegSet allocated_regs, TCGRegSet preferred_regs) 3897 { 3898 TCGReg reg; 3899 3900 switch (ts->val_type) { 3901 case TEMP_VAL_REG: 3902 return; 3903 case TEMP_VAL_CONST: 3904 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, 3905 preferred_regs, ts->indirect_base); 3906 if (ts->type <= TCG_TYPE_I64) { 3907 tcg_out_movi(s, ts->type, reg, ts->val); 3908 } else { 3909 uint64_t val = ts->val; 3910 MemOp vece = MO_64; 3911 3912 /* 3913 * Find the minimal vector element that matches the constant. 3914 * The targets will, in general, have to do this search anyway, 3915 * do this generically. 3916 */ 3917 if (val == dup_const(MO_8, val)) { 3918 vece = MO_8; 3919 } else if (val == dup_const(MO_16, val)) { 3920 vece = MO_16; 3921 } else if (val == dup_const(MO_32, val)) { 3922 vece = MO_32; 3923 } 3924 3925 tcg_out_dupi_vec(s, ts->type, vece, reg, ts->val); 3926 } 3927 ts->mem_coherent = 0; 3928 break; 3929 case TEMP_VAL_MEM: 3930 reg = tcg_reg_alloc(s, desired_regs, allocated_regs, 3931 preferred_regs, ts->indirect_base); 3932 tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); 3933 ts->mem_coherent = 1; 3934 break; 3935 case TEMP_VAL_DEAD: 3936 default: 3937 g_assert_not_reached(); 3938 } 3939 set_temp_val_reg(s, ts, reg); 3940 } 3941 3942 /* Save a temporary to memory. 'allocated_regs' is used in case a 3943 temporary registers needs to be allocated to store a constant. */ 3944 static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) 3945 { 3946 /* The liveness analysis already ensures that globals are back 3947 in memory. Keep an tcg_debug_assert for safety. */ 3948 tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || temp_readonly(ts)); 3949 } 3950 3951 /* save globals to their canonical location and assume they can be 3952 modified be the following code. 'allocated_regs' is used in case a 3953 temporary registers needs to be allocated to store a constant. */ 3954 static void save_globals(TCGContext *s, TCGRegSet allocated_regs) 3955 { 3956 int i, n; 3957 3958 for (i = 0, n = s->nb_globals; i < n; i++) { 3959 temp_save(s, &s->temps[i], allocated_regs); 3960 } 3961 } 3962 3963 /* sync globals to their canonical location and assume they can be 3964 read by the following code. 'allocated_regs' is used in case a 3965 temporary registers needs to be allocated to store a constant. */ 3966 static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) 3967 { 3968 int i, n; 3969 3970 for (i = 0, n = s->nb_globals; i < n; i++) { 3971 TCGTemp *ts = &s->temps[i]; 3972 tcg_debug_assert(ts->val_type != TEMP_VAL_REG 3973 || ts->kind == TEMP_FIXED 3974 || ts->mem_coherent); 3975 } 3976 } 3977 3978 /* at the end of a basic block, we assume all temporaries are dead and 3979 all globals are stored at their canonical location. */ 3980 static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) 3981 { 3982 int i; 3983 3984 for (i = s->nb_globals; i < s->nb_temps; i++) { 3985 TCGTemp *ts = &s->temps[i]; 3986 3987 switch (ts->kind) { 3988 case TEMP_TB: 3989 temp_save(s, ts, allocated_regs); 3990 break; 3991 case TEMP_EBB: 3992 /* The liveness analysis already ensures that temps are dead. 3993 Keep an tcg_debug_assert for safety. */ 3994 tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); 3995 break; 3996 case TEMP_CONST: 3997 /* Similarly, we should have freed any allocated register. */ 3998 tcg_debug_assert(ts->val_type == TEMP_VAL_CONST); 3999 break; 4000 default: 4001 g_assert_not_reached(); 4002 } 4003 } 4004 4005 save_globals(s, allocated_regs); 4006 } 4007 4008 /* 4009 * At a conditional branch, we assume all temporaries are dead unless 4010 * explicitly live-across-conditional-branch; all globals and local 4011 * temps are synced to their location. 4012 */ 4013 static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) 4014 { 4015 sync_globals(s, allocated_regs); 4016 4017 for (int i = s->nb_globals; i < s->nb_temps; i++) { 4018 TCGTemp *ts = &s->temps[i]; 4019 /* 4020 * The liveness analysis already ensures that temps are dead. 4021 * Keep tcg_debug_asserts for safety. 4022 */ 4023 switch (ts->kind) { 4024 case TEMP_TB: 4025 tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent); 4026 break; 4027 case TEMP_EBB: 4028 case TEMP_CONST: 4029 break; 4030 default: 4031 g_assert_not_reached(); 4032 } 4033 } 4034 } 4035 4036 /* 4037 * Specialized code generation for INDEX_op_mov_* with a constant. 4038 */ 4039 static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, 4040 tcg_target_ulong val, TCGLifeData arg_life, 4041 TCGRegSet preferred_regs) 4042 { 4043 /* ENV should not be modified. */ 4044 tcg_debug_assert(!temp_readonly(ots)); 4045 4046 /* The movi is not explicitly generated here. */ 4047 set_temp_val_nonreg(s, ots, TEMP_VAL_CONST); 4048 ots->val = val; 4049 ots->mem_coherent = 0; 4050 if (NEED_SYNC_ARG(0)) { 4051 temp_sync(s, ots, s->reserved_regs, preferred_regs, IS_DEAD_ARG(0)); 4052 } else if (IS_DEAD_ARG(0)) { 4053 temp_dead(s, ots); 4054 } 4055 } 4056 4057 /* 4058 * Specialized code generation for INDEX_op_mov_*. 4059 */ 4060 static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) 4061 { 4062 const TCGLifeData arg_life = op->life; 4063 TCGRegSet allocated_regs, preferred_regs; 4064 TCGTemp *ts, *ots; 4065 TCGType otype, itype; 4066 TCGReg oreg, ireg; 4067 4068 allocated_regs = s->reserved_regs; 4069 preferred_regs = output_pref(op, 0); 4070 ots = arg_temp(op->args[0]); 4071 ts = arg_temp(op->args[1]); 4072 4073 /* ENV should not be modified. */ 4074 tcg_debug_assert(!temp_readonly(ots)); 4075 4076 /* Note that otype != itype for no-op truncation. */ 4077 otype = ots->type; 4078 itype = ts->type; 4079 4080 if (ts->val_type == TEMP_VAL_CONST) { 4081 /* propagate constant or generate sti */ 4082 tcg_target_ulong val = ts->val; 4083 if (IS_DEAD_ARG(1)) { 4084 temp_dead(s, ts); 4085 } 4086 tcg_reg_alloc_do_movi(s, ots, val, arg_life, preferred_regs); 4087 return; 4088 } 4089 4090 /* If the source value is in memory we're going to be forced 4091 to have it in a register in order to perform the copy. Copy 4092 the SOURCE value into its own register first, that way we 4093 don't have to reload SOURCE the next time it is used. */ 4094 if (ts->val_type == TEMP_VAL_MEM) { 4095 temp_load(s, ts, tcg_target_available_regs[itype], 4096 allocated_regs, preferred_regs); 4097 } 4098 tcg_debug_assert(ts->val_type == TEMP_VAL_REG); 4099 ireg = ts->reg; 4100 4101 if (IS_DEAD_ARG(0)) { 4102 /* mov to a non-saved dead register makes no sense (even with 4103 liveness analysis disabled). */ 4104 tcg_debug_assert(NEED_SYNC_ARG(0)); 4105 if (!ots->mem_allocated) { 4106 temp_allocate_frame(s, ots); 4107 } 4108 tcg_out_st(s, otype, ireg, ots->mem_base->reg, ots->mem_offset); 4109 if (IS_DEAD_ARG(1)) { 4110 temp_dead(s, ts); 4111 } 4112 temp_dead(s, ots); 4113 return; 4114 } 4115 4116 if (IS_DEAD_ARG(1) && ts->kind != TEMP_FIXED) { 4117 /* 4118 * The mov can be suppressed. Kill input first, so that it 4119 * is unlinked from reg_to_temp, then set the output to the 4120 * reg that we saved from the input. 4121 */ 4122 temp_dead(s, ts); 4123 oreg = ireg; 4124 } else { 4125 if (ots->val_type == TEMP_VAL_REG) { 4126 oreg = ots->reg; 4127 } else { 4128 /* Make sure to not spill the input register during allocation. */ 4129 oreg = tcg_reg_alloc(s, tcg_target_available_regs[otype], 4130 allocated_regs | ((TCGRegSet)1 << ireg), 4131 preferred_regs, ots->indirect_base); 4132 } 4133 if (!tcg_out_mov(s, otype, oreg, ireg)) { 4134 /* 4135 * Cross register class move not supported. 4136 * Store the source register into the destination slot 4137 * and leave the destination temp as TEMP_VAL_MEM. 4138 */ 4139 assert(!temp_readonly(ots)); 4140 if (!ts->mem_allocated) { 4141 temp_allocate_frame(s, ots); 4142 } 4143 tcg_out_st(s, ts->type, ireg, ots->mem_base->reg, ots->mem_offset); 4144 set_temp_val_nonreg(s, ts, TEMP_VAL_MEM); 4145 ots->mem_coherent = 1; 4146 return; 4147 } 4148 } 4149 set_temp_val_reg(s, ots, oreg); 4150 ots->mem_coherent = 0; 4151 4152 if (NEED_SYNC_ARG(0)) { 4153 temp_sync(s, ots, allocated_regs, 0, 0); 4154 } 4155 } 4156 4157 /* 4158 * Specialized code generation for INDEX_op_dup_vec. 4159 */ 4160 static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) 4161 { 4162 const TCGLifeData arg_life = op->life; 4163 TCGRegSet dup_out_regs, dup_in_regs; 4164 TCGTemp *its, *ots; 4165 TCGType itype, vtype; 4166 unsigned vece; 4167 int lowpart_ofs; 4168 bool ok; 4169 4170 ots = arg_temp(op->args[0]); 4171 its = arg_temp(op->args[1]); 4172 4173 /* ENV should not be modified. */ 4174 tcg_debug_assert(!temp_readonly(ots)); 4175 4176 itype = its->type; 4177 vece = TCGOP_VECE(op); 4178 vtype = TCGOP_VECL(op) + TCG_TYPE_V64; 4179 4180 if (its->val_type == TEMP_VAL_CONST) { 4181 /* Propagate constant via movi -> dupi. */ 4182 tcg_target_ulong val = its->val; 4183 if (IS_DEAD_ARG(1)) { 4184 temp_dead(s, its); 4185 } 4186 tcg_reg_alloc_do_movi(s, ots, val, arg_life, output_pref(op, 0)); 4187 return; 4188 } 4189 4190 dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; 4191 dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs; 4192 4193 /* Allocate the output register now. */ 4194 if (ots->val_type != TEMP_VAL_REG) { 4195 TCGRegSet allocated_regs = s->reserved_regs; 4196 TCGReg oreg; 4197 4198 if (!IS_DEAD_ARG(1) && its->val_type == TEMP_VAL_REG) { 4199 /* Make sure to not spill the input register. */ 4200 tcg_regset_set_reg(allocated_regs, its->reg); 4201 } 4202 oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, 4203 output_pref(op, 0), ots->indirect_base); 4204 set_temp_val_reg(s, ots, oreg); 4205 } 4206 4207 switch (its->val_type) { 4208 case TEMP_VAL_REG: 4209 /* 4210 * The dup constriaints must be broad, covering all possible VECE. 4211 * However, tcg_op_dup_vec() gets to see the VECE and we allow it 4212 * to fail, indicating that extra moves are required for that case. 4213 */ 4214 if (tcg_regset_test_reg(dup_in_regs, its->reg)) { 4215 if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) { 4216 goto done; 4217 } 4218 /* Try again from memory or a vector input register. */ 4219 } 4220 if (!its->mem_coherent) { 4221 /* 4222 * The input register is not synced, and so an extra store 4223 * would be required to use memory. Attempt an integer-vector 4224 * register move first. We do not have a TCGRegSet for this. 4225 */ 4226 if (tcg_out_mov(s, itype, ots->reg, its->reg)) { 4227 break; 4228 } 4229 /* Sync the temp back to its slot and load from there. */ 4230 temp_sync(s, its, s->reserved_regs, 0, 0); 4231 } 4232 /* fall through */ 4233 4234 case TEMP_VAL_MEM: 4235 lowpart_ofs = 0; 4236 if (HOST_BIG_ENDIAN) { 4237 lowpart_ofs = tcg_type_size(itype) - (1 << vece); 4238 } 4239 if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg, 4240 its->mem_offset + lowpart_ofs)) { 4241 goto done; 4242 } 4243 /* Load the input into the destination vector register. */ 4244 tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset); 4245 break; 4246 4247 default: 4248 g_assert_not_reached(); 4249 } 4250 4251 /* We now have a vector input register, so dup must succeed. */ 4252 ok = tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg); 4253 tcg_debug_assert(ok); 4254 4255 done: 4256 ots->mem_coherent = 0; 4257 if (IS_DEAD_ARG(1)) { 4258 temp_dead(s, its); 4259 } 4260 if (NEED_SYNC_ARG(0)) { 4261 temp_sync(s, ots, s->reserved_regs, 0, 0); 4262 } 4263 if (IS_DEAD_ARG(0)) { 4264 temp_dead(s, ots); 4265 } 4266 } 4267 4268 static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) 4269 { 4270 const TCGLifeData arg_life = op->life; 4271 const TCGOpDef * const def = &tcg_op_defs[op->opc]; 4272 TCGRegSet i_allocated_regs; 4273 TCGRegSet o_allocated_regs; 4274 int i, k, nb_iargs, nb_oargs; 4275 TCGReg reg; 4276 TCGArg arg; 4277 const TCGArgConstraint *arg_ct; 4278 TCGTemp *ts; 4279 TCGArg new_args[TCG_MAX_OP_ARGS]; 4280 int const_args[TCG_MAX_OP_ARGS]; 4281 4282 nb_oargs = def->nb_oargs; 4283 nb_iargs = def->nb_iargs; 4284 4285 /* copy constants */ 4286 memcpy(new_args + nb_oargs + nb_iargs, 4287 op->args + nb_oargs + nb_iargs, 4288 sizeof(TCGArg) * def->nb_cargs); 4289 4290 i_allocated_regs = s->reserved_regs; 4291 o_allocated_regs = s->reserved_regs; 4292 4293 /* satisfy input constraints */ 4294 for (k = 0; k < nb_iargs; k++) { 4295 TCGRegSet i_preferred_regs, i_required_regs; 4296 bool allocate_new_reg, copyto_new_reg; 4297 TCGTemp *ts2; 4298 int i1, i2; 4299 4300 i = def->args_ct[nb_oargs + k].sort_index; 4301 arg = op->args[i]; 4302 arg_ct = &def->args_ct[i]; 4303 ts = arg_temp(arg); 4304 4305 if (ts->val_type == TEMP_VAL_CONST 4306 && tcg_target_const_match(ts->val, ts->type, arg_ct->ct)) { 4307 /* constant is OK for instruction */ 4308 const_args[i] = 1; 4309 new_args[i] = ts->val; 4310 continue; 4311 } 4312 4313 reg = ts->reg; 4314 i_preferred_regs = 0; 4315 i_required_regs = arg_ct->regs; 4316 allocate_new_reg = false; 4317 copyto_new_reg = false; 4318 4319 switch (arg_ct->pair) { 4320 case 0: /* not paired */ 4321 if (arg_ct->ialias) { 4322 i_preferred_regs = output_pref(op, arg_ct->alias_index); 4323 4324 /* 4325 * If the input is readonly, then it cannot also be an 4326 * output and aliased to itself. If the input is not 4327 * dead after the instruction, we must allocate a new 4328 * register and move it. 4329 */ 4330 if (temp_readonly(ts) || !IS_DEAD_ARG(i)) { 4331 allocate_new_reg = true; 4332 } else if (ts->val_type == TEMP_VAL_REG) { 4333 /* 4334 * Check if the current register has already been 4335 * allocated for another input. 4336 */ 4337 allocate_new_reg = 4338 tcg_regset_test_reg(i_allocated_regs, reg); 4339 } 4340 } 4341 if (!allocate_new_reg) { 4342 temp_load(s, ts, i_required_regs, i_allocated_regs, 4343 i_preferred_regs); 4344 reg = ts->reg; 4345 allocate_new_reg = !tcg_regset_test_reg(i_required_regs, reg); 4346 } 4347 if (allocate_new_reg) { 4348 /* 4349 * Allocate a new register matching the constraint 4350 * and move the temporary register into it. 4351 */ 4352 temp_load(s, ts, tcg_target_available_regs[ts->type], 4353 i_allocated_regs, 0); 4354 reg = tcg_reg_alloc(s, i_required_regs, i_allocated_regs, 4355 i_preferred_regs, ts->indirect_base); 4356 copyto_new_reg = true; 4357 } 4358 break; 4359 4360 case 1: 4361 /* First of an input pair; if i1 == i2, the second is an output. */ 4362 i1 = i; 4363 i2 = arg_ct->pair_index; 4364 ts2 = i1 != i2 ? arg_temp(op->args[i2]) : NULL; 4365 4366 /* 4367 * It is easier to default to allocating a new pair 4368 * and to identify a few cases where it's not required. 4369 */ 4370 if (arg_ct->ialias) { 4371 i_preferred_regs = output_pref(op, arg_ct->alias_index); 4372 if (IS_DEAD_ARG(i1) && 4373 IS_DEAD_ARG(i2) && 4374 !temp_readonly(ts) && 4375 ts->val_type == TEMP_VAL_REG && 4376 ts->reg < TCG_TARGET_NB_REGS - 1 && 4377 tcg_regset_test_reg(i_required_regs, reg) && 4378 !tcg_regset_test_reg(i_allocated_regs, reg) && 4379 !tcg_regset_test_reg(i_allocated_regs, reg + 1) && 4380 (ts2 4381 ? ts2->val_type == TEMP_VAL_REG && 4382 ts2->reg == reg + 1 && 4383 !temp_readonly(ts2) 4384 : s->reg_to_temp[reg + 1] == NULL)) { 4385 break; 4386 } 4387 } else { 4388 /* Without aliasing, the pair must also be an input. */ 4389 tcg_debug_assert(ts2); 4390 if (ts->val_type == TEMP_VAL_REG && 4391 ts2->val_type == TEMP_VAL_REG && 4392 ts2->reg == reg + 1 && 4393 tcg_regset_test_reg(i_required_regs, reg)) { 4394 break; 4395 } 4396 } 4397 reg = tcg_reg_alloc_pair(s, i_required_regs, i_allocated_regs, 4398 0, ts->indirect_base); 4399 goto do_pair; 4400 4401 case 2: /* pair second */ 4402 reg = new_args[arg_ct->pair_index] + 1; 4403 goto do_pair; 4404 4405 case 3: /* ialias with second output, no first input */ 4406 tcg_debug_assert(arg_ct->ialias); 4407 i_preferred_regs = output_pref(op, arg_ct->alias_index); 4408 4409 if (IS_DEAD_ARG(i) && 4410 !temp_readonly(ts) && 4411 ts->val_type == TEMP_VAL_REG && 4412 reg > 0 && 4413 s->reg_to_temp[reg - 1] == NULL && 4414 tcg_regset_test_reg(i_required_regs, reg) && 4415 !tcg_regset_test_reg(i_allocated_regs, reg) && 4416 !tcg_regset_test_reg(i_allocated_regs, reg - 1)) { 4417 tcg_regset_set_reg(i_allocated_regs, reg - 1); 4418 break; 4419 } 4420 reg = tcg_reg_alloc_pair(s, i_required_regs >> 1, 4421 i_allocated_regs, 0, 4422 ts->indirect_base); 4423 tcg_regset_set_reg(i_allocated_regs, reg); 4424 reg += 1; 4425 goto do_pair; 4426 4427 do_pair: 4428 /* 4429 * If an aliased input is not dead after the instruction, 4430 * we must allocate a new register and move it. 4431 */ 4432 if (arg_ct->ialias && (!IS_DEAD_ARG(i) || temp_readonly(ts))) { 4433 TCGRegSet t_allocated_regs = i_allocated_regs; 4434 4435 /* 4436 * Because of the alias, and the continued life, make sure 4437 * that the temp is somewhere *other* than the reg pair, 4438 * and we get a copy in reg. 4439 */ 4440 tcg_regset_set_reg(t_allocated_regs, reg); 4441 tcg_regset_set_reg(t_allocated_regs, reg + 1); 4442 if (ts->val_type == TEMP_VAL_REG && ts->reg == reg) { 4443 /* If ts was already in reg, copy it somewhere else. */ 4444 TCGReg nr; 4445 bool ok; 4446 4447 tcg_debug_assert(ts->kind != TEMP_FIXED); 4448 nr = tcg_reg_alloc(s, tcg_target_available_regs[ts->type], 4449 t_allocated_regs, 0, ts->indirect_base); 4450 ok = tcg_out_mov(s, ts->type, nr, reg); 4451 tcg_debug_assert(ok); 4452 4453 set_temp_val_reg(s, ts, nr); 4454 } else { 4455 temp_load(s, ts, tcg_target_available_regs[ts->type], 4456 t_allocated_regs, 0); 4457 copyto_new_reg = true; 4458 } 4459 } else { 4460 /* Preferably allocate to reg, otherwise copy. */ 4461 i_required_regs = (TCGRegSet)1 << reg; 4462 temp_load(s, ts, i_required_regs, i_allocated_regs, 4463 i_preferred_regs); 4464 copyto_new_reg = ts->reg != reg; 4465 } 4466 break; 4467 4468 default: 4469 g_assert_not_reached(); 4470 } 4471 4472 if (copyto_new_reg) { 4473 if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { 4474 /* 4475 * Cross register class move not supported. Sync the 4476 * temp back to its slot and load from there. 4477 */ 4478 temp_sync(s, ts, i_allocated_regs, 0, 0); 4479 tcg_out_ld(s, ts->type, reg, 4480 ts->mem_base->reg, ts->mem_offset); 4481 } 4482 } 4483 new_args[i] = reg; 4484 const_args[i] = 0; 4485 tcg_regset_set_reg(i_allocated_regs, reg); 4486 } 4487 4488 /* mark dead temporaries and free the associated registers */ 4489 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { 4490 if (IS_DEAD_ARG(i)) { 4491 temp_dead(s, arg_temp(op->args[i])); 4492 } 4493 } 4494 4495 if (def->flags & TCG_OPF_COND_BRANCH) { 4496 tcg_reg_alloc_cbranch(s, i_allocated_regs); 4497 } else if (def->flags & TCG_OPF_BB_END) { 4498 tcg_reg_alloc_bb_end(s, i_allocated_regs); 4499 } else { 4500 if (def->flags & TCG_OPF_CALL_CLOBBER) { 4501 /* XXX: permit generic clobber register list ? */ 4502 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 4503 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 4504 tcg_reg_free(s, i, i_allocated_regs); 4505 } 4506 } 4507 } 4508 if (def->flags & TCG_OPF_SIDE_EFFECTS) { 4509 /* sync globals if the op has side effects and might trigger 4510 an exception. */ 4511 sync_globals(s, i_allocated_regs); 4512 } 4513 4514 /* satisfy the output constraints */ 4515 for(k = 0; k < nb_oargs; k++) { 4516 i = def->args_ct[k].sort_index; 4517 arg = op->args[i]; 4518 arg_ct = &def->args_ct[i]; 4519 ts = arg_temp(arg); 4520 4521 /* ENV should not be modified. */ 4522 tcg_debug_assert(!temp_readonly(ts)); 4523 4524 switch (arg_ct->pair) { 4525 case 0: /* not paired */ 4526 if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { 4527 reg = new_args[arg_ct->alias_index]; 4528 } else if (arg_ct->newreg) { 4529 reg = tcg_reg_alloc(s, arg_ct->regs, 4530 i_allocated_regs | o_allocated_regs, 4531 output_pref(op, k), ts->indirect_base); 4532 } else { 4533 reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs, 4534 output_pref(op, k), ts->indirect_base); 4535 } 4536 break; 4537 4538 case 1: /* first of pair */ 4539 tcg_debug_assert(!arg_ct->newreg); 4540 if (arg_ct->oalias) { 4541 reg = new_args[arg_ct->alias_index]; 4542 break; 4543 } 4544 reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs, 4545 output_pref(op, k), ts->indirect_base); 4546 break; 4547 4548 case 2: /* second of pair */ 4549 tcg_debug_assert(!arg_ct->newreg); 4550 if (arg_ct->oalias) { 4551 reg = new_args[arg_ct->alias_index]; 4552 } else { 4553 reg = new_args[arg_ct->pair_index] + 1; 4554 } 4555 break; 4556 4557 case 3: /* first of pair, aliasing with a second input */ 4558 tcg_debug_assert(!arg_ct->newreg); 4559 reg = new_args[arg_ct->pair_index] - 1; 4560 break; 4561 4562 default: 4563 g_assert_not_reached(); 4564 } 4565 tcg_regset_set_reg(o_allocated_regs, reg); 4566 set_temp_val_reg(s, ts, reg); 4567 ts->mem_coherent = 0; 4568 new_args[i] = reg; 4569 } 4570 } 4571 4572 /* emit instruction */ 4573 switch (op->opc) { 4574 case INDEX_op_ext8s_i32: 4575 tcg_out_ext8s(s, TCG_TYPE_I32, new_args[0], new_args[1]); 4576 break; 4577 case INDEX_op_ext8s_i64: 4578 tcg_out_ext8s(s, TCG_TYPE_I64, new_args[0], new_args[1]); 4579 break; 4580 case INDEX_op_ext8u_i32: 4581 case INDEX_op_ext8u_i64: 4582 tcg_out_ext8u(s, new_args[0], new_args[1]); 4583 break; 4584 case INDEX_op_ext16s_i32: 4585 tcg_out_ext16s(s, TCG_TYPE_I32, new_args[0], new_args[1]); 4586 break; 4587 case INDEX_op_ext16s_i64: 4588 tcg_out_ext16s(s, TCG_TYPE_I64, new_args[0], new_args[1]); 4589 break; 4590 case INDEX_op_ext16u_i32: 4591 case INDEX_op_ext16u_i64: 4592 tcg_out_ext16u(s, new_args[0], new_args[1]); 4593 break; 4594 case INDEX_op_ext32s_i64: 4595 tcg_out_ext32s(s, new_args[0], new_args[1]); 4596 break; 4597 case INDEX_op_ext32u_i64: 4598 tcg_out_ext32u(s, new_args[0], new_args[1]); 4599 break; 4600 case INDEX_op_ext_i32_i64: 4601 tcg_out_exts_i32_i64(s, new_args[0], new_args[1]); 4602 break; 4603 case INDEX_op_extu_i32_i64: 4604 tcg_out_extu_i32_i64(s, new_args[0], new_args[1]); 4605 break; 4606 case INDEX_op_extrl_i64_i32: 4607 tcg_out_extrl_i64_i32(s, new_args[0], new_args[1]); 4608 break; 4609 default: 4610 if (def->flags & TCG_OPF_VECTOR) { 4611 tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), 4612 new_args, const_args); 4613 } else { 4614 tcg_out_op(s, op->opc, new_args, const_args); 4615 } 4616 break; 4617 } 4618 4619 /* move the outputs in the correct register if needed */ 4620 for(i = 0; i < nb_oargs; i++) { 4621 ts = arg_temp(op->args[i]); 4622 4623 /* ENV should not be modified. */ 4624 tcg_debug_assert(!temp_readonly(ts)); 4625 4626 if (NEED_SYNC_ARG(i)) { 4627 temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); 4628 } else if (IS_DEAD_ARG(i)) { 4629 temp_dead(s, ts); 4630 } 4631 } 4632 } 4633 4634 static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) 4635 { 4636 const TCGLifeData arg_life = op->life; 4637 TCGTemp *ots, *itsl, *itsh; 4638 TCGType vtype = TCGOP_VECL(op) + TCG_TYPE_V64; 4639 4640 /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ 4641 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 4642 tcg_debug_assert(TCGOP_VECE(op) == MO_64); 4643 4644 ots = arg_temp(op->args[0]); 4645 itsl = arg_temp(op->args[1]); 4646 itsh = arg_temp(op->args[2]); 4647 4648 /* ENV should not be modified. */ 4649 tcg_debug_assert(!temp_readonly(ots)); 4650 4651 /* Allocate the output register now. */ 4652 if (ots->val_type != TEMP_VAL_REG) { 4653 TCGRegSet allocated_regs = s->reserved_regs; 4654 TCGRegSet dup_out_regs = 4655 tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; 4656 TCGReg oreg; 4657 4658 /* Make sure to not spill the input registers. */ 4659 if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) { 4660 tcg_regset_set_reg(allocated_regs, itsl->reg); 4661 } 4662 if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) { 4663 tcg_regset_set_reg(allocated_regs, itsh->reg); 4664 } 4665 4666 oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, 4667 output_pref(op, 0), ots->indirect_base); 4668 set_temp_val_reg(s, ots, oreg); 4669 } 4670 4671 /* Promote dup2 of immediates to dupi_vec. */ 4672 if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) { 4673 uint64_t val = deposit64(itsl->val, 32, 32, itsh->val); 4674 MemOp vece = MO_64; 4675 4676 if (val == dup_const(MO_8, val)) { 4677 vece = MO_8; 4678 } else if (val == dup_const(MO_16, val)) { 4679 vece = MO_16; 4680 } else if (val == dup_const(MO_32, val)) { 4681 vece = MO_32; 4682 } 4683 4684 tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); 4685 goto done; 4686 } 4687 4688 /* If the two inputs form one 64-bit value, try dupm_vec. */ 4689 if (itsl->temp_subindex == HOST_BIG_ENDIAN && 4690 itsh->temp_subindex == !HOST_BIG_ENDIAN && 4691 itsl == itsh + (HOST_BIG_ENDIAN ? 1 : -1)) { 4692 TCGTemp *its = itsl - HOST_BIG_ENDIAN; 4693 4694 temp_sync(s, its + 0, s->reserved_regs, 0, 0); 4695 temp_sync(s, its + 1, s->reserved_regs, 0, 0); 4696 4697 if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, 4698 its->mem_base->reg, its->mem_offset)) { 4699 goto done; 4700 } 4701 } 4702 4703 /* Fall back to generic expansion. */ 4704 return false; 4705 4706 done: 4707 ots->mem_coherent = 0; 4708 if (IS_DEAD_ARG(1)) { 4709 temp_dead(s, itsl); 4710 } 4711 if (IS_DEAD_ARG(2)) { 4712 temp_dead(s, itsh); 4713 } 4714 if (NEED_SYNC_ARG(0)) { 4715 temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); 4716 } else if (IS_DEAD_ARG(0)) { 4717 temp_dead(s, ots); 4718 } 4719 return true; 4720 } 4721 4722 static void load_arg_reg(TCGContext *s, TCGReg reg, TCGTemp *ts, 4723 TCGRegSet allocated_regs) 4724 { 4725 if (ts->val_type == TEMP_VAL_REG) { 4726 if (ts->reg != reg) { 4727 tcg_reg_free(s, reg, allocated_regs); 4728 if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { 4729 /* 4730 * Cross register class move not supported. Sync the 4731 * temp back to its slot and load from there. 4732 */ 4733 temp_sync(s, ts, allocated_regs, 0, 0); 4734 tcg_out_ld(s, ts->type, reg, 4735 ts->mem_base->reg, ts->mem_offset); 4736 } 4737 } 4738 } else { 4739 TCGRegSet arg_set = 0; 4740 4741 tcg_reg_free(s, reg, allocated_regs); 4742 tcg_regset_set_reg(arg_set, reg); 4743 temp_load(s, ts, arg_set, allocated_regs, 0); 4744 } 4745 } 4746 4747 static void load_arg_stk(TCGContext *s, int stk_slot, TCGTemp *ts, 4748 TCGRegSet allocated_regs) 4749 { 4750 /* 4751 * When the destination is on the stack, load up the temp and store. 4752 * If there are many call-saved registers, the temp might live to 4753 * see another use; otherwise it'll be discarded. 4754 */ 4755 temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs, 0); 4756 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, 4757 TCG_TARGET_CALL_STACK_OFFSET + 4758 stk_slot * sizeof(tcg_target_long)); 4759 } 4760 4761 static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l, 4762 TCGTemp *ts, TCGRegSet *allocated_regs) 4763 { 4764 if (REG_P(l)) { 4765 TCGReg reg = tcg_target_call_iarg_regs[l->arg_slot]; 4766 load_arg_reg(s, reg, ts, *allocated_regs); 4767 tcg_regset_set_reg(*allocated_regs, reg); 4768 } else { 4769 load_arg_stk(s, l->arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs), 4770 ts, *allocated_regs); 4771 } 4772 } 4773 4774 static void load_arg_ref(TCGContext *s, int arg_slot, TCGReg ref_base, 4775 intptr_t ref_off, TCGRegSet *allocated_regs) 4776 { 4777 TCGReg reg; 4778 int stk_slot = arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); 4779 4780 if (stk_slot < 0) { 4781 reg = tcg_target_call_iarg_regs[arg_slot]; 4782 tcg_reg_free(s, reg, *allocated_regs); 4783 tcg_out_addi_ptr(s, reg, ref_base, ref_off); 4784 tcg_regset_set_reg(*allocated_regs, reg); 4785 } else { 4786 reg = tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_PTR], 4787 *allocated_regs, 0, false); 4788 tcg_out_addi_ptr(s, reg, ref_base, ref_off); 4789 tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, 4790 TCG_TARGET_CALL_STACK_OFFSET 4791 + stk_slot * sizeof(tcg_target_long)); 4792 } 4793 } 4794 4795 static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) 4796 { 4797 const int nb_oargs = TCGOP_CALLO(op); 4798 const int nb_iargs = TCGOP_CALLI(op); 4799 const TCGLifeData arg_life = op->life; 4800 const TCGHelperInfo *info = tcg_call_info(op); 4801 TCGRegSet allocated_regs = s->reserved_regs; 4802 int i; 4803 4804 /* 4805 * Move inputs into place in reverse order, 4806 * so that we place stacked arguments first. 4807 */ 4808 for (i = nb_iargs - 1; i >= 0; --i) { 4809 const TCGCallArgumentLoc *loc = &info->in[i]; 4810 TCGTemp *ts = arg_temp(op->args[nb_oargs + i]); 4811 4812 switch (loc->kind) { 4813 case TCG_CALL_ARG_NORMAL: 4814 case TCG_CALL_ARG_EXTEND_U: 4815 case TCG_CALL_ARG_EXTEND_S: 4816 load_arg_normal(s, loc, ts, &allocated_regs); 4817 break; 4818 case TCG_CALL_ARG_BY_REF: 4819 load_arg_stk(s, loc->ref_slot, ts, allocated_regs); 4820 load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, 4821 TCG_TARGET_CALL_STACK_OFFSET 4822 + loc->ref_slot * sizeof(tcg_target_long), 4823 &allocated_regs); 4824 break; 4825 case TCG_CALL_ARG_BY_REF_N: 4826 load_arg_stk(s, loc->ref_slot, ts, allocated_regs); 4827 break; 4828 default: 4829 g_assert_not_reached(); 4830 } 4831 } 4832 4833 /* Mark dead temporaries and free the associated registers. */ 4834 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { 4835 if (IS_DEAD_ARG(i)) { 4836 temp_dead(s, arg_temp(op->args[i])); 4837 } 4838 } 4839 4840 /* Clobber call registers. */ 4841 for (i = 0; i < TCG_TARGET_NB_REGS; i++) { 4842 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { 4843 tcg_reg_free(s, i, allocated_regs); 4844 } 4845 } 4846 4847 /* 4848 * Save globals if they might be written by the helper, 4849 * sync them if they might be read. 4850 */ 4851 if (info->flags & TCG_CALL_NO_READ_GLOBALS) { 4852 /* Nothing to do */ 4853 } else if (info->flags & TCG_CALL_NO_WRITE_GLOBALS) { 4854 sync_globals(s, allocated_regs); 4855 } else { 4856 save_globals(s, allocated_regs); 4857 } 4858 4859 /* 4860 * If the ABI passes a pointer to the returned struct as the first 4861 * argument, load that now. Pass a pointer to the output home slot. 4862 */ 4863 if (info->out_kind == TCG_CALL_RET_BY_REF) { 4864 TCGTemp *ts = arg_temp(op->args[0]); 4865 4866 if (!ts->mem_allocated) { 4867 temp_allocate_frame(s, ts); 4868 } 4869 load_arg_ref(s, 0, ts->mem_base->reg, ts->mem_offset, &allocated_regs); 4870 } 4871 4872 tcg_out_call(s, tcg_call_func(op), info); 4873 4874 /* Assign output registers and emit moves if needed. */ 4875 switch (info->out_kind) { 4876 case TCG_CALL_RET_NORMAL: 4877 for (i = 0; i < nb_oargs; i++) { 4878 TCGTemp *ts = arg_temp(op->args[i]); 4879 TCGReg reg = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i); 4880 4881 /* ENV should not be modified. */ 4882 tcg_debug_assert(!temp_readonly(ts)); 4883 4884 set_temp_val_reg(s, ts, reg); 4885 ts->mem_coherent = 0; 4886 } 4887 break; 4888 4889 case TCG_CALL_RET_BY_VEC: 4890 { 4891 TCGTemp *ts = arg_temp(op->args[0]); 4892 4893 tcg_debug_assert(ts->base_type == TCG_TYPE_I128); 4894 tcg_debug_assert(ts->temp_subindex == 0); 4895 if (!ts->mem_allocated) { 4896 temp_allocate_frame(s, ts); 4897 } 4898 tcg_out_st(s, TCG_TYPE_V128, 4899 tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), 4900 ts->mem_base->reg, ts->mem_offset); 4901 } 4902 /* fall through to mark all parts in memory */ 4903 4904 case TCG_CALL_RET_BY_REF: 4905 /* The callee has performed a write through the reference. */ 4906 for (i = 0; i < nb_oargs; i++) { 4907 TCGTemp *ts = arg_temp(op->args[i]); 4908 ts->val_type = TEMP_VAL_MEM; 4909 } 4910 break; 4911 4912 default: 4913 g_assert_not_reached(); 4914 } 4915 4916 /* Flush or discard output registers as needed. */ 4917 for (i = 0; i < nb_oargs; i++) { 4918 TCGTemp *ts = arg_temp(op->args[i]); 4919 if (NEED_SYNC_ARG(i)) { 4920 temp_sync(s, ts, s->reserved_regs, 0, IS_DEAD_ARG(i)); 4921 } else if (IS_DEAD_ARG(i)) { 4922 temp_dead(s, ts); 4923 } 4924 } 4925 } 4926 4927 #ifdef CONFIG_PROFILER 4928 4929 /* avoid copy/paste errors */ 4930 #define PROF_ADD(to, from, field) \ 4931 do { \ 4932 (to)->field += qatomic_read(&((from)->field)); \ 4933 } while (0) 4934 4935 #define PROF_MAX(to, from, field) \ 4936 do { \ 4937 typeof((from)->field) val__ = qatomic_read(&((from)->field)); \ 4938 if (val__ > (to)->field) { \ 4939 (to)->field = val__; \ 4940 } \ 4941 } while (0) 4942 4943 /* Pass in a zero'ed @prof */ 4944 static inline 4945 void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) 4946 { 4947 unsigned int n_ctxs = qatomic_read(&tcg_cur_ctxs); 4948 unsigned int i; 4949 4950 for (i = 0; i < n_ctxs; i++) { 4951 TCGContext *s = qatomic_read(&tcg_ctxs[i]); 4952 const TCGProfile *orig = &s->prof; 4953 4954 if (counters) { 4955 PROF_ADD(prof, orig, cpu_exec_time); 4956 PROF_ADD(prof, orig, tb_count1); 4957 PROF_ADD(prof, orig, tb_count); 4958 PROF_ADD(prof, orig, op_count); 4959 PROF_MAX(prof, orig, op_count_max); 4960 PROF_ADD(prof, orig, temp_count); 4961 PROF_MAX(prof, orig, temp_count_max); 4962 PROF_ADD(prof, orig, del_op_count); 4963 PROF_ADD(prof, orig, code_in_len); 4964 PROF_ADD(prof, orig, code_out_len); 4965 PROF_ADD(prof, orig, search_out_len); 4966 PROF_ADD(prof, orig, interm_time); 4967 PROF_ADD(prof, orig, code_time); 4968 PROF_ADD(prof, orig, la_time); 4969 PROF_ADD(prof, orig, opt_time); 4970 PROF_ADD(prof, orig, restore_count); 4971 PROF_ADD(prof, orig, restore_time); 4972 } 4973 if (table) { 4974 int i; 4975 4976 for (i = 0; i < NB_OPS; i++) { 4977 PROF_ADD(prof, orig, table_op_count[i]); 4978 } 4979 } 4980 } 4981 } 4982 4983 #undef PROF_ADD 4984 #undef PROF_MAX 4985 4986 static void tcg_profile_snapshot_counters(TCGProfile *prof) 4987 { 4988 tcg_profile_snapshot(prof, true, false); 4989 } 4990 4991 static void tcg_profile_snapshot_table(TCGProfile *prof) 4992 { 4993 tcg_profile_snapshot(prof, false, true); 4994 } 4995 4996 void tcg_dump_op_count(GString *buf) 4997 { 4998 TCGProfile prof = {}; 4999 int i; 5000 5001 tcg_profile_snapshot_table(&prof); 5002 for (i = 0; i < NB_OPS; i++) { 5003 g_string_append_printf(buf, "%s %" PRId64 "\n", tcg_op_defs[i].name, 5004 prof.table_op_count[i]); 5005 } 5006 } 5007 5008 int64_t tcg_cpu_exec_time(void) 5009 { 5010 unsigned int n_ctxs = qatomic_read(&tcg_cur_ctxs); 5011 unsigned int i; 5012 int64_t ret = 0; 5013 5014 for (i = 0; i < n_ctxs; i++) { 5015 const TCGContext *s = qatomic_read(&tcg_ctxs[i]); 5016 const TCGProfile *prof = &s->prof; 5017 5018 ret += qatomic_read(&prof->cpu_exec_time); 5019 } 5020 return ret; 5021 } 5022 #else 5023 void tcg_dump_op_count(GString *buf) 5024 { 5025 g_string_append_printf(buf, "[TCG profiler not compiled]\n"); 5026 } 5027 5028 int64_t tcg_cpu_exec_time(void) 5029 { 5030 error_report("%s: TCG profiler not compiled", __func__); 5031 exit(EXIT_FAILURE); 5032 } 5033 #endif 5034 5035 5036 int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start) 5037 { 5038 #ifdef CONFIG_PROFILER 5039 TCGProfile *prof = &s->prof; 5040 #endif 5041 int i, num_insns; 5042 TCGOp *op; 5043 5044 #ifdef CONFIG_PROFILER 5045 { 5046 int n = 0; 5047 5048 QTAILQ_FOREACH(op, &s->ops, link) { 5049 n++; 5050 } 5051 qatomic_set(&prof->op_count, prof->op_count + n); 5052 if (n > prof->op_count_max) { 5053 qatomic_set(&prof->op_count_max, n); 5054 } 5055 5056 n = s->nb_temps; 5057 qatomic_set(&prof->temp_count, prof->temp_count + n); 5058 if (n > prof->temp_count_max) { 5059 qatomic_set(&prof->temp_count_max, n); 5060 } 5061 } 5062 #endif 5063 5064 #ifdef DEBUG_DISAS 5065 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) 5066 && qemu_log_in_addr_range(pc_start))) { 5067 FILE *logfile = qemu_log_trylock(); 5068 if (logfile) { 5069 fprintf(logfile, "OP:\n"); 5070 tcg_dump_ops(s, logfile, false); 5071 fprintf(logfile, "\n"); 5072 qemu_log_unlock(logfile); 5073 } 5074 } 5075 #endif 5076 5077 #ifdef CONFIG_DEBUG_TCG 5078 /* Ensure all labels referenced have been emitted. */ 5079 { 5080 TCGLabel *l; 5081 bool error = false; 5082 5083 QSIMPLEQ_FOREACH(l, &s->labels, next) { 5084 if (unlikely(!l->present) && !QSIMPLEQ_EMPTY(&l->branches)) { 5085 qemu_log_mask(CPU_LOG_TB_OP, 5086 "$L%d referenced but not present.\n", l->id); 5087 error = true; 5088 } 5089 } 5090 assert(!error); 5091 } 5092 #endif 5093 5094 #ifdef CONFIG_PROFILER 5095 qatomic_set(&prof->opt_time, prof->opt_time - profile_getclock()); 5096 #endif 5097 5098 #ifdef USE_TCG_OPTIMIZATIONS 5099 tcg_optimize(s); 5100 #endif 5101 5102 #ifdef CONFIG_PROFILER 5103 qatomic_set(&prof->opt_time, prof->opt_time + profile_getclock()); 5104 qatomic_set(&prof->la_time, prof->la_time - profile_getclock()); 5105 #endif 5106 5107 reachable_code_pass(s); 5108 liveness_pass_0(s); 5109 liveness_pass_1(s); 5110 5111 if (s->nb_indirects > 0) { 5112 #ifdef DEBUG_DISAS 5113 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) 5114 && qemu_log_in_addr_range(pc_start))) { 5115 FILE *logfile = qemu_log_trylock(); 5116 if (logfile) { 5117 fprintf(logfile, "OP before indirect lowering:\n"); 5118 tcg_dump_ops(s, logfile, false); 5119 fprintf(logfile, "\n"); 5120 qemu_log_unlock(logfile); 5121 } 5122 } 5123 #endif 5124 /* Replace indirect temps with direct temps. */ 5125 if (liveness_pass_2(s)) { 5126 /* If changes were made, re-run liveness. */ 5127 liveness_pass_1(s); 5128 } 5129 } 5130 5131 #ifdef CONFIG_PROFILER 5132 qatomic_set(&prof->la_time, prof->la_time + profile_getclock()); 5133 #endif 5134 5135 #ifdef DEBUG_DISAS 5136 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) 5137 && qemu_log_in_addr_range(pc_start))) { 5138 FILE *logfile = qemu_log_trylock(); 5139 if (logfile) { 5140 fprintf(logfile, "OP after optimization and liveness analysis:\n"); 5141 tcg_dump_ops(s, logfile, true); 5142 fprintf(logfile, "\n"); 5143 qemu_log_unlock(logfile); 5144 } 5145 } 5146 #endif 5147 5148 /* Initialize goto_tb jump offsets. */ 5149 tb->jmp_reset_offset[0] = TB_JMP_OFFSET_INVALID; 5150 tb->jmp_reset_offset[1] = TB_JMP_OFFSET_INVALID; 5151 tb->jmp_insn_offset[0] = TB_JMP_OFFSET_INVALID; 5152 tb->jmp_insn_offset[1] = TB_JMP_OFFSET_INVALID; 5153 5154 tcg_reg_alloc_start(s); 5155 5156 /* 5157 * Reset the buffer pointers when restarting after overflow. 5158 * TODO: Move this into translate-all.c with the rest of the 5159 * buffer management. Having only this done here is confusing. 5160 */ 5161 s->code_buf = tcg_splitwx_to_rw(tb->tc.ptr); 5162 s->code_ptr = s->code_buf; 5163 5164 #ifdef TCG_TARGET_NEED_LDST_LABELS 5165 QSIMPLEQ_INIT(&s->ldst_labels); 5166 #endif 5167 #ifdef TCG_TARGET_NEED_POOL_LABELS 5168 s->pool_labels = NULL; 5169 #endif 5170 5171 num_insns = -1; 5172 QTAILQ_FOREACH(op, &s->ops, link) { 5173 TCGOpcode opc = op->opc; 5174 5175 #ifdef CONFIG_PROFILER 5176 qatomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] + 1); 5177 #endif 5178 5179 switch (opc) { 5180 case INDEX_op_mov_i32: 5181 case INDEX_op_mov_i64: 5182 case INDEX_op_mov_vec: 5183 tcg_reg_alloc_mov(s, op); 5184 break; 5185 case INDEX_op_dup_vec: 5186 tcg_reg_alloc_dup(s, op); 5187 break; 5188 case INDEX_op_insn_start: 5189 if (num_insns >= 0) { 5190 size_t off = tcg_current_code_size(s); 5191 s->gen_insn_end_off[num_insns] = off; 5192 /* Assert that we do not overflow our stored offset. */ 5193 assert(s->gen_insn_end_off[num_insns] == off); 5194 } 5195 num_insns++; 5196 for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { 5197 target_ulong a; 5198 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS 5199 a = deposit64(op->args[i * 2], 32, 32, op->args[i * 2 + 1]); 5200 #else 5201 a = op->args[i]; 5202 #endif 5203 s->gen_insn_data[num_insns][i] = a; 5204 } 5205 break; 5206 case INDEX_op_discard: 5207 temp_dead(s, arg_temp(op->args[0])); 5208 break; 5209 case INDEX_op_set_label: 5210 tcg_reg_alloc_bb_end(s, s->reserved_regs); 5211 tcg_out_label(s, arg_label(op->args[0])); 5212 break; 5213 case INDEX_op_call: 5214 tcg_reg_alloc_call(s, op); 5215 break; 5216 case INDEX_op_exit_tb: 5217 tcg_out_exit_tb(s, op->args[0]); 5218 break; 5219 case INDEX_op_goto_tb: 5220 tcg_out_goto_tb(s, op->args[0]); 5221 break; 5222 case INDEX_op_dup2_vec: 5223 if (tcg_reg_alloc_dup2(s, op)) { 5224 break; 5225 } 5226 /* fall through */ 5227 default: 5228 /* Sanity check that we've not introduced any unhandled opcodes. */ 5229 tcg_debug_assert(tcg_op_supported(opc)); 5230 /* Note: in order to speed up the code, it would be much 5231 faster to have specialized register allocator functions for 5232 some common argument patterns */ 5233 tcg_reg_alloc_op(s, op); 5234 break; 5235 } 5236 /* Test for (pending) buffer overflow. The assumption is that any 5237 one operation beginning below the high water mark cannot overrun 5238 the buffer completely. Thus we can test for overflow after 5239 generating code without having to check during generation. */ 5240 if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { 5241 return -1; 5242 } 5243 /* Test for TB overflow, as seen by gen_insn_end_off. */ 5244 if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) { 5245 return -2; 5246 } 5247 } 5248 tcg_debug_assert(num_insns >= 0); 5249 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); 5250 5251 /* Generate TB finalization at the end of block */ 5252 #ifdef TCG_TARGET_NEED_LDST_LABELS 5253 i = tcg_out_ldst_finalize(s); 5254 if (i < 0) { 5255 return i; 5256 } 5257 #endif 5258 #ifdef TCG_TARGET_NEED_POOL_LABELS 5259 i = tcg_out_pool_finalize(s); 5260 if (i < 0) { 5261 return i; 5262 } 5263 #endif 5264 if (!tcg_resolve_relocs(s)) { 5265 return -2; 5266 } 5267 5268 #ifndef CONFIG_TCG_INTERPRETER 5269 /* flush instruction cache */ 5270 flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), 5271 (uintptr_t)s->code_buf, 5272 tcg_ptr_byte_diff(s->code_ptr, s->code_buf)); 5273 #endif 5274 5275 return tcg_current_code_size(s); 5276 } 5277 5278 #ifdef CONFIG_PROFILER 5279 void tcg_dump_info(GString *buf) 5280 { 5281 TCGProfile prof = {}; 5282 const TCGProfile *s; 5283 int64_t tb_count; 5284 int64_t tb_div_count; 5285 int64_t tot; 5286 5287 tcg_profile_snapshot_counters(&prof); 5288 s = &prof; 5289 tb_count = s->tb_count; 5290 tb_div_count = tb_count ? tb_count : 1; 5291 tot = s->interm_time + s->code_time; 5292 5293 g_string_append_printf(buf, "JIT cycles %" PRId64 5294 " (%0.3f s at 2.4 GHz)\n", 5295 tot, tot / 2.4e9); 5296 g_string_append_printf(buf, "translated TBs %" PRId64 5297 " (aborted=%" PRId64 " %0.1f%%)\n", 5298 tb_count, s->tb_count1 - tb_count, 5299 (double)(s->tb_count1 - s->tb_count) 5300 / (s->tb_count1 ? s->tb_count1 : 1) * 100.0); 5301 g_string_append_printf(buf, "avg ops/TB %0.1f max=%d\n", 5302 (double)s->op_count / tb_div_count, s->op_count_max); 5303 g_string_append_printf(buf, "deleted ops/TB %0.2f\n", 5304 (double)s->del_op_count / tb_div_count); 5305 g_string_append_printf(buf, "avg temps/TB %0.2f max=%d\n", 5306 (double)s->temp_count / tb_div_count, 5307 s->temp_count_max); 5308 g_string_append_printf(buf, "avg host code/TB %0.1f\n", 5309 (double)s->code_out_len / tb_div_count); 5310 g_string_append_printf(buf, "avg search data/TB %0.1f\n", 5311 (double)s->search_out_len / tb_div_count); 5312 5313 g_string_append_printf(buf, "cycles/op %0.1f\n", 5314 s->op_count ? (double)tot / s->op_count : 0); 5315 g_string_append_printf(buf, "cycles/in byte %0.1f\n", 5316 s->code_in_len ? (double)tot / s->code_in_len : 0); 5317 g_string_append_printf(buf, "cycles/out byte %0.1f\n", 5318 s->code_out_len ? (double)tot / s->code_out_len : 0); 5319 g_string_append_printf(buf, "cycles/search byte %0.1f\n", 5320 s->search_out_len ? 5321 (double)tot / s->search_out_len : 0); 5322 if (tot == 0) { 5323 tot = 1; 5324 } 5325 g_string_append_printf(buf, " gen_interm time %0.1f%%\n", 5326 (double)s->interm_time / tot * 100.0); 5327 g_string_append_printf(buf, " gen_code time %0.1f%%\n", 5328 (double)s->code_time / tot * 100.0); 5329 g_string_append_printf(buf, "optim./code time %0.1f%%\n", 5330 (double)s->opt_time / (s->code_time ? 5331 s->code_time : 1) 5332 * 100.0); 5333 g_string_append_printf(buf, "liveness/code time %0.1f%%\n", 5334 (double)s->la_time / (s->code_time ? 5335 s->code_time : 1) * 100.0); 5336 g_string_append_printf(buf, "cpu_restore count %" PRId64 "\n", 5337 s->restore_count); 5338 g_string_append_printf(buf, " avg cycles %0.1f\n", 5339 s->restore_count ? 5340 (double)s->restore_time / s->restore_count : 0); 5341 } 5342 #else 5343 void tcg_dump_info(GString *buf) 5344 { 5345 g_string_append_printf(buf, "[TCG profiler not compiled]\n"); 5346 } 5347 #endif 5348 5349 #ifdef ELF_HOST_MACHINE 5350 /* In order to use this feature, the backend needs to do three things: 5351 5352 (1) Define ELF_HOST_MACHINE to indicate both what value to 5353 put into the ELF image and to indicate support for the feature. 5354 5355 (2) Define tcg_register_jit. This should create a buffer containing 5356 the contents of a .debug_frame section that describes the post- 5357 prologue unwind info for the tcg machine. 5358 5359 (3) Call tcg_register_jit_int, with the constructed .debug_frame. 5360 */ 5361 5362 /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */ 5363 typedef enum { 5364 JIT_NOACTION = 0, 5365 JIT_REGISTER_FN, 5366 JIT_UNREGISTER_FN 5367 } jit_actions_t; 5368 5369 struct jit_code_entry { 5370 struct jit_code_entry *next_entry; 5371 struct jit_code_entry *prev_entry; 5372 const void *symfile_addr; 5373 uint64_t symfile_size; 5374 }; 5375 5376 struct jit_descriptor { 5377 uint32_t version; 5378 uint32_t action_flag; 5379 struct jit_code_entry *relevant_entry; 5380 struct jit_code_entry *first_entry; 5381 }; 5382 5383 void __jit_debug_register_code(void) __attribute__((noinline)); 5384 void __jit_debug_register_code(void) 5385 { 5386 asm(""); 5387 } 5388 5389 /* Must statically initialize the version, because GDB may check 5390 the version before we can set it. */ 5391 struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 }; 5392 5393 /* End GDB interface. */ 5394 5395 static int find_string(const char *strtab, const char *str) 5396 { 5397 const char *p = strtab + 1; 5398 5399 while (1) { 5400 if (strcmp(p, str) == 0) { 5401 return p - strtab; 5402 } 5403 p += strlen(p) + 1; 5404 } 5405 } 5406 5407 static void tcg_register_jit_int(const void *buf_ptr, size_t buf_size, 5408 const void *debug_frame, 5409 size_t debug_frame_size) 5410 { 5411 struct __attribute__((packed)) DebugInfo { 5412 uint32_t len; 5413 uint16_t version; 5414 uint32_t abbrev; 5415 uint8_t ptr_size; 5416 uint8_t cu_die; 5417 uint16_t cu_lang; 5418 uintptr_t cu_low_pc; 5419 uintptr_t cu_high_pc; 5420 uint8_t fn_die; 5421 char fn_name[16]; 5422 uintptr_t fn_low_pc; 5423 uintptr_t fn_high_pc; 5424 uint8_t cu_eoc; 5425 }; 5426 5427 struct ElfImage { 5428 ElfW(Ehdr) ehdr; 5429 ElfW(Phdr) phdr; 5430 ElfW(Shdr) shdr[7]; 5431 ElfW(Sym) sym[2]; 5432 struct DebugInfo di; 5433 uint8_t da[24]; 5434 char str[80]; 5435 }; 5436 5437 struct ElfImage *img; 5438 5439 static const struct ElfImage img_template = { 5440 .ehdr = { 5441 .e_ident[EI_MAG0] = ELFMAG0, 5442 .e_ident[EI_MAG1] = ELFMAG1, 5443 .e_ident[EI_MAG2] = ELFMAG2, 5444 .e_ident[EI_MAG3] = ELFMAG3, 5445 .e_ident[EI_CLASS] = ELF_CLASS, 5446 .e_ident[EI_DATA] = ELF_DATA, 5447 .e_ident[EI_VERSION] = EV_CURRENT, 5448 .e_type = ET_EXEC, 5449 .e_machine = ELF_HOST_MACHINE, 5450 .e_version = EV_CURRENT, 5451 .e_phoff = offsetof(struct ElfImage, phdr), 5452 .e_shoff = offsetof(struct ElfImage, shdr), 5453 .e_ehsize = sizeof(ElfW(Shdr)), 5454 .e_phentsize = sizeof(ElfW(Phdr)), 5455 .e_phnum = 1, 5456 .e_shentsize = sizeof(ElfW(Shdr)), 5457 .e_shnum = ARRAY_SIZE(img->shdr), 5458 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1, 5459 #ifdef ELF_HOST_FLAGS 5460 .e_flags = ELF_HOST_FLAGS, 5461 #endif 5462 #ifdef ELF_OSABI 5463 .e_ident[EI_OSABI] = ELF_OSABI, 5464 #endif 5465 }, 5466 .phdr = { 5467 .p_type = PT_LOAD, 5468 .p_flags = PF_X, 5469 }, 5470 .shdr = { 5471 [0] = { .sh_type = SHT_NULL }, 5472 /* Trick: The contents of code_gen_buffer are not present in 5473 this fake ELF file; that got allocated elsewhere. Therefore 5474 we mark .text as SHT_NOBITS (similar to .bss) so that readers 5475 will not look for contents. We can record any address. */ 5476 [1] = { /* .text */ 5477 .sh_type = SHT_NOBITS, 5478 .sh_flags = SHF_EXECINSTR | SHF_ALLOC, 5479 }, 5480 [2] = { /* .debug_info */ 5481 .sh_type = SHT_PROGBITS, 5482 .sh_offset = offsetof(struct ElfImage, di), 5483 .sh_size = sizeof(struct DebugInfo), 5484 }, 5485 [3] = { /* .debug_abbrev */ 5486 .sh_type = SHT_PROGBITS, 5487 .sh_offset = offsetof(struct ElfImage, da), 5488 .sh_size = sizeof(img->da), 5489 }, 5490 [4] = { /* .debug_frame */ 5491 .sh_type = SHT_PROGBITS, 5492 .sh_offset = sizeof(struct ElfImage), 5493 }, 5494 [5] = { /* .symtab */ 5495 .sh_type = SHT_SYMTAB, 5496 .sh_offset = offsetof(struct ElfImage, sym), 5497 .sh_size = sizeof(img->sym), 5498 .sh_info = 1, 5499 .sh_link = ARRAY_SIZE(img->shdr) - 1, 5500 .sh_entsize = sizeof(ElfW(Sym)), 5501 }, 5502 [6] = { /* .strtab */ 5503 .sh_type = SHT_STRTAB, 5504 .sh_offset = offsetof(struct ElfImage, str), 5505 .sh_size = sizeof(img->str), 5506 } 5507 }, 5508 .sym = { 5509 [1] = { /* code_gen_buffer */ 5510 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC), 5511 .st_shndx = 1, 5512 } 5513 }, 5514 .di = { 5515 .len = sizeof(struct DebugInfo) - 4, 5516 .version = 2, 5517 .ptr_size = sizeof(void *), 5518 .cu_die = 1, 5519 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */ 5520 .fn_die = 2, 5521 .fn_name = "code_gen_buffer" 5522 }, 5523 .da = { 5524 1, /* abbrev number (the cu) */ 5525 0x11, 1, /* DW_TAG_compile_unit, has children */ 5526 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */ 5527 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 5528 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 5529 0, 0, /* end of abbrev */ 5530 2, /* abbrev number (the fn) */ 5531 0x2e, 0, /* DW_TAG_subprogram, no children */ 5532 0x3, 0x8, /* DW_AT_name, DW_FORM_string */ 5533 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ 5534 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ 5535 0, 0, /* end of abbrev */ 5536 0 /* no more abbrev */ 5537 }, 5538 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0" 5539 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer", 5540 }; 5541 5542 /* We only need a single jit entry; statically allocate it. */ 5543 static struct jit_code_entry one_entry; 5544 5545 uintptr_t buf = (uintptr_t)buf_ptr; 5546 size_t img_size = sizeof(struct ElfImage) + debug_frame_size; 5547 DebugFrameHeader *dfh; 5548 5549 img = g_malloc(img_size); 5550 *img = img_template; 5551 5552 img->phdr.p_vaddr = buf; 5553 img->phdr.p_paddr = buf; 5554 img->phdr.p_memsz = buf_size; 5555 5556 img->shdr[1].sh_name = find_string(img->str, ".text"); 5557 img->shdr[1].sh_addr = buf; 5558 img->shdr[1].sh_size = buf_size; 5559 5560 img->shdr[2].sh_name = find_string(img->str, ".debug_info"); 5561 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev"); 5562 5563 img->shdr[4].sh_name = find_string(img->str, ".debug_frame"); 5564 img->shdr[4].sh_size = debug_frame_size; 5565 5566 img->shdr[5].sh_name = find_string(img->str, ".symtab"); 5567 img->shdr[6].sh_name = find_string(img->str, ".strtab"); 5568 5569 img->sym[1].st_name = find_string(img->str, "code_gen_buffer"); 5570 img->sym[1].st_value = buf; 5571 img->sym[1].st_size = buf_size; 5572 5573 img->di.cu_low_pc = buf; 5574 img->di.cu_high_pc = buf + buf_size; 5575 img->di.fn_low_pc = buf; 5576 img->di.fn_high_pc = buf + buf_size; 5577 5578 dfh = (DebugFrameHeader *)(img + 1); 5579 memcpy(dfh, debug_frame, debug_frame_size); 5580 dfh->fde.func_start = buf; 5581 dfh->fde.func_len = buf_size; 5582 5583 #ifdef DEBUG_JIT 5584 /* Enable this block to be able to debug the ELF image file creation. 5585 One can use readelf, objdump, or other inspection utilities. */ 5586 { 5587 g_autofree char *jit = g_strdup_printf("%s/qemu.jit", g_get_tmp_dir()); 5588 FILE *f = fopen(jit, "w+b"); 5589 if (f) { 5590 if (fwrite(img, img_size, 1, f) != img_size) { 5591 /* Avoid stupid unused return value warning for fwrite. */ 5592 } 5593 fclose(f); 5594 } 5595 } 5596 #endif 5597 5598 one_entry.symfile_addr = img; 5599 one_entry.symfile_size = img_size; 5600 5601 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN; 5602 __jit_debug_descriptor.relevant_entry = &one_entry; 5603 __jit_debug_descriptor.first_entry = &one_entry; 5604 __jit_debug_register_code(); 5605 } 5606 #else 5607 /* No support for the feature. Provide the entry point expected by exec.c, 5608 and implement the internal function we declared earlier. */ 5609 5610 static void tcg_register_jit_int(const void *buf, size_t size, 5611 const void *debug_frame, 5612 size_t debug_frame_size) 5613 { 5614 } 5615 5616 void tcg_register_jit(const void *buf, size_t buf_size) 5617 { 5618 } 5619 #endif /* ELF_HOST_MACHINE */ 5620 5621 #if !TCG_TARGET_MAYBE_vec 5622 void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...) 5623 { 5624 g_assert_not_reached(); 5625 } 5626 #endif 5627