1 /* 2 * QTest testcase for the M25P80 Flash (Using the Aspeed SPI 3 * Controller) 4 * 5 * Copyright (C) 2016 IBM Corp. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/bswap.h" 28 #include "libqtest-single.h" 29 #include "qemu/bitops.h" 30 31 /* 32 * ASPEED SPI Controller registers 33 */ 34 #define R_CONF 0x00 35 #define CONF_ENABLE_W0 (1 << 16) 36 #define R_CE_CTRL 0x04 37 #define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ 38 #define R_CTRL0 0x10 39 #define CTRL_CE_STOP_ACTIVE (1 << 2) 40 #define CTRL_READMODE 0x0 41 #define CTRL_FREADMODE 0x1 42 #define CTRL_WRITEMODE 0x2 43 #define CTRL_USERMODE 0x3 44 #define SR_WEL BIT(1) 45 46 #define ASPEED_FMC_BASE 0x1E620000 47 #define ASPEED_FLASH_BASE 0x20000000 48 49 /* 50 * Flash commands 51 */ 52 enum { 53 JEDEC_READ = 0x9f, 54 RDSR = 0x5, 55 WRDI = 0x4, 56 BULK_ERASE = 0xc7, 57 READ = 0x03, 58 PP = 0x02, 59 WREN = 0x6, 60 RESET_ENABLE = 0x66, 61 RESET_MEMORY = 0x99, 62 EN_4BYTE_ADDR = 0xB7, 63 ERASE_SECTOR = 0xd8, 64 }; 65 66 #define FLASH_JEDEC 0x20ba19 /* n25q256a */ 67 #define FLASH_SIZE (32 * 1024 * 1024) 68 69 #define FLASH_PAGE_SIZE 256 70 71 /* 72 * Use an explicit bswap for the values read/wrote to the flash region 73 * as they are BE and the Aspeed CPU is LE. 74 */ 75 static inline uint32_t make_be32(uint32_t data) 76 { 77 return bswap32(data); 78 } 79 80 static void spi_conf(uint32_t value) 81 { 82 uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF); 83 84 conf |= value; 85 writel(ASPEED_FMC_BASE + R_CONF, conf); 86 } 87 88 static void spi_conf_remove(uint32_t value) 89 { 90 uint32_t conf = readl(ASPEED_FMC_BASE + R_CONF); 91 92 conf &= ~value; 93 writel(ASPEED_FMC_BASE + R_CONF, conf); 94 } 95 96 static void spi_ce_ctrl(uint32_t value) 97 { 98 uint32_t conf = readl(ASPEED_FMC_BASE + R_CE_CTRL); 99 100 conf |= value; 101 writel(ASPEED_FMC_BASE + R_CE_CTRL, conf); 102 } 103 104 static void spi_ctrl_setmode(uint8_t mode, uint8_t cmd) 105 { 106 uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0); 107 ctrl &= ~(CTRL_USERMODE | 0xff << 16); 108 ctrl |= mode | (cmd << 16); 109 writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); 110 } 111 112 static void spi_ctrl_start_user(void) 113 { 114 uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0); 115 116 ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; 117 writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); 118 119 ctrl &= ~CTRL_CE_STOP_ACTIVE; 120 writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); 121 } 122 123 static void spi_ctrl_stop_user(void) 124 { 125 uint32_t ctrl = readl(ASPEED_FMC_BASE + R_CTRL0); 126 127 ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; 128 writel(ASPEED_FMC_BASE + R_CTRL0, ctrl); 129 } 130 131 static void flash_reset(void) 132 { 133 spi_conf(CONF_ENABLE_W0); 134 135 spi_ctrl_start_user(); 136 writeb(ASPEED_FLASH_BASE, RESET_ENABLE); 137 writeb(ASPEED_FLASH_BASE, RESET_MEMORY); 138 spi_ctrl_stop_user(); 139 140 spi_conf_remove(CONF_ENABLE_W0); 141 } 142 143 static void test_read_jedec(void) 144 { 145 uint32_t jedec = 0x0; 146 147 spi_conf(CONF_ENABLE_W0); 148 149 spi_ctrl_start_user(); 150 writeb(ASPEED_FLASH_BASE, JEDEC_READ); 151 jedec |= readb(ASPEED_FLASH_BASE) << 16; 152 jedec |= readb(ASPEED_FLASH_BASE) << 8; 153 jedec |= readb(ASPEED_FLASH_BASE); 154 spi_ctrl_stop_user(); 155 156 flash_reset(); 157 158 g_assert_cmphex(jedec, ==, FLASH_JEDEC); 159 } 160 161 static void read_page(uint32_t addr, uint32_t *page) 162 { 163 int i; 164 165 spi_ctrl_start_user(); 166 167 writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); 168 writeb(ASPEED_FLASH_BASE, READ); 169 writel(ASPEED_FLASH_BASE, make_be32(addr)); 170 171 /* Continuous read are supported */ 172 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 173 page[i] = make_be32(readl(ASPEED_FLASH_BASE)); 174 } 175 spi_ctrl_stop_user(); 176 } 177 178 static void read_page_mem(uint32_t addr, uint32_t *page) 179 { 180 int i; 181 182 /* move out USER mode to use direct reads from the AHB bus */ 183 spi_ctrl_setmode(CTRL_READMODE, READ); 184 185 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 186 page[i] = make_be32(readl(ASPEED_FLASH_BASE + addr + i * 4)); 187 } 188 } 189 190 static void test_erase_sector(void) 191 { 192 uint32_t some_page_addr = 0x600 * FLASH_PAGE_SIZE; 193 uint32_t page[FLASH_PAGE_SIZE / 4]; 194 int i; 195 196 spi_conf(CONF_ENABLE_W0); 197 198 spi_ctrl_start_user(); 199 writeb(ASPEED_FLASH_BASE, WREN); 200 writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); 201 writeb(ASPEED_FLASH_BASE, ERASE_SECTOR); 202 writel(ASPEED_FLASH_BASE, make_be32(some_page_addr)); 203 spi_ctrl_stop_user(); 204 205 /* Previous page should be full of zeroes as backend is not 206 * initialized */ 207 read_page(some_page_addr - FLASH_PAGE_SIZE, page); 208 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 209 g_assert_cmphex(page[i], ==, 0x0); 210 } 211 212 /* But this one was erased */ 213 read_page(some_page_addr, page); 214 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 215 g_assert_cmphex(page[i], ==, 0xffffffff); 216 } 217 218 flash_reset(); 219 } 220 221 static void test_erase_all(void) 222 { 223 uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE; 224 uint32_t page[FLASH_PAGE_SIZE / 4]; 225 int i; 226 227 spi_conf(CONF_ENABLE_W0); 228 229 /* Check some random page. Should be full of zeroes as backend is 230 * not initialized */ 231 read_page(some_page_addr, page); 232 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 233 g_assert_cmphex(page[i], ==, 0x0); 234 } 235 236 spi_ctrl_start_user(); 237 writeb(ASPEED_FLASH_BASE, WREN); 238 writeb(ASPEED_FLASH_BASE, BULK_ERASE); 239 spi_ctrl_stop_user(); 240 241 /* Recheck that some random page */ 242 read_page(some_page_addr, page); 243 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 244 g_assert_cmphex(page[i], ==, 0xffffffff); 245 } 246 247 flash_reset(); 248 } 249 250 static void test_write_page(void) 251 { 252 uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */ 253 uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE; 254 uint32_t page[FLASH_PAGE_SIZE / 4]; 255 int i; 256 257 spi_conf(CONF_ENABLE_W0); 258 259 spi_ctrl_start_user(); 260 writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); 261 writeb(ASPEED_FLASH_BASE, WREN); 262 writeb(ASPEED_FLASH_BASE, PP); 263 writel(ASPEED_FLASH_BASE, make_be32(my_page_addr)); 264 265 /* Fill the page with its own addresses */ 266 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 267 writel(ASPEED_FLASH_BASE, make_be32(my_page_addr + i * 4)); 268 } 269 spi_ctrl_stop_user(); 270 271 /* Check what was written */ 272 read_page(my_page_addr, page); 273 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 274 g_assert_cmphex(page[i], ==, my_page_addr + i * 4); 275 } 276 277 /* Check some other page. It should be full of 0xff */ 278 read_page(some_page_addr, page); 279 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 280 g_assert_cmphex(page[i], ==, 0xffffffff); 281 } 282 283 flash_reset(); 284 } 285 286 static void test_read_page_mem(void) 287 { 288 uint32_t my_page_addr = 0x14000 * FLASH_PAGE_SIZE; /* beyond 16MB */ 289 uint32_t some_page_addr = 0x15000 * FLASH_PAGE_SIZE; 290 uint32_t page[FLASH_PAGE_SIZE / 4]; 291 int i; 292 293 /* Enable 4BYTE mode for controller. This is should be strapped by 294 * HW for CE0 anyhow. 295 */ 296 spi_ce_ctrl(1 << CRTL_EXTENDED0); 297 298 /* Enable 4BYTE mode for flash. */ 299 spi_conf(CONF_ENABLE_W0); 300 spi_ctrl_start_user(); 301 writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); 302 spi_ctrl_stop_user(); 303 spi_conf_remove(CONF_ENABLE_W0); 304 305 /* Check what was written */ 306 read_page_mem(my_page_addr, page); 307 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 308 g_assert_cmphex(page[i], ==, my_page_addr + i * 4); 309 } 310 311 /* Check some other page. It should be full of 0xff */ 312 read_page_mem(some_page_addr, page); 313 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 314 g_assert_cmphex(page[i], ==, 0xffffffff); 315 } 316 317 flash_reset(); 318 } 319 320 static void test_write_page_mem(void) 321 { 322 uint32_t my_page_addr = 0x15000 * FLASH_PAGE_SIZE; 323 uint32_t page[FLASH_PAGE_SIZE / 4]; 324 int i; 325 326 /* Enable 4BYTE mode for controller. This is should be strapped by 327 * HW for CE0 anyhow. 328 */ 329 spi_ce_ctrl(1 << CRTL_EXTENDED0); 330 331 /* Enable 4BYTE mode for flash. */ 332 spi_conf(CONF_ENABLE_W0); 333 spi_ctrl_start_user(); 334 writeb(ASPEED_FLASH_BASE, EN_4BYTE_ADDR); 335 writeb(ASPEED_FLASH_BASE, WREN); 336 spi_ctrl_stop_user(); 337 338 /* move out USER mode to use direct writes to the AHB bus */ 339 spi_ctrl_setmode(CTRL_WRITEMODE, PP); 340 341 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 342 writel(ASPEED_FLASH_BASE + my_page_addr + i * 4, 343 make_be32(my_page_addr + i * 4)); 344 } 345 346 /* Check what was written */ 347 read_page_mem(my_page_addr, page); 348 for (i = 0; i < FLASH_PAGE_SIZE / 4; i++) { 349 g_assert_cmphex(page[i], ==, my_page_addr + i * 4); 350 } 351 352 flash_reset(); 353 } 354 355 static void test_read_status_reg(void) 356 { 357 uint8_t r; 358 359 spi_conf(CONF_ENABLE_W0); 360 361 spi_ctrl_start_user(); 362 writeb(ASPEED_FLASH_BASE, RDSR); 363 r = readb(ASPEED_FLASH_BASE); 364 spi_ctrl_stop_user(); 365 366 g_assert_cmphex(r & SR_WEL, ==, 0); 367 g_assert(!qtest_qom_get_bool 368 (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); 369 370 spi_ctrl_start_user(); 371 writeb(ASPEED_FLASH_BASE, WREN); 372 writeb(ASPEED_FLASH_BASE, RDSR); 373 r = readb(ASPEED_FLASH_BASE); 374 spi_ctrl_stop_user(); 375 376 g_assert_cmphex(r & SR_WEL, ==, SR_WEL); 377 g_assert(qtest_qom_get_bool 378 (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); 379 380 spi_ctrl_start_user(); 381 writeb(ASPEED_FLASH_BASE, WRDI); 382 writeb(ASPEED_FLASH_BASE, RDSR); 383 r = readb(ASPEED_FLASH_BASE); 384 spi_ctrl_stop_user(); 385 386 g_assert_cmphex(r & SR_WEL, ==, 0); 387 g_assert(!qtest_qom_get_bool 388 (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enable")); 389 390 flash_reset(); 391 } 392 393 static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX"; 394 395 int main(int argc, char **argv) 396 { 397 int ret; 398 int fd; 399 400 g_test_init(&argc, &argv, NULL); 401 402 fd = mkstemp(tmp_path); 403 g_assert(fd >= 0); 404 ret = ftruncate(fd, FLASH_SIZE); 405 g_assert(ret == 0); 406 close(fd); 407 408 global_qtest = qtest_initf("-m 256 -machine palmetto-bmc " 409 "-drive file=%s,format=raw,if=mtd", 410 tmp_path); 411 412 qtest_add_func("/ast2400/smc/read_jedec", test_read_jedec); 413 qtest_add_func("/ast2400/smc/erase_sector", test_erase_sector); 414 qtest_add_func("/ast2400/smc/erase_all", test_erase_all); 415 qtest_add_func("/ast2400/smc/write_page", test_write_page); 416 qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem); 417 qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem); 418 qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg); 419 420 ret = g_test_run(); 421 422 qtest_quit(global_qtest); 423 unlink(tmp_path); 424 return ret; 425 } 426