1 /* 2 * QTests for Nuvoton NPCM7xx EMC Modules. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "libqos/libqos.h" 19 #include "qapi/qmp/qdict.h" 20 #include "qapi/qmp/qnum.h" 21 #include "qemu/bitops.h" 22 #include "qemu/iov.h" 23 24 /* Name of the emc device. */ 25 #define TYPE_NPCM7XX_EMC "npcm7xx-emc" 26 27 /* Timeout for various operations, in seconds. */ 28 #define TIMEOUT_SECONDS 10 29 30 /* Address in memory of the descriptor. */ 31 #define DESC_ADDR (1 << 20) /* 1 MiB */ 32 33 /* Address in memory of the data packet. */ 34 #define DATA_ADDR (DESC_ADDR + 4096) 35 36 #define CRC_LENGTH 4 37 38 #define NUM_TX_DESCRIPTORS 3 39 #define NUM_RX_DESCRIPTORS 2 40 41 /* Size of tx,rx test buffers. */ 42 #define TX_DATA_LEN 64 43 #define RX_DATA_LEN 64 44 45 #define TX_STEP_COUNT 10000 46 #define RX_STEP_COUNT 10000 47 48 /* 32-bit register indices. */ 49 typedef enum NPCM7xxPWMRegister { 50 /* Control registers. */ 51 REG_CAMCMR, 52 REG_CAMEN, 53 54 /* There are 16 CAMn[ML] registers. */ 55 REG_CAMM_BASE, 56 REG_CAML_BASE, 57 58 REG_TXDLSA = 0x22, 59 REG_RXDLSA, 60 REG_MCMDR, 61 REG_MIID, 62 REG_MIIDA, 63 REG_FFTCR, 64 REG_TSDR, 65 REG_RSDR, 66 REG_DMARFC, 67 REG_MIEN, 68 69 /* Status registers. */ 70 REG_MISTA, 71 REG_MGSTA, 72 REG_MPCNT, 73 REG_MRPC, 74 REG_MRPCC, 75 REG_MREPC, 76 REG_DMARFS, 77 REG_CTXDSA, 78 REG_CTXBSA, 79 REG_CRXDSA, 80 REG_CRXBSA, 81 82 NPCM7XX_NUM_EMC_REGS, 83 } NPCM7xxPWMRegister; 84 85 enum { NUM_CAMML_REGS = 16 }; 86 87 /* REG_CAMCMR fields */ 88 /* Enable CAM Compare */ 89 #define REG_CAMCMR_ECMP (1 << 4) 90 /* Accept Unicast Packet */ 91 #define REG_CAMCMR_AUP (1 << 0) 92 93 /* REG_MCMDR fields */ 94 /* Software Reset */ 95 #define REG_MCMDR_SWR (1 << 24) 96 /* Frame Transmission On */ 97 #define REG_MCMDR_TXON (1 << 8) 98 /* Accept Long Packet */ 99 #define REG_MCMDR_ALP (1 << 1) 100 /* Frame Reception On */ 101 #define REG_MCMDR_RXON (1 << 0) 102 103 /* REG_MIEN fields */ 104 /* Enable Transmit Completion Interrupt */ 105 #define REG_MIEN_ENTXCP (1 << 18) 106 /* Enable Transmit Interrupt */ 107 #define REG_MIEN_ENTXINTR (1 << 16) 108 /* Enable Receive Good Interrupt */ 109 #define REG_MIEN_ENRXGD (1 << 4) 110 /* ENable Receive Interrupt */ 111 #define REG_MIEN_ENRXINTR (1 << 0) 112 113 /* REG_MISTA fields */ 114 /* Transmit Bus Error Interrupt */ 115 #define REG_MISTA_TXBERR (1 << 24) 116 /* Transmit Descriptor Unavailable Interrupt */ 117 #define REG_MISTA_TDU (1 << 23) 118 /* Transmit Completion Interrupt */ 119 #define REG_MISTA_TXCP (1 << 18) 120 /* Transmit Interrupt */ 121 #define REG_MISTA_TXINTR (1 << 16) 122 /* Receive Bus Error Interrupt */ 123 #define REG_MISTA_RXBERR (1 << 11) 124 /* Receive Descriptor Unavailable Interrupt */ 125 #define REG_MISTA_RDU (1 << 10) 126 /* DMA Early Notification Interrupt */ 127 #define REG_MISTA_DENI (1 << 9) 128 /* Maximum Frame Length Interrupt */ 129 #define REG_MISTA_DFOI (1 << 8) 130 /* Receive Good Interrupt */ 131 #define REG_MISTA_RXGD (1 << 4) 132 /* Packet Too Long Interrupt */ 133 #define REG_MISTA_PTLE (1 << 3) 134 /* Receive Interrupt */ 135 #define REG_MISTA_RXINTR (1 << 0) 136 137 typedef struct NPCM7xxEMCTxDesc NPCM7xxEMCTxDesc; 138 typedef struct NPCM7xxEMCRxDesc NPCM7xxEMCRxDesc; 139 140 struct NPCM7xxEMCTxDesc { 141 uint32_t flags; 142 uint32_t txbsa; 143 uint32_t status_and_length; 144 uint32_t ntxdsa; 145 }; 146 147 struct NPCM7xxEMCRxDesc { 148 uint32_t status_and_length; 149 uint32_t rxbsa; 150 uint32_t reserved; 151 uint32_t nrxdsa; 152 }; 153 154 /* NPCM7xxEMCTxDesc.flags values */ 155 /* Owner: 0 = cpu, 1 = emc */ 156 #define TX_DESC_FLAG_OWNER_MASK (1 << 31) 157 /* Transmit interrupt enable */ 158 #define TX_DESC_FLAG_INTEN (1 << 2) 159 160 /* NPCM7xxEMCTxDesc.status_and_length values */ 161 /* Transmission complete */ 162 #define TX_DESC_STATUS_TXCP (1 << 19) 163 /* Transmit interrupt */ 164 #define TX_DESC_STATUS_TXINTR (1 << 16) 165 166 /* NPCM7xxEMCRxDesc.status_and_length values */ 167 /* Owner: 0b00 = cpu, 0b10 = emc */ 168 #define RX_DESC_STATUS_OWNER_SHIFT 30 169 #define RX_DESC_STATUS_OWNER_MASK 0xc0000000 170 /* Frame Reception Complete */ 171 #define RX_DESC_STATUS_RXGD (1 << 20) 172 /* Packet too long */ 173 #define RX_DESC_STATUS_PTLE (1 << 19) 174 /* Receive Interrupt */ 175 #define RX_DESC_STATUS_RXINTR (1 << 16) 176 177 #define RX_DESC_PKT_LEN(word) ((uint32_t) (word) & 0xffff) 178 179 typedef struct EMCModule { 180 int rx_irq; 181 int tx_irq; 182 uint64_t base_addr; 183 } EMCModule; 184 185 typedef struct TestData { 186 const EMCModule *module; 187 } TestData; 188 189 static const EMCModule emc_module_list[] = { 190 { 191 .rx_irq = 15, 192 .tx_irq = 16, 193 .base_addr = 0xf0825000 194 }, 195 { 196 .rx_irq = 114, 197 .tx_irq = 115, 198 .base_addr = 0xf0826000 199 } 200 }; 201 202 /* Returns the index of the EMC module. */ 203 static int emc_module_index(const EMCModule *mod) 204 { 205 ptrdiff_t diff = mod - emc_module_list; 206 207 g_assert_true(diff >= 0 && diff < ARRAY_SIZE(emc_module_list)); 208 209 return diff; 210 } 211 212 static void packet_test_clear(void *sockets) 213 { 214 int *test_sockets = sockets; 215 216 close(test_sockets[0]); 217 g_free(test_sockets); 218 } 219 220 static int *packet_test_init(int module_num, GString *cmd_line) 221 { 222 int *test_sockets = g_new(int, 2); 223 int ret = socketpair(PF_UNIX, SOCK_STREAM, 0, test_sockets); 224 g_assert_cmpint(ret, != , -1); 225 226 /* 227 * KISS and use -nic. We specify two nics (both emc{0,1}) because there's 228 * currently no way to specify only emc1: The driver implicitly relies on 229 * emc[i] == nd_table[i]. 230 */ 231 if (module_num == 0) { 232 g_string_append_printf(cmd_line, 233 " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " " 234 " -nic user,model=" TYPE_NPCM7XX_EMC " ", 235 test_sockets[1]); 236 } else { 237 g_string_append_printf(cmd_line, 238 " -nic user,model=" TYPE_NPCM7XX_EMC " " 239 " -nic socket,fd=%d,model=" TYPE_NPCM7XX_EMC " ", 240 test_sockets[1]); 241 } 242 243 g_test_queue_destroy(packet_test_clear, test_sockets); 244 return test_sockets; 245 } 246 247 static uint32_t emc_read(QTestState *qts, const EMCModule *mod, 248 NPCM7xxPWMRegister regno) 249 { 250 return qtest_readl(qts, mod->base_addr + regno * sizeof(uint32_t)); 251 } 252 253 static void emc_write(QTestState *qts, const EMCModule *mod, 254 NPCM7xxPWMRegister regno, uint32_t value) 255 { 256 qtest_writel(qts, mod->base_addr + regno * sizeof(uint32_t), value); 257 } 258 259 static void emc_read_tx_desc(QTestState *qts, uint32_t addr, 260 NPCM7xxEMCTxDesc *desc) 261 { 262 qtest_memread(qts, addr, desc, sizeof(*desc)); 263 desc->flags = le32_to_cpu(desc->flags); 264 desc->txbsa = le32_to_cpu(desc->txbsa); 265 desc->status_and_length = le32_to_cpu(desc->status_and_length); 266 desc->ntxdsa = le32_to_cpu(desc->ntxdsa); 267 } 268 269 static void emc_write_tx_desc(QTestState *qts, const NPCM7xxEMCTxDesc *desc, 270 uint32_t addr) 271 { 272 NPCM7xxEMCTxDesc le_desc; 273 274 le_desc.flags = cpu_to_le32(desc->flags); 275 le_desc.txbsa = cpu_to_le32(desc->txbsa); 276 le_desc.status_and_length = cpu_to_le32(desc->status_and_length); 277 le_desc.ntxdsa = cpu_to_le32(desc->ntxdsa); 278 qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); 279 } 280 281 static void emc_read_rx_desc(QTestState *qts, uint32_t addr, 282 NPCM7xxEMCRxDesc *desc) 283 { 284 qtest_memread(qts, addr, desc, sizeof(*desc)); 285 desc->status_and_length = le32_to_cpu(desc->status_and_length); 286 desc->rxbsa = le32_to_cpu(desc->rxbsa); 287 desc->reserved = le32_to_cpu(desc->reserved); 288 desc->nrxdsa = le32_to_cpu(desc->nrxdsa); 289 } 290 291 static void emc_write_rx_desc(QTestState *qts, const NPCM7xxEMCRxDesc *desc, 292 uint32_t addr) 293 { 294 NPCM7xxEMCRxDesc le_desc; 295 296 le_desc.status_and_length = cpu_to_le32(desc->status_and_length); 297 le_desc.rxbsa = cpu_to_le32(desc->rxbsa); 298 le_desc.reserved = cpu_to_le32(desc->reserved); 299 le_desc.nrxdsa = cpu_to_le32(desc->nrxdsa); 300 qtest_memwrite(qts, addr, &le_desc, sizeof(le_desc)); 301 } 302 303 /* 304 * Reset the EMC module. 305 * The module must be reset before, e.g., TXDLSA,RXDLSA are changed. 306 */ 307 static bool emc_soft_reset(QTestState *qts, const EMCModule *mod) 308 { 309 uint32_t val; 310 uint64_t end_time; 311 312 emc_write(qts, mod, REG_MCMDR, REG_MCMDR_SWR); 313 314 /* 315 * Wait for device to reset as the linux driver does. 316 * During reset the AHB reads 0 for all registers. So first wait for 317 * something that resets to non-zero, and then wait for SWR becoming 0. 318 */ 319 end_time = g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; 320 321 do { 322 qtest_clock_step(qts, 100); 323 val = emc_read(qts, mod, REG_FFTCR); 324 } while (val == 0 && g_get_monotonic_time() < end_time); 325 if (val != 0) { 326 do { 327 qtest_clock_step(qts, 100); 328 val = emc_read(qts, mod, REG_MCMDR); 329 if ((val & REG_MCMDR_SWR) == 0) { 330 /* 331 * N.B. The CAMs have been reset here, so macaddr matching of 332 * incoming packets will not work. 333 */ 334 return true; 335 } 336 } while (g_get_monotonic_time() < end_time); 337 } 338 339 g_message("%s: Timeout expired", __func__); 340 return false; 341 } 342 343 /* Check emc registers are reset to default value. */ 344 static void test_init(gconstpointer test_data) 345 { 346 const TestData *td = test_data; 347 const EMCModule *mod = td->module; 348 QTestState *qts = qtest_init("-machine quanta-gsj"); 349 int i; 350 351 #define CHECK_REG(regno, value) \ 352 do { \ 353 g_assert_cmphex(emc_read(qts, mod, (regno)), ==, (value)); \ 354 } while (0) 355 356 CHECK_REG(REG_CAMCMR, 0); 357 CHECK_REG(REG_CAMEN, 0); 358 CHECK_REG(REG_TXDLSA, 0xfffffffc); 359 CHECK_REG(REG_RXDLSA, 0xfffffffc); 360 CHECK_REG(REG_MCMDR, 0); 361 CHECK_REG(REG_MIID, 0); 362 CHECK_REG(REG_MIIDA, 0x00900000); 363 CHECK_REG(REG_FFTCR, 0x0101); 364 CHECK_REG(REG_DMARFC, 0x0800); 365 CHECK_REG(REG_MIEN, 0); 366 CHECK_REG(REG_MISTA, 0); 367 CHECK_REG(REG_MGSTA, 0); 368 CHECK_REG(REG_MPCNT, 0x7fff); 369 CHECK_REG(REG_MRPC, 0); 370 CHECK_REG(REG_MRPCC, 0); 371 CHECK_REG(REG_MREPC, 0); 372 CHECK_REG(REG_DMARFS, 0); 373 CHECK_REG(REG_CTXDSA, 0); 374 CHECK_REG(REG_CTXBSA, 0); 375 CHECK_REG(REG_CRXDSA, 0); 376 CHECK_REG(REG_CRXBSA, 0); 377 378 #undef CHECK_REG 379 380 for (i = 0; i < NUM_CAMML_REGS; ++i) { 381 g_assert_cmpuint(emc_read(qts, mod, REG_CAMM_BASE + i * 2), ==, 382 0); 383 g_assert_cmpuint(emc_read(qts, mod, REG_CAML_BASE + i * 2), ==, 384 0); 385 } 386 387 qtest_quit(qts); 388 } 389 390 static bool emc_wait_irq(QTestState *qts, const EMCModule *mod, int step, 391 bool is_tx) 392 { 393 uint64_t end_time = 394 g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; 395 396 do { 397 if (qtest_get_irq(qts, is_tx ? mod->tx_irq : mod->rx_irq)) { 398 return true; 399 } 400 qtest_clock_step(qts, step); 401 } while (g_get_monotonic_time() < end_time); 402 403 g_message("%s: Timeout expired", __func__); 404 return false; 405 } 406 407 static bool emc_wait_mista(QTestState *qts, const EMCModule *mod, int step, 408 uint32_t flag) 409 { 410 uint64_t end_time = 411 g_get_monotonic_time() + TIMEOUT_SECONDS * G_TIME_SPAN_SECOND; 412 413 do { 414 uint32_t mista = emc_read(qts, mod, REG_MISTA); 415 if (mista & flag) { 416 return true; 417 } 418 qtest_clock_step(qts, step); 419 } while (g_get_monotonic_time() < end_time); 420 421 g_message("%s: Timeout expired", __func__); 422 return false; 423 } 424 425 static bool wait_socket_readable(int fd) 426 { 427 fd_set read_fds; 428 struct timeval tv; 429 int rv; 430 431 FD_ZERO(&read_fds); 432 FD_SET(fd, &read_fds); 433 tv.tv_sec = TIMEOUT_SECONDS; 434 tv.tv_usec = 0; 435 rv = select(fd + 1, &read_fds, NULL, NULL, &tv); 436 if (rv == -1) { 437 perror("select"); 438 } else if (rv == 0) { 439 g_message("%s: Timeout expired", __func__); 440 } 441 return rv == 1; 442 } 443 444 /* Initialize *desc (in host endian format). */ 445 static void init_tx_desc(NPCM7xxEMCTxDesc *desc, size_t count, 446 uint32_t desc_addr) 447 { 448 g_assert(count >= 2); 449 memset(&desc[0], 0, sizeof(*desc) * count); 450 /* Leave the last one alone, owned by the cpu -> stops transmission. */ 451 for (size_t i = 0; i < count - 1; ++i) { 452 desc[i].flags = 453 (TX_DESC_FLAG_OWNER_MASK | /* owner = 1: emc */ 454 TX_DESC_FLAG_INTEN | 455 0 | /* crc append = 0 */ 456 0 /* padding enable = 0 */); 457 desc[i].status_and_length = 458 (0 | /* collision count = 0 */ 459 0 | /* SQE = 0 */ 460 0 | /* PAU = 0 */ 461 0 | /* TXHA = 0 */ 462 0 | /* LC = 0 */ 463 0 | /* TXABT = 0 */ 464 0 | /* NCS = 0 */ 465 0 | /* EXDEF = 0 */ 466 0 | /* TXCP = 0 */ 467 0 | /* DEF = 0 */ 468 0 | /* TXINTR = 0 */ 469 0 /* length filled in later */); 470 desc[i].ntxdsa = desc_addr + (i + 1) * sizeof(*desc); 471 } 472 } 473 474 static void enable_tx(QTestState *qts, const EMCModule *mod, 475 const NPCM7xxEMCTxDesc *desc, size_t count, 476 uint32_t desc_addr, uint32_t mien_flags) 477 { 478 /* Write the descriptors to guest memory. */ 479 for (size_t i = 0; i < count; ++i) { 480 emc_write_tx_desc(qts, desc + i, desc_addr + i * sizeof(*desc)); 481 } 482 483 /* Trigger sending the packet. */ 484 /* The module must be reset before changing TXDLSA. */ 485 g_assert(emc_soft_reset(qts, mod)); 486 emc_write(qts, mod, REG_TXDLSA, desc_addr); 487 emc_write(qts, mod, REG_CTXDSA, ~0); 488 emc_write(qts, mod, REG_MIEN, REG_MIEN_ENTXCP | mien_flags); 489 { 490 uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR); 491 mcmdr |= REG_MCMDR_TXON; 492 emc_write(qts, mod, REG_MCMDR, mcmdr); 493 } 494 } 495 496 static void emc_send_verify1(QTestState *qts, const EMCModule *mod, int fd, 497 bool with_irq, uint32_t desc_addr, 498 uint32_t next_desc_addr, 499 const char *test_data, int test_size) 500 { 501 NPCM7xxEMCTxDesc result_desc; 502 uint32_t expected_mask, expected_value, recv_len; 503 int ret; 504 char buffer[TX_DATA_LEN]; 505 506 g_assert(wait_socket_readable(fd)); 507 508 /* Read the descriptor back. */ 509 emc_read_tx_desc(qts, desc_addr, &result_desc); 510 /* Descriptor should be owned by cpu now. */ 511 g_assert((result_desc.flags & TX_DESC_FLAG_OWNER_MASK) == 0); 512 /* Test the status bits, ignoring the length field. */ 513 expected_mask = 0xffff << 16; 514 expected_value = TX_DESC_STATUS_TXCP; 515 if (with_irq) { 516 expected_value |= TX_DESC_STATUS_TXINTR; 517 } 518 g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, 519 expected_value); 520 521 /* Check data sent to the backend. */ 522 recv_len = ~0; 523 ret = recv(fd, &recv_len, sizeof(recv_len), MSG_DONTWAIT); 524 g_assert_cmpint(ret, == , sizeof(recv_len)); 525 526 g_assert(wait_socket_readable(fd)); 527 memset(buffer, 0xff, sizeof(buffer)); 528 ret = recv(fd, buffer, test_size, MSG_DONTWAIT); 529 g_assert_cmpmem(buffer, ret, test_data, test_size); 530 } 531 532 static void emc_send_verify(QTestState *qts, const EMCModule *mod, int fd, 533 bool with_irq) 534 { 535 NPCM7xxEMCTxDesc desc[NUM_TX_DESCRIPTORS]; 536 uint32_t desc_addr = DESC_ADDR; 537 static const char test1_data[] = "TEST1"; 538 static const char test2_data[] = "Testing 1 2 3 ..."; 539 uint32_t data1_addr = DATA_ADDR; 540 uint32_t data2_addr = data1_addr + sizeof(test1_data); 541 bool got_tdu; 542 uint32_t end_desc_addr; 543 544 /* Prepare test data buffer. */ 545 qtest_memwrite(qts, data1_addr, test1_data, sizeof(test1_data)); 546 qtest_memwrite(qts, data2_addr, test2_data, sizeof(test2_data)); 547 548 init_tx_desc(&desc[0], NUM_TX_DESCRIPTORS, desc_addr); 549 desc[0].txbsa = data1_addr; 550 desc[0].status_and_length |= sizeof(test1_data); 551 desc[1].txbsa = data2_addr; 552 desc[1].status_and_length |= sizeof(test2_data); 553 554 enable_tx(qts, mod, &desc[0], NUM_TX_DESCRIPTORS, desc_addr, 555 with_irq ? REG_MIEN_ENTXINTR : 0); 556 557 /* Prod the device to send the packet. */ 558 emc_write(qts, mod, REG_TSDR, 1); 559 560 /* 561 * It's problematic to observe the interrupt for each packet. 562 * Instead just wait until all the packets go out. 563 */ 564 got_tdu = false; 565 while (!got_tdu) { 566 if (with_irq) { 567 g_assert_true(emc_wait_irq(qts, mod, TX_STEP_COUNT, 568 /*is_tx=*/true)); 569 } else { 570 g_assert_true(emc_wait_mista(qts, mod, TX_STEP_COUNT, 571 REG_MISTA_TXINTR)); 572 } 573 got_tdu = !!(emc_read(qts, mod, REG_MISTA) & REG_MISTA_TDU); 574 /* If we don't have TDU yet, reset the interrupt. */ 575 if (!got_tdu) { 576 emc_write(qts, mod, REG_MISTA, 577 emc_read(qts, mod, REG_MISTA) & 0xffff0000); 578 } 579 } 580 581 end_desc_addr = desc_addr + 2 * sizeof(desc[0]); 582 g_assert_cmphex(emc_read(qts, mod, REG_CTXDSA), ==, end_desc_addr); 583 g_assert_cmphex(emc_read(qts, mod, REG_MISTA), ==, 584 REG_MISTA_TXCP | REG_MISTA_TXINTR | REG_MISTA_TDU); 585 586 emc_send_verify1(qts, mod, fd, with_irq, 587 desc_addr, end_desc_addr, 588 test1_data, sizeof(test1_data)); 589 emc_send_verify1(qts, mod, fd, with_irq, 590 desc_addr + sizeof(desc[0]), end_desc_addr, 591 test2_data, sizeof(test2_data)); 592 } 593 594 /* Initialize *desc (in host endian format). */ 595 static void init_rx_desc(NPCM7xxEMCRxDesc *desc, size_t count, 596 uint32_t desc_addr, uint32_t data_addr) 597 { 598 g_assert_true(count >= 2); 599 memset(desc, 0, sizeof(*desc) * count); 600 desc[0].rxbsa = data_addr; 601 desc[0].status_and_length = 602 (0b10 << RX_DESC_STATUS_OWNER_SHIFT | /* owner = 10: emc */ 603 0 | /* RP = 0 */ 604 0 | /* ALIE = 0 */ 605 0 | /* RXGD = 0 */ 606 0 | /* PTLE = 0 */ 607 0 | /* CRCE = 0 */ 608 0 | /* RXINTR = 0 */ 609 0 /* length (filled in later) */); 610 /* Leave the last one alone, owned by the cpu -> stops transmission. */ 611 desc[0].nrxdsa = desc_addr + sizeof(*desc); 612 } 613 614 static void enable_rx(QTestState *qts, const EMCModule *mod, 615 const NPCM7xxEMCRxDesc *desc, size_t count, 616 uint32_t desc_addr, uint32_t mien_flags, 617 uint32_t mcmdr_flags) 618 { 619 /* 620 * Write the descriptor to guest memory. 621 * FWIW, IWBN if the docs said the buffer needs to be at least DMARFC 622 * bytes. 623 */ 624 for (size_t i = 0; i < count; ++i) { 625 emc_write_rx_desc(qts, desc + i, desc_addr + i * sizeof(*desc)); 626 } 627 628 /* Trigger receiving the packet. */ 629 /* The module must be reset before changing RXDLSA. */ 630 g_assert(emc_soft_reset(qts, mod)); 631 emc_write(qts, mod, REG_RXDLSA, desc_addr); 632 emc_write(qts, mod, REG_MIEN, REG_MIEN_ENRXGD | mien_flags); 633 634 /* 635 * We don't know what the device's macaddr is, so just accept all 636 * unicast packets (AUP). 637 */ 638 emc_write(qts, mod, REG_CAMCMR, REG_CAMCMR_AUP); 639 emc_write(qts, mod, REG_CAMEN, 1 << 0); 640 { 641 uint32_t mcmdr = emc_read(qts, mod, REG_MCMDR); 642 mcmdr |= REG_MCMDR_RXON | mcmdr_flags; 643 emc_write(qts, mod, REG_MCMDR, mcmdr); 644 } 645 } 646 647 static void emc_recv_verify(QTestState *qts, const EMCModule *mod, int fd, 648 bool with_irq, bool pump_rsdr) 649 { 650 NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; 651 uint32_t desc_addr = DESC_ADDR; 652 uint32_t data_addr = DATA_ADDR; 653 int ret; 654 uint32_t expected_mask, expected_value; 655 NPCM7xxEMCRxDesc result_desc; 656 657 /* Prepare test data buffer. */ 658 const char test[RX_DATA_LEN] = "TEST"; 659 int len = htonl(sizeof(test)); 660 const struct iovec iov[] = { 661 { 662 .iov_base = &len, 663 .iov_len = sizeof(len), 664 },{ 665 .iov_base = (char *) test, 666 .iov_len = sizeof(test), 667 }, 668 }; 669 670 /* 671 * Reset the device BEFORE sending a test packet, otherwise the packet 672 * may get swallowed by an active device of an earlier test. 673 */ 674 init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); 675 enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, 676 with_irq ? REG_MIEN_ENRXINTR : 0, 0); 677 678 /* 679 * If requested, prod the device to accept a packet. 680 * This isn't necessary, the linux driver doesn't do this. 681 * Test doing/not-doing this for robustness. 682 */ 683 if (pump_rsdr) { 684 emc_write(qts, mod, REG_RSDR, 1); 685 } 686 687 /* Send test packet to device's socket. */ 688 ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test)); 689 g_assert_cmpint(ret, == , sizeof(test) + sizeof(len)); 690 691 /* Wait for RX interrupt. */ 692 if (with_irq) { 693 g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false)); 694 } else { 695 g_assert_true(emc_wait_mista(qts, mod, RX_STEP_COUNT, REG_MISTA_RXGD)); 696 } 697 698 g_assert_cmphex(emc_read(qts, mod, REG_CRXDSA), ==, 699 desc_addr + sizeof(desc[0])); 700 701 expected_mask = 0xffff; 702 expected_value = (REG_MISTA_DENI | 703 REG_MISTA_RXGD | 704 REG_MISTA_RXINTR); 705 g_assert_cmphex((emc_read(qts, mod, REG_MISTA) & expected_mask), 706 ==, expected_value); 707 708 /* Read the descriptor back. */ 709 emc_read_rx_desc(qts, desc_addr, &result_desc); 710 /* Descriptor should be owned by cpu now. */ 711 g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0); 712 /* Test the status bits, ignoring the length field. */ 713 expected_mask = 0xffff << 16; 714 expected_value = RX_DESC_STATUS_RXGD; 715 if (with_irq) { 716 expected_value |= RX_DESC_STATUS_RXINTR; 717 } 718 g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, 719 expected_value); 720 g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==, 721 RX_DATA_LEN + CRC_LENGTH); 722 723 { 724 char buffer[RX_DATA_LEN]; 725 qtest_memread(qts, data_addr, buffer, sizeof(buffer)); 726 g_assert_cmpstr(buffer, == , "TEST"); 727 } 728 } 729 730 static void emc_test_ptle(QTestState *qts, const EMCModule *mod, int fd) 731 { 732 NPCM7xxEMCRxDesc desc[NUM_RX_DESCRIPTORS]; 733 uint32_t desc_addr = DESC_ADDR; 734 uint32_t data_addr = DATA_ADDR; 735 int ret; 736 NPCM7xxEMCRxDesc result_desc; 737 uint32_t expected_mask, expected_value; 738 739 /* Prepare test data buffer. */ 740 #define PTLE_DATA_LEN 1600 741 char test_data[PTLE_DATA_LEN]; 742 int len = htonl(sizeof(test_data)); 743 const struct iovec iov[] = { 744 { 745 .iov_base = &len, 746 .iov_len = sizeof(len), 747 },{ 748 .iov_base = (char *) test_data, 749 .iov_len = sizeof(test_data), 750 }, 751 }; 752 memset(test_data, 42, sizeof(test_data)); 753 754 /* 755 * Reset the device BEFORE sending a test packet, otherwise the packet 756 * may get swallowed by an active device of an earlier test. 757 */ 758 init_rx_desc(&desc[0], NUM_RX_DESCRIPTORS, desc_addr, data_addr); 759 enable_rx(qts, mod, &desc[0], NUM_RX_DESCRIPTORS, desc_addr, 760 REG_MIEN_ENRXINTR, REG_MCMDR_ALP); 761 762 /* Send test packet to device's socket. */ 763 ret = iov_send(fd, iov, 2, 0, sizeof(len) + sizeof(test_data)); 764 g_assert_cmpint(ret, == , sizeof(test_data) + sizeof(len)); 765 766 /* Wait for RX interrupt. */ 767 g_assert_true(emc_wait_irq(qts, mod, RX_STEP_COUNT, /*is_tx=*/false)); 768 769 /* Read the descriptor back. */ 770 emc_read_rx_desc(qts, desc_addr, &result_desc); 771 /* Descriptor should be owned by cpu now. */ 772 g_assert((result_desc.status_and_length & RX_DESC_STATUS_OWNER_MASK) == 0); 773 /* Test the status bits, ignoring the length field. */ 774 expected_mask = 0xffff << 16; 775 expected_value = (RX_DESC_STATUS_RXGD | 776 RX_DESC_STATUS_PTLE | 777 RX_DESC_STATUS_RXINTR); 778 g_assert_cmphex((result_desc.status_and_length & expected_mask), ==, 779 expected_value); 780 g_assert_cmpint(RX_DESC_PKT_LEN(result_desc.status_and_length), ==, 781 PTLE_DATA_LEN + CRC_LENGTH); 782 783 { 784 char buffer[PTLE_DATA_LEN]; 785 qtest_memread(qts, data_addr, buffer, sizeof(buffer)); 786 g_assert(memcmp(buffer, test_data, PTLE_DATA_LEN) == 0); 787 } 788 } 789 790 static void test_tx(gconstpointer test_data) 791 { 792 const TestData *td = test_data; 793 GString *cmd_line = g_string_new("-machine quanta-gsj"); 794 int *test_sockets = packet_test_init(emc_module_index(td->module), 795 cmd_line); 796 QTestState *qts = qtest_init(cmd_line->str); 797 798 /* 799 * TODO: For pedantic correctness test_sockets[0] should be closed after 800 * the fork and before the exec, but that will require some harness 801 * improvements. 802 */ 803 close(test_sockets[1]); 804 /* Defensive programming */ 805 test_sockets[1] = -1; 806 807 qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); 808 809 emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/false); 810 emc_send_verify(qts, td->module, test_sockets[0], /*with_irq=*/true); 811 812 qtest_quit(qts); 813 } 814 815 static void test_rx(gconstpointer test_data) 816 { 817 const TestData *td = test_data; 818 GString *cmd_line = g_string_new("-machine quanta-gsj"); 819 int *test_sockets = packet_test_init(emc_module_index(td->module), 820 cmd_line); 821 QTestState *qts = qtest_init(cmd_line->str); 822 823 /* 824 * TODO: For pedantic correctness test_sockets[0] should be closed after 825 * the fork and before the exec, but that will require some harness 826 * improvements. 827 */ 828 close(test_sockets[1]); 829 /* Defensive programming */ 830 test_sockets[1] = -1; 831 832 qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic"); 833 834 emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false, 835 /*pump_rsdr=*/false); 836 emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/false, 837 /*pump_rsdr=*/true); 838 emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true, 839 /*pump_rsdr=*/false); 840 emc_recv_verify(qts, td->module, test_sockets[0], /*with_irq=*/true, 841 /*pump_rsdr=*/true); 842 emc_test_ptle(qts, td->module, test_sockets[0]); 843 844 qtest_quit(qts); 845 } 846 847 static void emc_add_test(const char *name, const TestData* td, 848 GTestDataFunc fn) 849 { 850 g_autofree char *full_name = g_strdup_printf( 851 "npcm7xx_emc/emc[%d]/%s", emc_module_index(td->module), name); 852 qtest_add_data_func(full_name, td, fn); 853 } 854 #define add_test(name, td) emc_add_test(#name, td, test_##name) 855 856 int main(int argc, char **argv) 857 { 858 TestData test_data_list[ARRAY_SIZE(emc_module_list)]; 859 860 g_test_init(&argc, &argv, NULL); 861 862 for (int i = 0; i < ARRAY_SIZE(emc_module_list); ++i) { 863 TestData *td = &test_data_list[i]; 864 865 td->module = &emc_module_list[i]; 866 867 add_test(init, td); 868 add_test(tx, td); 869 add_test(rx, td); 870 } 871 872 return g_test_run(); 873 } 874