xref: /qemu/tests/tcg/ppc64/non_signalling_xscv.c (revision c23a9563)
1 #include <stdio.h>
2 #include <stdint.h>
3 #include <inttypes.h>
4 #include <assert.h>
5 
6 #define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \
7     do {                                                                \
8         uint64_t th, tl, bh = B_HI, bl = B_LO;                          \
9         asm("mtvsrd 32, %2\n\t"                                         \
10             "mtvsrd 33, %3\n\t"                                         \
11             "xxmrghd 32, 32, 33\n\t"                                    \
12             INSN " 32, 32\n\t"                                          \
13             "mfvsrd %0, 32\n\t"                                         \
14             "xxswapd 32, 32\n\t"                                        \
15             "mfvsrd %1, 32\n\t"                                         \
16             : "=r" (th), "=r" (tl)                                      \
17             : "r" (bh), "r" (bl)                                        \
18             : "v0", "v1");                                              \
19         printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64  \
20                "%016" PRIx64 "\n", bh, bl, th, tl);                     \
21         assert(th == T_HI && tl == T_LO);                               \
22     } while (0)
23 
24 int main(void)
25 {
26     /* SNaN shouldn't be silenced */
27     TEST("xscvspdpn", 0x7fbfffff00000000ULL, 0x0, 0x7ff7ffffe0000000ULL, 0x0);
28     TEST("xscvdpspn", 0x7ff7ffffffffffffULL, 0x0, 0x7fbfffff7fbfffffULL, 0x0);
29 
30     /*
31      * SNaN inputs having no significant bits in the upper 23 bits of the
32      * signifcand will return Infinity as the result.
33      */
34     TEST("xscvdpspn", 0x7ff000001fffffffULL, 0x0, 0x7f8000007f800000ULL, 0x0);
35 
36     return 0;
37 }
38