xref: /qemu/tests/tcg/xtensa/linker.ld.S (revision bfa3ab61) 
1#include <core-isa.h>
2
3#if XTENSA_HAVE_BE
4OUTPUT_FORMAT("elf32-xtensa-be")
5#else
6OUTPUT_FORMAT("elf32-xtensa-le")
7#endif
8ENTRY(_start)
9
10__DYNAMIC = 0;
11
12MEMORY {
13    ram : ORIGIN = XCHAL_VECBASE_RESET_VADDR, LENGTH = 0x08000000  /* 128M */
14    rom : ORIGIN = XCHAL_RESET_VECTOR_VADDR, LENGTH = 0x00001000  /* 4k */
15}
16
17SECTIONS
18{
19    .init :
20    {
21        *(.init)
22        *(.init.*)
23    } > rom
24
25    .vector :
26    {
27    . = XCHAL_WINDOW_OF4_VECOFS;
28        *(.vector.window_overflow_4)
29        *(.vector.window_overflow_4.*)
30    . = XCHAL_WINDOW_UF4_VECOFS;
31        *(.vector.window_underflow_4)
32        *(.vector.window_underflow_4.*)
33    . = XCHAL_WINDOW_OF8_VECOFS;
34        *(.vector.window_overflow_8)
35        *(.vector.window_overflow_8.*)
36    . = XCHAL_WINDOW_UF8_VECOFS;
37        *(.vector.window_underflow_8)
38        *(.vector.window_underflow_8.*)
39    . = XCHAL_WINDOW_OF12_VECOFS;
40        *(.vector.window_overflow_12)
41        *(.vector.window_overflow_12.*)
42    . = XCHAL_WINDOW_UF12_VECOFS;
43        *(.vector.window_underflow_12)
44        *(.vector.window_underflow_12.*)
45
46#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 2
47    . = XCHAL_INTLEVEL2_VECOFS;
48        *(.vector.level2)
49        *(.vector.level2.*)
50#endif
51#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 3
52    . = XCHAL_INTLEVEL3_VECOFS;
53        *(.vector.level3)
54        *(.vector.level3.*)
55#endif
56#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 4
57    . = XCHAL_INTLEVEL4_VECOFS;
58        *(.vector.level4)
59        *(.vector.level4.*)
60#endif
61#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 5
62    . = XCHAL_INTLEVEL5_VECOFS;
63        *(.vector.level5)
64        *(.vector.level5.*)
65#endif
66#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 6
67    . = XCHAL_INTLEVEL6_VECOFS;
68        *(.vector.level6)
69        *(.vector.level6.*)
70#endif
71#if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI >= 7
72    . = XCHAL_INTLEVEL7_VECOFS;
73        *(.vector.level7)
74        *(.vector.level7.*)
75#endif
76
77    . = XCHAL_KERNEL_VECOFS;
78        *(.vector.kernel)
79        *(.vector.kernel.*)
80    . = XCHAL_USER_VECOFS;
81        *(.vector.user)
82        *(.vector.user.*)
83    . = XCHAL_DOUBLEEXC_VECOFS;
84        *(.vector.double)
85        *(.vector.double.*)
86    } > ram
87
88    .text :
89    {
90        _ftext = .;
91        *(.text .stub .text.* .gnu.linkonce.t.* .literal .literal.*)
92        _etext = .;
93    } > ram
94
95    .rodata :
96    {
97        . = ALIGN(4);
98        _frodata = .;
99        *(.rodata .rodata.* .gnu.linkonce.r.*)
100        *(.rodata1)
101        _erodata = .;
102    } > ram
103
104    .data :
105    {
106        . = ALIGN(4);
107        _fdata = .;
108        *(.data .data.* .gnu.linkonce.d.*)
109        *(.data1)
110        _gp = ALIGN(16);
111        *(.sdata .sdata.* .gnu.linkonce.s.*)
112        _edata = .;
113    } > ram
114
115    .bss :
116    {
117        . = ALIGN(4);
118        _fbss = .;
119        *(.dynsbss)
120        *(.sbss .sbss.* .gnu.linkonce.sb.*)
121        *(.scommon)
122        *(.dynbss)
123        *(.bss .bss.* .gnu.linkonce.b.*)
124        *(COMMON)
125        _ebss = .;
126        _end = .;
127    } > ram
128}
129
130PROVIDE(_fstack = (ORIGIN(ram) & 0xf0000000) + LENGTH(ram) - 16);
131