1 #include "precomp.h" 2 3 // 4 // Minimal Attribute Controller Registers initialization command stream. 5 // Compatible EGA. 6 // 7 USHORT AT_Initialization[] = 8 { 9 /* Reset ATC to index mode */ 10 IB, 11 VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */, 12 13 /* Write the AC registers */ 14 METAOUT+ATCOUT, 15 VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */, 16 16, 0, // Values Count and Start Index 17 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, // Palette indices 0-5 18 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, // Palette indices 6-11 19 0x0C, 0x0D, 0x0E, 0x0F, // Palette indices 12-15 20 21 /* Reset ATC to index mode */ 22 IB, 23 VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */, 24 25 /* Enable screen and disable palette access */ 26 OB, 27 VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */, 28 VIDEO_ENABLE, 29 30 /* End of Stream */ 31 EOD 32 }; 33 34 // 35 // 640x480 256-color 60Hz mode (BIOS mode 12) set command stream for VGA. 36 // Adapted from win32ss/drivers/miniport/vga_new/vgadata.c 37 // 38 USHORT VGA_640x480[] = 39 { 40 /* Write the Sequencer Registers */ 41 OWM, 42 VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, 43 VGA_NUM_SEQUENCER_PORTS, // Values Count (5) 44 // HI: Value in SEQ_DATA_PORT, LO: Register index in SEQ_ADDRESS_PORT 45 0x0100, // Synchronous reset on 46 0x0101, // 8-Dot Mode 47 0x0F02, // Memory Plane Write Enable on all planes 0-3 48 0x0003, // No character set selected 49 0x0604, // Disable Odd/Even host mem addressing; Enable Extended Memory 50 51 /* Write the Miscellaneous Register */ 52 OB, 53 VGA_BASE_IO_PORT + MISC_OUTPUT_REG_WRITE_PORT, 54 0xE3, // V/H-SYNC polarity, Odd/Even High page select, RAM enable, 55 // I/O Address select (1: color/graphics adapter) 56 57 /* Enable Graphics Mode */ 58 OW, 59 VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, 60 // HI: Value in GRAPH_DATA_PORT, LO: Register index in GRAPH_ADDRESS_PORT 61 0x506, // Select A0000h-AFFFFh memory region, Disable Alphanumeric mode 62 63 /* Synchronous reset off */ 64 OW, 65 VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, 66 // HI: Value in SEQ_DATA_PORT, LO: Register index in SEQ_ADDRESS_PORT 67 0x0300, // Synchronous reset off (LO: IND_SYNC_RESET, HI: END_SYNC_RESET_VALUE) 68 69 /* Unlock CRTC registers 0-7 */ 70 OW, 71 VGA_BASE_IO_PORT + CRTC_ADDRESS_PORT_COLOR, 72 0x511, 73 74 /* Write the CRTC registers */ 75 METAOUT+INDXOUT, 76 VGA_BASE_IO_PORT + CRTC_ADDRESS_PORT_COLOR, 77 VGA_NUM_CRTC_PORTS, 0, // Values Count (25) and Start Index 78 0x5F, 0x4F, 0x50, 0x82, 0x54, 0x80, 0x0B, 0x3E, 0x00, 0x40, 0x00, 0x00, 79 0x00, 0x00, 0x00, 0x00, 0xEA, 0x8C, 0xDF, 0x28, 0x00, 0xE7, 0x04, 0xE3, 80 0xFF, 81 82 /* Reset ATC to index mode */ 83 IB, 84 VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */, 85 86 /* Write the AC registers */ 87 METAOUT+ATCOUT, 88 VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */, 89 VGA_NUM_ATTRIB_CONT_PORTS, 0, // Values Count (21) and Start Index 90 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, // Palette indices 0-5 91 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, // Palette indices 6-11 92 0x0C, 0x0D, 0x0E, 0x0F, // Palette indices 12-15 93 0x01, 0x00, 0x0F, 0x00, 0x00, 94 95 /* Write the GC registers */ 96 METAOUT+INDXOUT, 97 VGA_BASE_IO_PORT + GRAPH_ADDRESS_PORT, 98 VGA_NUM_GRAPH_CONT_PORTS, 0, // Values Count (9) and Start Index 99 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 100 0x05, 0x0F, 0xFF, 101 102 /* Set the PEL mask */ 103 OB, 104 VGA_BASE_IO_PORT + DAC_PIXEL_MASK_PORT, 105 0xFF, 106 107 /* Reset ATC to index mode */ 108 IB, 109 VGA_BASE_IO_PORT + ATT_INITIALIZE_PORT_COLOR /* INPUT_STATUS_1_COLOR */, 110 111 /* Enable screen and disable palette access */ 112 OB, 113 VGA_BASE_IO_PORT + ATT_ADDRESS_PORT /* ATT_DATA_WRITE_PORT */, 114 VIDEO_ENABLE, 115 116 /* End of Stream */ 117 EOD 118 }; 119