1 /* 2 * PROJECT: ReactOS Hardware Abstraction Layer 3 * LICENSE: GPL-2.0-or-later (https://spdx.org/licenses/GPL-2.0-or-later) 4 * PURPOSE: PC/AT hardware header file 5 * COPYRIGHT: ... 6 */ 7 8 #pragma once 9 10 /* CMOS Registers and Ports */ 11 #define CMOS_CONTROL_PORT (PUCHAR)0x70 12 #define CMOS_DATA_PORT (PUCHAR)0x71 13 #define RTC_REGISTER_A 0x0A 14 #define RTC_REG_A_UIP 0x80 15 #define RTC_REGISTER_B 0x0B 16 #define RTC_REG_B_PI 0x40 17 #define RTC_REGISTER_C 0x0C 18 #define RTC_REG_C_IRQ 0x80 19 #define RTC_REGISTER_D 0x0D 20 #define RTC_REGISTER_CENTURY 0x32 21 22 // 23 // BIOS Interrupts 24 // 25 #define VIDEO_SERVICES 0x10 26 27 // 28 // Operations for INT 10h (in AH) 29 // 30 #define SET_VIDEO_MODE 0x00 31 32 // 33 // Video Modes for INT10h AH=00 (in AL) 34 // 35 #define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */ 36 37 #if defined(SARCH_XBOX) 38 // 39 // For some unknown reason the PIT of the Xbox is fixed at 1.125000 MHz, 40 // which is ~5.7% lower than on the PC. 41 // 42 #define PIT_FREQUENCY 1125000 43 #else 44 // 45 // Commonly stated as being 1.19318MHz 46 // 47 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle) 48 // p. 471 49 // 50 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd 51 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz. 52 // 53 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if 54 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the 55 // infinite series) and divides it by three, one obtains 1.19318167. 56 // 57 // It may be that the original NT HAL source code introduced a typo and turned 58 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the 59 // number is quite long. 60 // 61 #define PIT_FREQUENCY 1193182 62 #endif 63 64 // 65 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT) 66 // 67 #define TIMER_CHANNEL0_DATA_PORT 0x40 68 #define TIMER_CHANNEL1_DATA_PORT 0x41 69 #define TIMER_CHANNEL2_DATA_PORT 0x42 70 #define TIMER_CONTROL_PORT 0x43 71 72 // 73 // Mode 0 - Interrupt On Terminal Count 74 // Mode 1 - Hardware Re-triggerable One-Shot 75 // Mode 2 - Rate Generator 76 // Mode 3 - Square Wave Generator 77 // Mode 4 - Software Triggered Strobe 78 // Mode 5 - Hardware Triggered Strobe 79 // 80 typedef enum _TIMER_OPERATING_MODES 81 { 82 PitOperatingMode0, 83 PitOperatingMode1, 84 PitOperatingMode2, 85 PitOperatingMode3, 86 PitOperatingMode4, 87 PitOperatingMode5, 88 PitOperatingMode2Reserved, 89 PitOperatingMode5Reserved 90 } TIMER_OPERATING_MODES; 91 92 typedef enum _TIMER_ACCESS_MODES 93 { 94 PitAccessModeCounterLatch, 95 PitAccessModeLow, 96 PitAccessModeHigh, 97 PitAccessModeLowHigh 98 } TIMER_ACCESS_MODES; 99 100 typedef enum _TIMER_CHANNELS 101 { 102 PitChannel0, 103 PitChannel1, 104 PitChannel2, 105 PitReadBack 106 } TIMER_CHANNELS; 107 108 typedef union _TIMER_CONTROL_PORT_REGISTER 109 { 110 struct 111 { 112 UCHAR BcdMode:1; 113 UCHAR OperatingMode:3; 114 UCHAR AccessMode:2; 115 UCHAR Channel:2; 116 }; 117 UCHAR Bits; 118 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER; 119 120 // 121 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle) 122 // P. 400 123 // 124 // This port is controled by the i8255 Programmable Peripheral Interface (PPI) 125 // 126 #define SYSTEM_CONTROL_PORT_A 0x92 127 #define SYSTEM_CONTROL_PORT_B 0x61 128 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER 129 { 130 struct 131 { 132 UCHAR Timer2GateToSpeaker:1; 133 UCHAR SpeakerDataEnable:1; 134 UCHAR ParityCheckEnable:1; 135 UCHAR ChannelCheckEnable:1; 136 UCHAR RefreshRequest:1; 137 UCHAR Timer2Output:1; 138 UCHAR ChannelCheck:1; 139 UCHAR ParityCheck:1; 140 }; 141 UCHAR Bits; 142 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER; 143 144 // 145 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle) 146 // P. 396, 397 147 // 148 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC) 149 // 150 #define PIC1_CONTROL_PORT 0x20 151 #define PIC1_DATA_PORT 0x21 152 #define PIC2_CONTROL_PORT 0xA0 153 #define PIC2_DATA_PORT 0xA1 154 155 // 156 // Definitions for ICW/OCW Bits 157 // 158 typedef enum _I8259_ICW1_OPERATING_MODE 159 { 160 Cascade, 161 Single 162 } I8259_ICW1_OPERATING_MODE; 163 164 typedef enum _I8259_ICW1_INTERRUPT_MODE 165 { 166 EdgeTriggered, 167 LevelTriggered 168 } I8259_ICW1_INTERRUPT_MODE; 169 170 typedef enum _I8259_ICW1_INTERVAL 171 { 172 Interval8, 173 Interval4 174 } I8259_ICW1_INTERVAL; 175 176 typedef enum _I8259_ICW4_SYSTEM_MODE 177 { 178 Mcs8085Mode, 179 New8086Mode 180 } I8259_ICW4_SYSTEM_MODE; 181 182 typedef enum _I8259_ICW4_EOI_MODE 183 { 184 NormalEoi, 185 AutomaticEoi 186 } I8259_ICW4_EOI_MODE; 187 188 typedef enum _I8259_ICW4_BUFFERED_MODE 189 { 190 NonBuffered, 191 NonBuffered2, 192 BufferedSlave, 193 BufferedMaster 194 } I8259_ICW4_BUFFERED_MODE; 195 196 typedef enum _I8259_READ_REQUEST 197 { 198 InvalidRequest, 199 InvalidRequest2, 200 ReadIdr, 201 ReadIsr 202 } I8259_READ_REQUEST; 203 204 typedef enum _I8259_EOI_MODE 205 { 206 RotateAutoEoiClear, 207 NonSpecificEoi, 208 InvalidEoiMode, 209 SpecificEoi, 210 RotateAutoEoiSet, 211 RotateNonSpecific, 212 SetPriority, 213 RotateSpecific 214 } I8259_EOI_MODE; 215 216 // 217 // Definitions for ICW Registers 218 // 219 typedef union _I8259_ICW1 220 { 221 struct 222 { 223 UCHAR NeedIcw4:1; 224 UCHAR OperatingMode:1; 225 UCHAR Interval:1; 226 UCHAR InterruptMode:1; 227 UCHAR Init:1; 228 UCHAR InterruptVectorAddress:3; 229 }; 230 UCHAR Bits; 231 } I8259_ICW1, *PI8259_ICW1; 232 233 typedef union _I8259_ICW2 234 { 235 struct 236 { 237 UCHAR Sbz:3; 238 UCHAR InterruptVector:5; 239 }; 240 UCHAR Bits; 241 } I8259_ICW2, *PI8259_ICW2; 242 243 typedef union _I8259_ICW3 244 { 245 union 246 { 247 struct 248 { 249 UCHAR SlaveIrq0:1; 250 UCHAR SlaveIrq1:1; 251 UCHAR SlaveIrq2:1; 252 UCHAR SlaveIrq3:1; 253 UCHAR SlaveIrq4:1; 254 UCHAR SlaveIrq5:1; 255 UCHAR SlaveIrq6:1; 256 UCHAR SlaveIrq7:1; 257 }; 258 struct 259 { 260 UCHAR SlaveId:3; 261 UCHAR Reserved:5; 262 }; 263 }; 264 UCHAR Bits; 265 } I8259_ICW3, *PI8259_ICW3; 266 267 typedef union _I8259_ICW4 268 { 269 struct 270 { 271 UCHAR SystemMode:1; 272 UCHAR EoiMode:1; 273 UCHAR BufferedMode:2; 274 UCHAR SpecialFullyNestedMode:1; 275 UCHAR Reserved:3; 276 }; 277 UCHAR Bits; 278 } I8259_ICW4, *PI8259_ICW4; 279 280 typedef union _I8259_OCW2 281 { 282 struct 283 { 284 UCHAR IrqNumber:3; 285 UCHAR Sbz:2; 286 UCHAR EoiMode:3; 287 }; 288 UCHAR Bits; 289 } I8259_OCW2, *PI8259_OCW2; 290 291 typedef union _I8259_OCW3 292 { 293 struct 294 { 295 UCHAR ReadRequest:2; 296 UCHAR PollCommand:1; 297 UCHAR Sbo:1; 298 UCHAR Sbz:1; 299 UCHAR SpecialMaskMode:2; 300 UCHAR Reserved:1; 301 }; 302 UCHAR Bits; 303 } I8259_OCW3, *PI8259_OCW3; 304 305 typedef union _I8259_ISR 306 { 307 union 308 { 309 struct 310 { 311 UCHAR Irq0:1; 312 UCHAR Irq1:1; 313 UCHAR Irq2:1; 314 UCHAR Irq3:1; 315 UCHAR Irq4:1; 316 UCHAR Irq5:1; 317 UCHAR Irq6:1; 318 UCHAR Irq7:1; 319 }; 320 }; 321 UCHAR Bits; 322 } I8259_ISR, *PI8259_ISR; 323 324 typedef I8259_ISR I8259_IDR, *PI8259_IDR; 325 326 // 327 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle) 328 // P. 34, 35 329 // 330 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC) 331 // 332 #define EISA_ELCR_MASTER 0x4D0 333 #define EISA_ELCR_SLAVE 0x4D1 334 335 typedef union _EISA_ELCR 336 { 337 struct 338 { 339 struct 340 { 341 UCHAR Irq0Level:1; 342 UCHAR Irq1Level:1; 343 UCHAR Irq2Level:1; 344 UCHAR Irq3Level:1; 345 UCHAR Irq4Level:1; 346 UCHAR Irq5Level:1; 347 UCHAR Irq6Level:1; 348 UCHAR Irq7Level:1; 349 } Master; 350 struct 351 { 352 UCHAR Irq8Level:1; 353 UCHAR Irq9Level:1; 354 UCHAR Irq10Level:1; 355 UCHAR Irq11Level:1; 356 UCHAR Irq12Level:1; 357 UCHAR Irq13Level:1; 358 UCHAR Irq14Level:1; 359 UCHAR Irq15Level:1; 360 } Slave; 361 }; 362 USHORT Bits; 363 } EISA_ELCR, *PEISA_ELCR; 364 365 typedef struct _PIC_MASK 366 { 367 union 368 { 369 struct 370 { 371 UCHAR Master; 372 UCHAR Slave; 373 }; 374 USHORT Both; 375 }; 376 } PIC_MASK, *PPIC_MASK; 377