1 #pragma once 2 3 #include "intrin_i.h" 4 5 #define KiServiceExit2 KiExceptionExit 6 7 #define SYNCH_LEVEL DISPATCH_LEVEL 8 #define PCR ((KPCR * const)KIP0PCRADDRESS) 9 10 // 11 //Lockdown TLB entries 12 // 13 #define PCR_ENTRY 0 14 #define PDR_ENTRY 2 15 16 // 17 // BKPT is 4 bytes long 18 // 19 #define KD_BREAKPOINT_TYPE ULONG 20 #define KD_BREAKPOINT_SIZE sizeof(ULONG) 21 #define KD_BREAKPOINT_VALUE 0xDEFE 22 23 // 24 // Maximum IRQs 25 // 26 #define MAXIMUM_VECTOR 16 27 28 // 29 // Macros for getting and setting special purpose registers in portable code 30 // 31 #define KeGetContextPc(Context) \ 32 ((Context)->Pc) 33 34 #define KeSetContextPc(Context, ProgramCounter) \ 35 ((Context)->Pc = (ProgramCounter)) 36 37 #define KeGetTrapFramePc(TrapFrame) \ 38 ((TrapFrame)->Pc) 39 40 #define KeGetContextReturnRegister(Context) \ 41 ((Context)->R0) 42 43 #define KeSetContextReturnRegister(Context, ReturnValue) \ 44 ((Context)->R0 = (ReturnValue)) 45 46 // 47 // Macro to get trap and exception frame from a thread stack 48 // 49 #define KeGetTrapFrame(Thread) \ 50 (PKTRAP_FRAME)((ULONG_PTR)((Thread)->InitialStack) - \ 51 sizeof(KTRAP_FRAME)) 52 53 #define KeGetExceptionFrame(Thread) \ 54 (PKEXCEPTION_FRAME)((ULONG_PTR)KeGetTrapFrame(Thread) - \ 55 sizeof(KEXCEPTION_FRAME)) 56 57 // 58 // Macro to get context switches from the PRCB 59 // All architectures but x86 have it in the PRCB's KeContextSwitches 60 // 61 #define KeGetContextSwitches(Prcb) \ 62 (Prcb)->KeContextSwitches 63 64 // 65 // Macro to get the second level cache size field name which differs between 66 // CISC and RISC architectures, as the former has unified I/D cache 67 // 68 #define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelDcacheSize 69 70 // 71 // Returns the Interrupt State from a Trap Frame. 72 // ON = TRUE, OFF = FALSE 73 // 74 #define KeGetTrapFrameInterruptState(TrapFrame) 0 75 76 FORCEINLINE 77 BOOLEAN 78 KeDisableInterrupts(VOID) 79 { 80 ARM_STATUS_REGISTER Flags; 81 82 // 83 // Get current interrupt state and disable interrupts 84 // 85 Flags = KeArmStatusRegisterGet(); 86 _disable(); 87 88 // 89 // Return previous interrupt state 90 // 91 return Flags.IrqDisable; 92 } 93 94 FORCEINLINE 95 VOID 96 KeRestoreInterrupts(BOOLEAN WereEnabled) 97 { 98 if (WereEnabled) _enable(); 99 } 100 101 // 102 // Invalidates the TLB entry for a specified address 103 // 104 FORCEINLINE 105 VOID 106 KeInvalidateTlbEntry(IN PVOID Address) 107 { 108 /* Invalidate the TLB entry for this address */ 109 KeArmInvalidateTlbEntry(Address); 110 } 111 112 FORCEINLINE 113 VOID 114 KeFlushProcessTb(VOID) 115 { 116 KeArmFlushTlb(); 117 } 118 119 FORCEINLINE 120 VOID 121 KeSweepICache(IN PVOID BaseAddress, 122 IN SIZE_T FlushSize) 123 { 124 // 125 // Always sweep the whole cache 126 // 127 UNREFERENCED_PARAMETER(BaseAddress); 128 UNREFERENCED_PARAMETER(FlushSize); 129 _MoveToCoprocessor(0, CP15_ICIALLU); 130 } 131 132 FORCEINLINE 133 VOID 134 KiRundownThread(IN PKTHREAD Thread) 135 { 136 /* FIXME */ 137 } 138 139 VOID 140 KiPassiveRelease( 141 VOID 142 ); 143 144 VOID 145 KiSystemService(IN PKTHREAD Thread, 146 IN PKTRAP_FRAME TrapFrame, 147 IN ULONG Instruction); 148 149 VOID 150 KiApcInterrupt( 151 VOID 152 ); 153 154 #include "mm.h" 155 156 VOID 157 KeFlushTb( 158 VOID 159 ); 160 161 // 162 // Cache clean and flush 163 // 164 VOID 165 HalSweepDcache( 166 VOID 167 ); 168 169 VOID 170 HalSweepIcache( 171 VOID 172 ); 173 174 #define Ki386PerfEnd() 175 #define KiEndInterrupt(x,y) 176 177 #define KiGetLinkedTrapFrame(x) \ 178 (PKTRAP_FRAME)((x)->TrapFrame) 179 180 #define KiGetPreviousMode(tf) \ 181 ((tf->Cpsr & CPSRM_MASK) == CPSRM_USER) ? UserMode: KernelMode 182