1 /* 2 * kernel internal memory management definitions for arm 3 */ 4 #pragma once 5 6 #define _MI_PAGING_LEVELS 2 7 8 /* Memory layout base addresses */ 9 #define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000 10 #define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000 11 #define HYPER_SPACE 0xC0500000 12 #define HYPER_SPACE_END 0xC08FFFFF 13 #define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000 14 #define MI_PAGED_POOL_START (PVOID)0xE1000000 15 #define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000 16 #define MI_DEBUG_MAPPING (PVOID)0xFFBFF000 17 #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFF 18 19 #define PTE_PER_PAGE 256 20 #define PDE_PER_PAGE 4096 21 #define PPE_PER_PAGE 1 22 23 /* Misc address definitions */ 24 #define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL) 25 #define MM_HIGHEST_VAD_ADDRESS \ 26 (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE)) 27 #define MI_MAPPING_RANGE_START ((ULONG)HYPER_SPACE) 28 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \ 29 MI_HYPERSPACE_PTES * PAGE_SIZE) 30 #define MI_DUMMY_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \ 31 PAGE_SIZE) 32 #define MI_VAD_BITMAP (PMMPTE)(MI_DUMMY_PTE + \ 33 PAGE_SIZE) 34 #define MI_WORKING_SET_LIST (PMMPTE)(MI_VAD_BITMAP + \ 35 PAGE_SIZE) 36 37 /* Memory sizes */ 38 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT) 39 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT) 40 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT) 41 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT) 42 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB) 43 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB) 44 #define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB) 45 #define MI_SYSTEM_VIEW_SIZE (32 * _1MB) 46 #define MI_SESSION_VIEW_SIZE (48 * _1MB) 47 #define MI_SESSION_POOL_SIZE (16 * _1MB) 48 #define MI_SESSION_IMAGE_SIZE (8 * _1MB) 49 #define MI_SESSION_WORKING_SET_SIZE (4 * _1MB) 50 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \ 51 MI_SESSION_POOL_SIZE + \ 52 MI_SESSION_IMAGE_SIZE + \ 53 MI_SESSION_WORKING_SET_SIZE) 54 #define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB) 55 #define MI_ALLOCATION_FRAGMENT (64 * _1KB) 56 #define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB) 57 58 /* Misc constants */ 59 #define MM_PTE_SOFTWARE_PROTECTION_BITS 6 60 #define MI_MIN_SECONDARY_COLORS 8 61 #define MI_SECONDARY_COLORS 64 62 #define MI_MAX_SECONDARY_COLORS 1024 63 #define MI_MAX_FREE_PAGE_LISTS 4 64 #define MI_HYPERSPACE_PTES (256 - 1) /* Dee PDR definition */ 65 #define MI_ZERO_PTES (32) /* Dee PDR definition */ 66 #define MI_MAX_ZERO_BITS 21 67 #define SESSION_POOL_LOOKASIDES 26 // CHECKME 68 69 /* MMPTE related defines */ 70 #define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF) 71 #define MM_EMPTY_LIST ((ULONG_PTR)-1) 72 73 74 /* Easy accessing PFN in PTE */ 75 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber) 76 77 /* Macros for portable PTE modification */ 78 #define MI_MAKE_DIRTY_PAGE(x) 79 #define MI_MAKE_CLEAN_PAGE(x) 80 #define MI_MAKE_ACCESSED_PAGE(x) 81 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.Cached = 0) 82 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.Buffered = 0) 83 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.Buffered = 1) 84 #define MI_IS_PAGE_LARGE(x) FALSE 85 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.ReadOnly == 0) 86 #define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE 87 #define MI_IS_PAGE_EXECUTABLE(x) TRUE 88 #define MI_IS_PAGE_DIRTY(x) TRUE 89 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1) 90 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.ReadOnly = 0) 91 92 /* Macros to identify the page fault reason from the error code */ 93 #define MI_IS_NOT_PRESENT_FAULT(FaultCode) TRUE 94 #define MI_IS_WRITE_ACCESS(FaultCode) TRUE 95 #define MI_IS_INSTRUCTION_FETCH(FaultCode) FALSE 96 97 /* Convert an address to a corresponding PTE */ 98 #define MiAddressToPte(x) \ 99 ((PMMPTE)(PTE_BASE + (((ULONG)(x) >> 12) << 2))) 100 101 /* Convert an address to a corresponding PDE */ 102 #define MiAddressToPde(x) \ 103 ((PMMPDE)(PDE_BASE + (((ULONG)(x) >> 20) << 2))) 104 105 /* Convert an address to a corresponding PTE offset/index */ 106 #define MiAddressToPteOffset(x) \ 107 ((((ULONG)(x)) << 12) >> 24) 108 109 /* Convert an address to a corresponding PDE offset/index */ 110 #define MiAddressToPdeOffset(x) \ 111 (((ULONG)(x)) >> 20) 112 #define MiGetPdeOffset MiAddressToPdeOffset 113 114 /* Convert a PTE/PDE into a corresponding address */ 115 #define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10)) 116 #define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 18)) 117 118 /* Translate between P*Es */ 119 #define MiPdeToPte(_Pde) ((PMMPTE)0) /* FIXME */ 120 #define MiPteToPde(_Pte) ((PMMPDE)0) /* FIXME */ 121 122 /* Check P*E boundaries */ 123 #define MiIsPteOnPdeBoundary(PointerPte) \ 124 ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0) 125 126 // 127 // Decodes a Prototype PTE into the underlying PTE 128 // 129 #define MiProtoPteToPte(x) \ 130 (PMMPTE)((ULONG_PTR)MmPagedPoolStart + \ 131 (((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2)) 132 133 // 134 // Decodes a Prototype PTE into the underlying PTE 135 // 136 #define MiSubsectionPteToSubsection(x) \ 137 ((x)->u.Subsect.WhichPool == PagedPool) ? \ 138 (PMMPTE)((ULONG_PTR)MmSubsectionBase + \ 139 (((x)->u.Subsect.SubsectionAddressHigh << 7) | \ 140 (x)->u.Subsect.SubsectionAddressLow << 3)) : \ 141 (PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \ 142 (((x)->u.Subsect.SubsectionAddressHigh << 7) | \ 143 (x)->u.Subsect.SubsectionAddressLow << 3)) 144 145 // 146 // Number of bits corresponding to the area that a coarse page table occupies (1KB) 147 // 148 #define CPT_SHIFT 10 149 150 /* See PDR definition */ 151 #define MI_ZERO_PTE (PMMPTE)(MI_MAPPING_RANGE_END + \ 152 PAGE_SIZE) 153 154