1 /* 2 * kernel internal memory management definitions for x86 3 */ 4 #pragma once 5 6 #ifdef _PAE_ 7 #define _MI_PAGING_LEVELS 3 8 #else 9 #define _MI_PAGING_LEVELS 2 10 #endif 11 12 /* Memory layout base addresses */ 13 #define MI_USER_PROBE_ADDRESS (PVOID)0x7FFF0000 14 #define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0x80000000 15 #ifndef PAE 16 #define HYPER_SPACE 0xC0400000 17 #define HYPER_SPACE_END 0xC07FFFFF 18 #else 19 #define HYPER_SPACE 0xC0800000 20 #define HYPER_SPACE_END 0xC0BFFFFF 21 #endif 22 #define MI_SYSTEM_CACHE_WS_START (PVOID)0xC0C00000 23 #define MI_SYSTEM_CACHE_START (PVOID)0xC1000000 24 #define MI_PAGED_POOL_START (PVOID)0xE1000000 25 #define MI_NONPAGED_POOL_END (PVOID)0xFFBE0000 26 #define MI_DEBUG_MAPPING (PVOID)0xFFBFF000 27 #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFF 28 29 /* FIXME: These are different for PAE */ 30 #define PTE_BASE 0xC0000000 31 #define PDE_BASE 0xC0300000 32 #define PDE_TOP 0xC0300FFF 33 #define PTE_TOP 0xC03FFFFF 34 35 #define PTE_PER_PAGE 0x400 36 #define PDE_PER_PAGE 0x400 37 #define PPE_PER_PAGE 1 38 39 /* Misc address definitions */ 40 #define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(NULL) 41 #define MM_HIGHEST_VAD_ADDRESS \ 42 (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE)) 43 #define MI_MAPPING_RANGE_START (ULONG)HYPER_SPACE 44 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + \ 45 MI_HYPERSPACE_PTES * PAGE_SIZE) 46 #define MI_DUMMY_PTE (PMMPTE)((ULONG_PTR)MI_MAPPING_RANGE_END + \ 47 PAGE_SIZE) 48 #define MI_VAD_BITMAP (PMMPTE)((ULONG_PTR)MI_DUMMY_PTE + \ 49 PAGE_SIZE) 50 #define MI_WORKING_SET_LIST (PMMPTE)((ULONG_PTR)MI_VAD_BITMAP + \ 51 PAGE_SIZE) 52 53 /* Memory sizes */ 54 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT) 55 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT) 56 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT) 57 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT) 58 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB) 59 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128 * _1MB) 60 #define MI_MAX_NONPAGED_POOL_SIZE (128 * _1MB) 61 #define MI_SYSTEM_VIEW_SIZE (32 * _1MB) 62 #define MI_SESSION_VIEW_SIZE (48 * _1MB) 63 #define MI_SESSION_POOL_SIZE (16 * _1MB) 64 #define MI_SESSION_IMAGE_SIZE (8 * _1MB) 65 #define MI_SESSION_WORKING_SET_SIZE (4 * _1MB) 66 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \ 67 MI_SESSION_POOL_SIZE + \ 68 MI_SESSION_IMAGE_SIZE + \ 69 MI_SESSION_WORKING_SET_SIZE) 70 #define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB) 71 #define MI_ALLOCATION_FRAGMENT (64 * _1KB) 72 #define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB) 73 74 /* Misc constants */ 75 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5 76 #define MI_MIN_SECONDARY_COLORS 8 77 #define MI_SECONDARY_COLORS 64 78 #define MI_MAX_SECONDARY_COLORS 1024 79 #define MI_MAX_FREE_PAGE_LISTS 4 80 #define MI_HYPERSPACE_PTES (256 - 1) 81 #define MI_ZERO_PTES (32) 82 #define MI_MAX_ZERO_BITS 21 83 #define SESSION_POOL_LOOKASIDES 26 84 85 /* MMPTE related defines */ 86 #define MM_EMPTY_PTE_LIST ((ULONG)0xFFFFF) 87 #define MM_EMPTY_LIST ((ULONG_PTR)-1) 88 89 90 /* Easy accessing PFN in PTE */ 91 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber) 92 93 /* Macros for portable PTE modification */ 94 #define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1) 95 #define MI_MAKE_CLEAN_PAGE(x) ((x)->u.Hard.Dirty = 0) 96 #define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1) 97 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1) 98 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1) 99 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0) 100 #define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1) 101 #if !defined(CONFIG_SMP) 102 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1) 103 #else 104 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1) 105 #endif 106 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1) 107 #ifdef _PAE_ 108 #define MI_IS_PAGE_EXECUTABLE(x) ((x)->u.Hard.NoExecute == 0) 109 #else 110 #define MI_IS_PAGE_EXECUTABLE(x) TRUE 111 #endif 112 #define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1) 113 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1) 114 #if !defined(CONFIG_SMP) 115 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1) 116 #else 117 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1) 118 #endif 119 120 121 /* Macros to identify the page fault reason from the error code */ 122 #define MI_IS_NOT_PRESENT_FAULT(FaultCode) !BooleanFlagOn(FaultCode, 0x1) 123 #define MI_IS_WRITE_ACCESS(FaultCode) BooleanFlagOn(FaultCode, 0x2) 124 #define MI_IS_INSTRUCTION_FETCH(FaultCode) BooleanFlagOn(FaultCode, 0x10) 125 126 /* On x86, these two are the same */ 127 #define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE 128 129 /* Convert an address to a corresponding PTE */ 130 #define MiAddressToPte(x) \ 131 ((PMMPTE)(((((ULONG)(x)) >> 12) << 2) + PTE_BASE)) 132 133 /* Convert an address to a corresponding PDE */ 134 #define MiAddressToPde(x) \ 135 ((PMMPDE)(((((ULONG)(x)) >> 22) << 2) + PDE_BASE)) 136 137 /* Convert an address to a corresponding PTE offset/index */ 138 #define MiAddressToPteOffset(x) \ 139 ((((ULONG)(x)) << 10) >> 22) 140 141 /* Convert an address to a corresponding PDE offset/index */ 142 #define MiAddressToPdeOffset(x) \ 143 (((ULONG)(x)) / (1024 * PAGE_SIZE)) 144 #define MiGetPdeOffset MiAddressToPdeOffset 145 146 /* Convert a PTE/PDE into a corresponding address */ 147 #define MiPteToAddress(_Pte) ((PVOID)((ULONG)(_Pte) << 10)) 148 #define MiPdeToAddress(_Pde) ((PVOID)((ULONG)(_Pde) << 20)) 149 150 /* Translate between P*Es */ 151 #define MiPdeToPte(_Pde) ((PMMPTE)MiPteToAddress(_Pde)) 152 #define MiPteToPde(_Pte) ((PMMPDE)MiAddressToPte(_Pte)) 153 154 /* Check P*E boundaries */ 155 #define MiIsPteOnPdeBoundary(PointerPte) \ 156 ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0) 157 158 // 159 // Decodes a Prototype PTE into the underlying PTE 160 // 161 #define MiProtoPteToPte(x) \ 162 (PMMPTE)((ULONG_PTR)MmPagedPoolStart + \ 163 (((x)->u.Proto.ProtoAddressHigh << 9) | (x)->u.Proto.ProtoAddressLow << 2)) 164 165 // 166 // Decodes a Prototype PTE into the underlying PTE 167 // 168 #define MiSubsectionPteToSubsection(x) \ 169 ((x)->u.Subsect.WhichPool == PagedPool) ? \ 170 (PMMPTE)((ULONG_PTR)MmSubsectionBase + \ 171 (((x)->u.Subsect.SubsectionAddressHigh << 7) | \ 172 (x)->u.Subsect.SubsectionAddressLow << 3)) : \ 173 (PMMPTE)((ULONG_PTR)MmNonPagedPoolEnd - \ 174 (((x)->u.Subsect.SubsectionAddressHigh << 7) | \ 175 (x)->u.Subsect.SubsectionAddressLow << 3)) 176