1 /* 2 * PROJECT: ReactOS Kernel 3 * LICENSE: BSD - See COPYING.ARM in the top level directory 4 * FILE: ntoskrnl/kd/arm/kdbg.c 5 * PURPOSE: Serial Port Kernel Debugging Transport Library 6 * PROGRAMMERS: ReactOS Portable Systems Group 7 */ 8 9 /* INCLUDES *******************************************************************/ 10 11 #include <ntoskrnl.h> 12 #include <arm/peripherals/pl011.h> 13 #define NDEBUG 14 #include <debug.h> 15 16 /* GLOBALS ********************************************************************/ 17 18 CPPORT DefaultPort = {0, 0, 0}; 19 20 // 21 // We need to build this in the configuration root and use KeFindConfigurationEntry 22 // to recover it later. 23 // 24 #define HACK 24000000 25 26 /* REACTOS FUNCTIONS **********************************************************/ 27 28 BOOLEAN 29 NTAPI 30 KdPortInitializeEx(IN PCPPORT PortInformation, 31 IN ULONG ComPortNumber) 32 { 33 ULONG Divider, Remainder, Fraction; 34 ULONG Baudrate = PortInformation->BaudRate; 35 36 // 37 // Calculate baudrate clock divider and remainder 38 // 39 Divider = HACK / (16 * Baudrate); 40 Remainder = HACK % (16 * Baudrate); 41 42 // 43 // Calculate the fractional part 44 // 45 Fraction = (8 * Remainder / Baudrate) >> 1; 46 Fraction += (8 * Remainder / Baudrate) & 1; 47 48 // 49 // Disable interrupts 50 // 51 WRITE_REGISTER_ULONG((PULONG)UART_PL011_CR, 0); 52 53 // 54 // Set the baud rate 55 // 56 WRITE_REGISTER_ULONG((PULONG)UART_PL011_IBRD, Divider); 57 WRITE_REGISTER_ULONG((PULONG)UART_PL011_FBRD, Fraction); 58 59 // 60 // Set 8 bits for data, 1 stop bit, no parity, FIFO enabled 61 // 62 WRITE_REGISTER_ULONG((PULONG)UART_PL011_LCRH, 63 UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN); 64 65 // 66 // Clear and enable FIFO 67 // 68 WRITE_REGISTER_ULONG((PULONG)UART_PL011_CR, 69 UART_PL011_CR_UARTEN | 70 UART_PL011_CR_TXE | 71 UART_PL011_CR_RXE); 72 73 // 74 // Done 75 // 76 return TRUE; 77 } 78 79 BOOLEAN 80 NTAPI 81 KdPortGetByteEx(IN PCPPORT PortInformation, 82 OUT PUCHAR ByteReceived) 83 { 84 UNIMPLEMENTED; 85 while (TRUE); 86 return FALSE; 87 } 88 89 VOID 90 NTAPI 91 KdPortPutByteEx(IN PCPPORT PortInformation, 92 IN UCHAR ByteToSend) 93 { 94 // 95 // Wait for ready 96 // 97 while ((READ_REGISTER_ULONG((PULONG)UART_PL01x_FR) & UART_PL01x_FR_TXFF) != 0); 98 99 // 100 // Send the character 101 // 102 WRITE_REGISTER_ULONG((PULONG)UART_PL01x_DR, ByteToSend); 103 } 104 105 /* EOF */ 106