1 /* 2 * File cvconst.h - MS debug information 3 * 4 * Copyright (C) 2004, Eric Pouech 5 * Copyright (C) 2012, André Hentschel 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA 20 */ 21 22 /* information in this file is highly derived from MSDN DIA information pages */ 23 24 /* symbols & types enumeration */ 25 enum SymTagEnum 26 { 27 SymTagNull, 28 SymTagExe, 29 SymTagCompiland, 30 SymTagCompilandDetails, 31 SymTagCompilandEnv, 32 SymTagFunction, 33 SymTagBlock, 34 SymTagData, 35 SymTagAnnotation, 36 SymTagLabel, 37 SymTagPublicSymbol, 38 SymTagUDT, 39 SymTagEnum, 40 SymTagFunctionType, 41 SymTagPointerType, 42 SymTagArrayType, 43 SymTagBaseType, 44 SymTagTypedef, 45 SymTagBaseClass, 46 SymTagFriend, 47 SymTagFunctionArgType, 48 SymTagFuncDebugStart, 49 SymTagFuncDebugEnd, 50 SymTagUsingNamespace, 51 SymTagVTableShape, 52 SymTagVTable, 53 SymTagCustom, 54 SymTagThunk, 55 SymTagCustomType, 56 SymTagManagedType, 57 SymTagDimension, 58 SymTagMax 59 }; 60 61 enum BasicType 62 { 63 btNoType = 0, 64 btVoid = 1, 65 btChar = 2, 66 btWChar = 3, 67 btInt = 6, 68 btUInt = 7, 69 btFloat = 8, 70 btBCD = 9, 71 btBool = 10, 72 btLong = 13, 73 btULong = 14, 74 btCurrency = 25, 75 btDate = 26, 76 btVariant = 27, 77 btComplex = 28, 78 btBit = 29, 79 btBSTR = 30, 80 btHresult = 31, 81 btChar16 = 32, 82 btChar32 = 33 83 }; 84 85 /* kind of UDT */ 86 enum UdtKind 87 { 88 UdtStruct, 89 UdtClass, 90 UdtUnion 91 }; 92 93 /* where a SymTagData is */ 94 enum LocationType 95 { 96 LocIsNull, 97 LocIsStatic, 98 LocIsTLS, 99 LocIsRegRel, 100 LocIsThisRel, 101 LocIsEnregistered, 102 LocIsBitField, 103 LocIsSlot, 104 LocIsIlRel, 105 LocInMetaData, 106 LocIsConstant 107 }; 108 109 /* kind of SymTagData */ 110 enum DataKind 111 { 112 DataIsUnknown, 113 DataIsLocal, 114 DataIsStaticLocal, 115 DataIsParam, 116 DataIsObjectPtr, 117 DataIsFileStatic, 118 DataIsGlobal, 119 DataIsMember, 120 DataIsStaticMember, 121 DataIsConstant 122 }; 123 124 /* values for registers (on different CPUs) */ 125 enum CV_HREG_e 126 { 127 /* those values are common to all supported CPUs (and CPU independent) */ 128 CV_ALLREG_ERR = 30000, 129 CV_ALLREG_TEB = 30001, 130 CV_ALLREG_TIMER = 30002, 131 CV_ALLREG_EFAD1 = 30003, 132 CV_ALLREG_EFAD2 = 30004, 133 CV_ALLREG_EFAD3 = 30005, 134 CV_ALLREG_VFRAME = 30006, 135 CV_ALLREG_HANDLE = 30007, 136 CV_ALLREG_PARAMS = 30008, 137 CV_ALLREG_LOCALS = 30009, 138 CV_ALLREG_TID = 30010, 139 CV_ALLREG_ENV = 30011, 140 CV_ALLREG_CMDLN = 30012, 141 142 /* Intel x86 CPU */ 143 CV_REG_NONE = 0, 144 CV_REG_AL = 1, 145 CV_REG_CL = 2, 146 CV_REG_DL = 3, 147 CV_REG_BL = 4, 148 CV_REG_AH = 5, 149 CV_REG_CH = 6, 150 CV_REG_DH = 7, 151 CV_REG_BH = 8, 152 CV_REG_AX = 9, 153 CV_REG_CX = 10, 154 CV_REG_DX = 11, 155 CV_REG_BX = 12, 156 CV_REG_SP = 13, 157 CV_REG_BP = 14, 158 CV_REG_SI = 15, 159 CV_REG_DI = 16, 160 CV_REG_EAX = 17, 161 CV_REG_ECX = 18, 162 CV_REG_EDX = 19, 163 CV_REG_EBX = 20, 164 CV_REG_ESP = 21, 165 CV_REG_EBP = 22, 166 CV_REG_ESI = 23, 167 CV_REG_EDI = 24, 168 CV_REG_ES = 25, 169 CV_REG_CS = 26, 170 CV_REG_SS = 27, 171 CV_REG_DS = 28, 172 CV_REG_FS = 29, 173 CV_REG_GS = 30, 174 CV_REG_IP = 31, 175 CV_REG_FLAGS = 32, 176 CV_REG_EIP = 33, 177 CV_REG_EFLAGS = 34, 178 179 /* <pcode> */ 180 CV_REG_TEMP = 40, 181 CV_REG_TEMPH = 41, 182 CV_REG_QUOTE = 42, 183 CV_REG_PCDR3 = 43, /* this includes PCDR4 to PCDR7 */ 184 CV_REG_CR0 = 80, /* this includes CR1 to CR4 */ 185 CV_REG_DR0 = 90, /* this includes DR1 to DR7 */ 186 /* </pcode> */ 187 188 CV_REG_GDTR = 110, 189 CV_REG_GDTL = 111, 190 CV_REG_IDTR = 112, 191 CV_REG_IDTL = 113, 192 CV_REG_LDTR = 114, 193 CV_REG_TR = 115, 194 195 CV_REG_PSEUDO1 = 116, /* this includes Pseudo02 to Pseudo09 */ 196 CV_REG_ST0 = 128, /* this includes ST1 to ST7 */ 197 CV_REG_CTRL = 136, 198 CV_REG_STAT = 137, 199 CV_REG_TAG = 138, 200 CV_REG_FPIP = 139, 201 CV_REG_FPCS = 140, 202 CV_REG_FPDO = 141, 203 CV_REG_FPDS = 142, 204 CV_REG_ISEM = 143, 205 CV_REG_FPEIP = 144, 206 CV_REG_FPEDO = 145, 207 CV_REG_MM0 = 146, /* this includes MM1 to MM7 */ 208 CV_REG_XMM0 = 154, /* this includes XMM1 to XMM7 */ 209 CV_REG_XMM00 = 162, 210 CV_REG_XMM0L = 194, /* this includes XMM1L to XMM7L */ 211 CV_REG_XMM0H = 202, /* this includes XMM1H to XMM7H */ 212 CV_REG_MXCSR = 211, 213 CV_REG_EDXEAX = 212, 214 CV_REG_EMM0L = 220, 215 CV_REG_EMM0H = 228, 216 CV_REG_MM00 = 236, 217 CV_REG_MM01 = 237, 218 CV_REG_MM10 = 238, 219 CV_REG_MM11 = 239, 220 CV_REG_MM20 = 240, 221 CV_REG_MM21 = 241, 222 CV_REG_MM30 = 242, 223 CV_REG_MM31 = 243, 224 CV_REG_MM40 = 244, 225 CV_REG_MM41 = 245, 226 CV_REG_MM50 = 246, 227 CV_REG_MM51 = 247, 228 CV_REG_MM60 = 248, 229 CV_REG_MM61 = 249, 230 CV_REG_MM70 = 250, 231 CV_REG_MM71 = 251, 232 233 CV_REG_YMM0 = 252, /* this includes YMM1 to YMM7 */ 234 CV_REG_YMM0H = 260, /* this includes YMM1H to YMM7H */ 235 CV_REG_YMM0I0 = 268, /* this includes YMM0I1 to YMM0I3 */ 236 CV_REG_YMM1I0 = 272, /* this includes YMM1I1 to YMM1I3 */ 237 CV_REG_YMM2I0 = 276, /* this includes YMM2I1 to YMM2I3 */ 238 CV_REG_YMM3I0 = 280, /* this includes YMM3I1 to YMM3I3 */ 239 CV_REG_YMM4I0 = 284, /* this includes YMM4I1 to YMM4I3 */ 240 CV_REG_YMM5I0 = 288, /* this includes YMM5I1 to YMM5I3 */ 241 CV_REG_YMM6I0 = 292, /* this includes YMM6I1 to YMM6I3 */ 242 CV_REG_YMM7I0 = 296, /* this includes YMM7I1 to YMM7I3 */ 243 CV_REG_YMM0F0 = 300, /* this includes YMM0F1 to YMM0F7 */ 244 CV_REG_YMM1F0 = 308, /* this includes YMM1F1 to YMM1F7 */ 245 CV_REG_YMM2F0 = 316, /* this includes YMM2F1 to YMM2F7 */ 246 CV_REG_YMM3F0 = 324, /* this includes YMM3F1 to YMM3F7 */ 247 CV_REG_YMM4F0 = 332, /* this includes YMM4F1 to YMM4F7 */ 248 CV_REG_YMM5F0 = 340, /* this includes YMM5F1 to YMM5F7 */ 249 CV_REG_YMM6F0 = 348, /* this includes YMM6F1 to YMM6F7 */ 250 CV_REG_YMM7F0 = 356, /* this includes YMM7F1 to YMM7F7 */ 251 CV_REG_YMM0D0 = 364, /* this includes YMM0D1 to YMM0D3 */ 252 CV_REG_YMM1D0 = 368, /* this includes YMM1D1 to YMM1D3 */ 253 CV_REG_YMM2D0 = 372, /* this includes YMM2D1 to YMM2D3 */ 254 CV_REG_YMM3D0 = 376, /* this includes YMM3D1 to YMM3D3 */ 255 CV_REG_YMM4D0 = 380, /* this includes YMM4D1 to YMM4D3 */ 256 CV_REG_YMM5D0 = 384, /* this includes YMM5D1 to YMM5D3 */ 257 CV_REG_YMM6D0 = 388, /* this includes YMM6D1 to YMM6D3 */ 258 CV_REG_YMM7D0 = 392, /* this includes YMM7D1 to YMM7D3 */ 259 260 /* Motorola 68K CPU */ 261 CV_R68_D0 = 0, /* this includes D1 to D7 too */ 262 CV_R68_A0 = 8, /* this includes A1 to A7 too */ 263 CV_R68_CCR = 16, 264 CV_R68_SR = 17, 265 CV_R68_USP = 18, 266 CV_R68_MSP = 19, 267 CV_R68_SFC = 20, 268 CV_R68_DFC = 21, 269 CV_R68_CACR = 22, 270 CV_R68_VBR = 23, 271 CV_R68_CAAR = 24, 272 CV_R68_ISP = 25, 273 CV_R68_PC = 26, 274 CV_R68_FPCR = 28, 275 CV_R68_FPSR = 29, 276 CV_R68_FPIAR = 30, 277 CV_R68_FP0 = 32, /* this includes FP1 to FP7 */ 278 CV_R68_MMUSR030 = 41, 279 CV_R68_MMUSR = 42, 280 CV_R68_URP = 43, 281 CV_R68_DTT0 = 44, 282 CV_R68_DTT1 = 45, 283 CV_R68_ITT0 = 46, 284 CV_R68_ITT1 = 47, 285 CV_R68_PSR = 51, 286 CV_R68_PCSR = 52, 287 CV_R68_VAL = 53, 288 CV_R68_CRP = 54, 289 CV_R68_SRP = 55, 290 CV_R68_DRP = 56, 291 CV_R68_TC = 57, 292 CV_R68_AC = 58, 293 CV_R68_SCC = 59, 294 CV_R68_CAL = 60, 295 CV_R68_TT0 = 61, 296 CV_R68_TT1 = 62, 297 CV_R68_BAD0 = 64, /* this includes BAD1 to BAD7 */ 298 CV_R68_BAC0 = 72, /* this includes BAC1 to BAC7 */ 299 300 /* MIPS 4000 CPU */ 301 CV_M4_NOREG = CV_REG_NONE, 302 CV_M4_IntZERO = 10, 303 CV_M4_IntAT = 11, 304 CV_M4_IntV0 = 12, 305 CV_M4_IntV1 = 13, 306 CV_M4_IntA0 = 14, /* this includes IntA1 to IntA3 */ 307 CV_M4_IntT0 = 18, /* this includes IntT1 to IntT7 */ 308 CV_M4_IntS0 = 26, /* this includes IntS1 to IntS7 */ 309 CV_M4_IntT8 = 34, 310 CV_M4_IntT9 = 35, 311 CV_M4_IntKT0 = 36, 312 CV_M4_IntKT1 = 37, 313 CV_M4_IntGP = 38, 314 CV_M4_IntSP = 39, 315 CV_M4_IntS8 = 40, 316 CV_M4_IntRA = 41, 317 CV_M4_IntLO = 42, 318 CV_M4_IntHI = 43, 319 CV_M4_Fir = 50, 320 CV_M4_Psr = 51, 321 CV_M4_FltF0 = 60, /* this includes FltF1 to Flt31 */ 322 CV_M4_FltFsr = 92, 323 324 /* Alpha AXP CPU */ 325 CV_ALPHA_NOREG = CV_REG_NONE, 326 CV_ALPHA_FltF0 = 10, /* this includes FltF1 to FltF31 */ 327 CV_ALPHA_IntV0 = 42, 328 CV_ALPHA_IntT0 = 43, /* this includes T1 to T7 */ 329 CV_ALPHA_IntS0 = 51, /* this includes S1 to S5 */ 330 CV_ALPHA_IntFP = 57, 331 CV_ALPHA_IntA0 = 58, /* this includes A1 to A5 */ 332 CV_ALPHA_IntT8 = 64, 333 CV_ALPHA_IntT9 = 65, 334 CV_ALPHA_IntT10 = 66, 335 CV_ALPHA_IntT11 = 67, 336 CV_ALPHA_IntRA = 68, 337 CV_ALPHA_IntT12 = 69, 338 CV_ALPHA_IntAT = 70, 339 CV_ALPHA_IntGP = 71, 340 CV_ALPHA_IntSP = 72, 341 CV_ALPHA_IntZERO = 73, 342 CV_ALPHA_Fpcr = 74, 343 CV_ALPHA_Fir = 75, 344 CV_ALPHA_Psr = 76, 345 CV_ALPHA_FltFsr = 77, 346 CV_ALPHA_SoftFpcr = 78, 347 348 /* Motorola & IBM PowerPC CPU */ 349 CV_PPC_GPR0 = 1, /* this includes GPR1 to GPR31 */ 350 CV_PPC_CR = 33, 351 CV_PPC_CR0 = 34, /* this includes CR1 to CR7 */ 352 CV_PPC_FPR0 = 42, /* this includes FPR1 to FPR31 */ 353 354 CV_PPC_FPSCR = 74, 355 CV_PPC_MSR = 75, 356 CV_PPC_SR0 = 76, /* this includes SR1 to SR15 */ 357 CV_PPC_PC = 99, 358 CV_PPC_MQ = 100, 359 CV_PPC_XER = 101, 360 CV_PPC_RTCU = 104, 361 CV_PPC_RTCL = 105, 362 CV_PPC_LR = 108, 363 CV_PPC_CTR = 109, 364 CV_PPC_COMPARE = 110, 365 CV_PPC_COUNT = 111, 366 CV_PPC_DSISR = 118, 367 CV_PPC_DAR = 119, 368 CV_PPC_DEC = 122, 369 CV_PPC_SDR1 = 125, 370 CV_PPC_SRR0 = 126, 371 CV_PPC_SRR1 = 127, 372 CV_PPC_SPRG0 = 372, /* this includes SPRG1 to SPRG3 */ 373 CV_PPC_ASR = 280, 374 CV_PPC_EAR = 382, 375 CV_PPC_PVR = 287, 376 CV_PPC_BAT0U = 628, 377 CV_PPC_BAT0L = 629, 378 CV_PPC_BAT1U = 630, 379 CV_PPC_BAT1L = 631, 380 CV_PPC_BAT2U = 632, 381 CV_PPC_BAT2L = 633, 382 CV_PPC_BAT3U = 634, 383 CV_PPC_BAT3L = 635, 384 CV_PPC_DBAT0U = 636, 385 CV_PPC_DBAT0L = 637, 386 CV_PPC_DBAT1U = 638, 387 CV_PPC_DBAT1L = 639, 388 CV_PPC_DBAT2U = 640, 389 CV_PPC_DBAT2L = 641, 390 CV_PPC_DBAT3U = 642, 391 CV_PPC_DBAT3L = 643, 392 CV_PPC_PMR0 = 1044, /* this includes PMR1 to PMR15 */ 393 CV_PPC_DMISS = 1076, 394 CV_PPC_DCMP = 1077, 395 CV_PPC_HASH1 = 1078, 396 CV_PPC_HASH2 = 1079, 397 CV_PPC_IMISS = 1080, 398 CV_PPC_ICMP = 1081, 399 CV_PPC_RPA = 1082, 400 CV_PPC_HID0 = 1108, /* this includes HID1 to HID15 */ 401 402 /* Java */ 403 CV_JAVA_PC = 1, 404 405 /* Hitachi SH3 CPU */ 406 CV_SH3_NOREG = CV_REG_NONE, 407 CV_SH3_IntR0 = 10, /* this include R1 to R13 */ 408 CV_SH3_IntFp = 24, 409 CV_SH3_IntSp = 25, 410 CV_SH3_Gbr = 38, 411 CV_SH3_Pr = 39, 412 CV_SH3_Mach = 40, 413 CV_SH3_Macl = 41, 414 CV_SH3_Pc = 50, 415 CV_SH3_Sr = 51, 416 CV_SH3_BarA = 60, 417 CV_SH3_BasrA = 61, 418 CV_SH3_BamrA = 62, 419 CV_SH3_BbrA = 63, 420 CV_SH3_BarB = 64, 421 CV_SH3_BasrB = 65, 422 CV_SH3_BamrB = 66, 423 CV_SH3_BbrB = 67, 424 CV_SH3_BdrB = 68, 425 CV_SH3_BdmrB = 69, 426 CV_SH3_Brcr = 70, 427 CV_SH_Fpscr = 75, 428 CV_SH_Fpul = 76, 429 CV_SH_FpR0 = 80, /* this includes FpR1 to FpR15 */ 430 CV_SH_XFpR0 = 96, /* this includes XFpR1 to XXFpR15 */ 431 432 /* ARM CPU */ 433 CV_ARM_NOREG = CV_REG_NONE, 434 CV_ARM_R0 = 10, /* this includes R1 to R12 */ 435 CV_ARM_SP = 23, 436 CV_ARM_LR = 24, 437 CV_ARM_PC = 25, 438 CV_ARM_CPSR = 26, 439 CV_ARM_ACC0 = 27, 440 CV_ARM_FPSCR = 40, 441 CV_ARM_FPEXC = 41, 442 CV_ARM_FS0 = 50, /* this includes FS1 to FS31 */ 443 CV_ARM_FPEXTRA0 = 90, /* this includes FPEXTRA1 to FPEXTRA7 */ 444 CV_ARM_WR0 = 128, /* this includes WR1 to WR15 */ 445 CV_ARM_WCID = 144, 446 CV_ARM_WCON = 145, 447 CV_ARM_WCSSF = 146, 448 CV_ARM_WCASF = 147, 449 CV_ARM_WC4 = 148, 450 CV_ARM_WC5 = 149, 451 CV_ARM_WC6 = 150, 452 CV_ARM_WC7 = 151, 453 CV_ARM_WCGR0 = 152, /* this includes WCGR1 to WCGR3 */ 454 CV_ARM_WC12 = 156, 455 CV_ARM_WC13 = 157, 456 CV_ARM_WC14 = 158, 457 CV_ARM_WC15 = 159, 458 CV_ARM_FS32 = 200, /* this includes FS33 to FS63 */ 459 CV_ARM_ND0 = 300, /* this includes ND1 to ND31 */ 460 CV_ARM_NQ0 = 400, /* this includes NQ1 to NQ15 */ 461 462 /* ARM64 CPU */ 463 CV_ARM64_NOREG = CV_REG_NONE, 464 CV_ARM64_W0 = 10, /* this includes W0 to W30 */ 465 CV_ARM64_WZR = 41, 466 CV_ARM64_PC = 42, /* Wine extension */ 467 CV_ARM64_PSTATE = 43, /* Wine extension */ 468 CV_ARM64_X0 = 50, /* this includes X0 to X28 */ 469 CV_ARM64_IP0 = 66, /* Same as X16 */ 470 CV_ARM64_IP1 = 67, /* Same as X17 */ 471 CV_ARM64_FP = 79, 472 CV_ARM64_LR = 80, 473 CV_ARM64_SP = 81, 474 CV_ARM64_ZR = 82, 475 CV_ARM64_NZCV = 90, 476 CV_ARM64_S0 = 100, /* this includes S0 to S31 */ 477 CV_ARM64_D0 = 140, /* this includes D0 to D31 */ 478 CV_ARM64_Q0 = 180, /* this includes Q0 to Q31 */ 479 CV_ARM64_FPSR = 220, 480 481 /* Intel IA64 CPU */ 482 CV_IA64_NOREG = CV_REG_NONE, 483 CV_IA64_Br0 = 512, /* this includes Br1 to Br7 */ 484 CV_IA64_P0 = 704, /* this includes P1 to P63 */ 485 CV_IA64_Preds = 768, 486 CV_IA64_IntH0 = 832, /* this includes H1 to H15 */ 487 CV_IA64_Ip = 1016, 488 CV_IA64_Umask = 1017, 489 CV_IA64_Cfm = 1018, 490 CV_IA64_Psr = 1019, 491 CV_IA64_Nats = 1020, 492 CV_IA64_Nats2 = 1021, 493 CV_IA64_Nats3 = 1022, 494 CV_IA64_IntR0 = 1024, /* this includes R1 to R127 */ 495 CV_IA64_FltF0 = 2048, /* this includes FltF1 to FltF127 */ 496 /* some IA64 registers missing */ 497 498 /* TriCore CPU */ 499 CV_TRI_NOREG = CV_REG_NONE, 500 CV_TRI_D0 = 10, /* includes D1 to D15 */ 501 CV_TRI_A0 = 26, /* includes A1 to A15 */ 502 CV_TRI_E0 = 42, 503 CV_TRI_E2 = 43, 504 CV_TRI_E4 = 44, 505 CV_TRI_E6 = 45, 506 CV_TRI_E8 = 46, 507 CV_TRI_E10 = 47, 508 CV_TRI_E12 = 48, 509 CV_TRI_E14 = 49, 510 CV_TRI_EA0 = 50, 511 CV_TRI_EA2 = 51, 512 CV_TRI_EA4 = 52, 513 CV_TRI_EA6 = 53, 514 CV_TRI_EA8 = 54, 515 CV_TRI_EA10 = 55, 516 CV_TRI_EA12 = 56, 517 CV_TRI_EA14 = 57, 518 CV_TRI_PSW = 58, 519 CV_TRI_PCXI = 59, 520 CV_TRI_PC = 60, 521 CV_TRI_FCX = 61, 522 CV_TRI_LCX = 62, 523 CV_TRI_ISP = 63, 524 CV_TRI_ICR = 64, 525 CV_TRI_BIV = 65, 526 CV_TRI_BTV = 66, 527 CV_TRI_SYSCON = 67, 528 CV_TRI_DPRx_0 = 68, /* includes DPRx_1 to DPRx_3 */ 529 CV_TRI_CPRx_0 = 68, /* includes CPRx_1 to CPRx_3 */ 530 CV_TRI_DPMx_0 = 68, /* includes DPMx_1 to DPMx_3 */ 531 CV_TRI_CPMx_0 = 68, /* includes CPMx_1 to CPMx_3 */ 532 CV_TRI_DBGSSR = 72, 533 CV_TRI_EXEVT = 73, 534 CV_TRI_SWEVT = 74, 535 CV_TRI_CREVT = 75, 536 CV_TRI_TRnEVT = 76, 537 CV_TRI_MMUCON = 77, 538 CV_TRI_ASI = 78, 539 CV_TRI_TVA = 79, 540 CV_TRI_TPA = 80, 541 CV_TRI_TPX = 81, 542 CV_TRI_TFA = 82, 543 544 /* AM33 (and the likes) CPU */ 545 CV_AM33_NOREG = CV_REG_NONE, 546 CV_AM33_E0 = 10, /* this includes E1 to E7 */ 547 CV_AM33_A0 = 20, /* this includes A1 to A3 */ 548 CV_AM33_D0 = 30, /* this includes D1 to D3 */ 549 CV_AM33_FS0 = 40, /* this includes FS1 to FS31 */ 550 CV_AM33_SP = 80, 551 CV_AM33_PC = 81, 552 CV_AM33_MDR = 82, 553 CV_AM33_MDRQ = 83, 554 CV_AM33_MCRH = 84, 555 CV_AM33_MCRL = 85, 556 CV_AM33_MCVF = 86, 557 CV_AM33_EPSW = 87, 558 CV_AM33_FPCR = 88, 559 CV_AM33_LIR = 89, 560 CV_AM33_LAR = 90, 561 562 /* Mitsubishi M32R CPU */ 563 CV_M32R_NOREG = CV_REG_NONE, 564 CV_M32R_R0 = 10, /* this includes R1 to R11 */ 565 CV_M32R_R12 = 22, 566 CV_M32R_R13 = 23, 567 CV_M32R_R14 = 24, 568 CV_M32R_R15 = 25, 569 CV_M32R_PSW = 26, 570 CV_M32R_CBR = 27, 571 CV_M32R_SPI = 28, 572 CV_M32R_SPU = 29, 573 CV_M32R_SPO = 30, 574 CV_M32R_BPC = 31, 575 CV_M32R_ACHI = 32, 576 CV_M32R_ACLO = 33, 577 CV_M32R_PC = 34, 578 579 /* AMD/Intel x86_64 CPU */ 580 CV_AMD64_NONE = CV_REG_NONE, 581 CV_AMD64_AL = CV_REG_AL, 582 CV_AMD64_CL = CV_REG_CL, 583 CV_AMD64_DL = CV_REG_DL, 584 CV_AMD64_BL = CV_REG_BL, 585 CV_AMD64_AH = CV_REG_AH, 586 CV_AMD64_CH = CV_REG_CH, 587 CV_AMD64_DH = CV_REG_DH, 588 CV_AMD64_BH = CV_REG_BH, 589 CV_AMD64_AX = CV_REG_AX, 590 CV_AMD64_CX = CV_REG_CX, 591 CV_AMD64_DX = CV_REG_DX, 592 CV_AMD64_BX = CV_REG_BX, 593 CV_AMD64_SP = CV_REG_SP, 594 CV_AMD64_BP = CV_REG_BP, 595 CV_AMD64_SI = CV_REG_SI, 596 CV_AMD64_DI = CV_REG_DI, 597 CV_AMD64_EAX = CV_REG_EAX, 598 CV_AMD64_ECX = CV_REG_ECX, 599 CV_AMD64_EDX = CV_REG_EDX, 600 CV_AMD64_EBX = CV_REG_EBX, 601 CV_AMD64_ESP = CV_REG_ESP, 602 CV_AMD64_EBP = CV_REG_EBP, 603 CV_AMD64_ESI = CV_REG_ESI, 604 CV_AMD64_EDI = CV_REG_EDI, 605 CV_AMD64_ES = CV_REG_ES, 606 CV_AMD64_CS = CV_REG_CS, 607 CV_AMD64_SS = CV_REG_SS, 608 CV_AMD64_DS = CV_REG_DS, 609 CV_AMD64_FS = CV_REG_FS, 610 CV_AMD64_GS = CV_REG_GS, 611 CV_AMD64_FLAGS = CV_REG_FLAGS, 612 CV_AMD64_RIP = CV_REG_EIP, 613 CV_AMD64_EFLAGS = CV_REG_EFLAGS, 614 615 /* <pcode> */ 616 CV_AMD64_TEMP = CV_REG_TEMP, 617 CV_AMD64_TEMPH = CV_REG_TEMPH, 618 CV_AMD64_QUOTE = CV_REG_QUOTE, 619 CV_AMD64_PCDR3 = CV_REG_PCDR3, /* this includes PCDR4 to PCDR7 */ 620 CV_AMD64_CR0 = CV_REG_CR0, /* this includes CR1 to CR4 */ 621 CV_AMD64_DR0 = CV_REG_DR0, /* this includes DR1 to DR7 */ 622 /* </pcode> */ 623 624 CV_AMD64_GDTR = CV_REG_GDTR, 625 CV_AMD64_GDTL = CV_REG_GDTL, 626 CV_AMD64_IDTR = CV_REG_IDTR, 627 CV_AMD64_IDTL = CV_REG_IDTL, 628 CV_AMD64_LDTR = CV_REG_LDTR, 629 CV_AMD64_TR = CV_REG_TR, 630 631 CV_AMD64_PSEUDO1 = CV_REG_PSEUDO1, /* this includes Pseudo02 to Pseudo09 */ 632 CV_AMD64_ST0 = CV_REG_ST0, /* this includes ST1 to ST7 */ 633 CV_AMD64_CTRL = CV_REG_CTRL, 634 CV_AMD64_STAT = CV_REG_STAT, 635 CV_AMD64_TAG = CV_REG_TAG, 636 CV_AMD64_FPIP = CV_REG_FPIP, 637 CV_AMD64_FPCS = CV_REG_FPCS, 638 CV_AMD64_FPDO = CV_REG_FPDO, 639 CV_AMD64_FPDS = CV_REG_FPDS, 640 CV_AMD64_ISEM = CV_REG_ISEM, 641 CV_AMD64_FPEIP = CV_REG_FPEIP, 642 CV_AMD64_FPEDO = CV_REG_FPEDO, 643 CV_AMD64_MM0 = CV_REG_MM0, /* this includes MM1 to MM7 */ 644 CV_AMD64_XMM0 = CV_REG_XMM0, /* this includes XMM1 to XMM7 */ 645 CV_AMD64_XMM00 = CV_REG_XMM00, 646 CV_AMD64_XMM0L = CV_REG_XMM0L, /* this includes XMM1L to XMM7L */ 647 CV_AMD64_XMM0H = CV_REG_XMM0H, /* this includes XMM1H to XMM7H */ 648 CV_AMD64_MXCSR = CV_REG_MXCSR, 649 CV_AMD64_EDXEAX = CV_REG_EDXEAX, 650 CV_AMD64_EMM0L = CV_REG_EMM0L, 651 CV_AMD64_EMM0H = CV_REG_EMM0H, 652 CV_AMD64_MM00 = CV_REG_MM00, 653 CV_AMD64_MM01 = CV_REG_MM01, 654 CV_AMD64_MM10 = CV_REG_MM10, 655 CV_AMD64_MM11 = CV_REG_MM11, 656 CV_AMD64_MM20 = CV_REG_MM20, 657 CV_AMD64_MM21 = CV_REG_MM21, 658 CV_AMD64_MM30 = CV_REG_MM30, 659 CV_AMD64_MM31 = CV_REG_MM31, 660 CV_AMD64_MM40 = CV_REG_MM40, 661 CV_AMD64_MM41 = CV_REG_MM41, 662 CV_AMD64_MM50 = CV_REG_MM50, 663 CV_AMD64_MM51 = CV_REG_MM51, 664 CV_AMD64_MM60 = CV_REG_MM60, 665 CV_AMD64_MM61 = CV_REG_MM61, 666 CV_AMD64_MM70 = CV_REG_MM70, 667 CV_AMD64_MM71 = CV_REG_MM71, 668 669 CV_AMD64_XMM8 = 252, /* this includes XMM9 to XMM15 */ 670 671 CV_AMD64_RAX = 328, 672 CV_AMD64_RBX = 329, 673 CV_AMD64_RCX = 330, 674 CV_AMD64_RDX = 331, 675 CV_AMD64_RSI = 332, 676 CV_AMD64_RDI = 333, 677 CV_AMD64_RBP = 334, 678 CV_AMD64_RSP = 335, 679 680 CV_AMD64_R8 = 336, 681 CV_AMD64_R9 = 337, 682 CV_AMD64_R10 = 338, 683 CV_AMD64_R11 = 339, 684 CV_AMD64_R12 = 340, 685 CV_AMD64_R13 = 341, 686 CV_AMD64_R14 = 342, 687 CV_AMD64_R15 = 343, 688 }; 689 690 typedef enum 691 { 692 THUNK_ORDINAL_NOTYPE, 693 THUNK_ORDINAL_ADJUSTOR, 694 THUNK_ORDINAL_VCALL, 695 THUNK_ORDINAL_PCODE, 696 THUNK_ORDINAL_LOAD 697 } THUNK_ORDINAL; 698 699 typedef enum CV_call_e 700 { 701 CV_CALL_NEAR_C, 702 CV_CALL_FAR_C, 703 CV_CALL_NEAR_PASCAL, 704 CV_CALL_FAR_PASCAL, 705 CV_CALL_NEAR_FAST, 706 CV_CALL_FAR_FAST, 707 CV_CALL_SKIPPED, 708 CV_CALL_NEAR_STD, 709 CV_CALL_FAR_STD, 710 CV_CALL_NEAR_SYS, 711 CV_CALL_FAR_SYS, 712 CV_CALL_THISCALL, 713 CV_CALL_MIPSCALL, 714 CV_CALL_GENERIC, 715 CV_CALL_ALPHACALL, 716 CV_CALL_PPCCALL, 717 CV_CALL_SHCALL, 718 CV_CALL_ARMCALL, 719 CV_CALL_AM33CALL, 720 CV_CALL_TRICALL, 721 CV_CALL_SH5CALL, 722 CV_CALL_M32RCALL, 723 CV_CALL_RESERVED, 724 } CV_call_e; 725