1 /* 2 * PROJECT: ReactOS VGA Miniport Driver 3 * LICENSE: Microsoft NT4 DDK Sample Code License 4 * FILE: win32ss/drivers/miniport/vga_new/vgadata.c 5 * PURPOSE: Handles switching to VGA Modes and holds VGA Built-in Modes 6 * PROGRAMMERS: Copyright (c) 1992 Microsoft Corporation 7 * ReactOS Portable Systems Group 8 */ 9 10 #include "vga.h" 11 12 // 13 // This structure describes to which ports access is required. 14 // 15 16 VIDEO_ACCESS_RANGE VgaAccessRange[] = { 17 { 18 {{VGA_BASE_IO_PORT, 0x00000000}}, // 64-bit linear base address 19 // of range 20 VGA_START_BREAK_PORT - VGA_BASE_IO_PORT + 1, // # of ports 21 1, // range is in I/O space 22 1, // range should be visible 23 0 // range should be shareable 24 }, 25 { 26 {{VGA_END_BREAK_PORT, 0x00000000}}, 27 VGA_MAX_IO_PORT - VGA_END_BREAK_PORT + 1, 28 1, 29 1, 30 0 31 }, 32 33 // 34 // This next region also includes Memory mapped IO. In MMIO, the ports are 35 // repeated every 256 bytes from b8000 to bff00. 36 // 37 38 { 39 {{MEM_VGA, 0x00000000}}, 40 MEM_VGA_SIZE, 41 0, 42 1, 43 0 44 }, 45 // eVb: 4.1 [VGA] - Add ATI/Mach64 VGA registers 46 // 47 // ATI Registers 48 // 49 50 { 51 {{0x1CE, 0x00000000}}, 52 2, 53 1, 54 1, 55 0 56 }, 57 { 58 {{0x2E8, 0x00000000}}, 59 8, 60 1, 61 1, 62 0 63 } 64 // eVb: 4.1 [END] 65 }; 66 67 // 68 // 640x480 256-color 60Hz mode (BIOS mode 12) set command string for 69 // VGA. 70 // 71 // eVb: 4.2 [VGA] - Add VGA command streams instead of Cirrus 72 USHORT VGA_640x480[] = { 73 OWM, // begin setmode 74 SEQ_ADDRESS_PORT, 75 5, // count 76 0x100, // start sync reset 77 0x0101,0x0F02,0x0003,0x0604, // program up sequencer 78 79 OB, // misc. register 80 MISC_OUTPUT_REG_WRITE_PORT, 81 0xE3, 82 83 OW, // text/graphics bit 84 GRAPH_ADDRESS_PORT, 85 0x506, 86 87 OW, // end sync reset 88 SEQ_ADDRESS_PORT, 89 IND_SYNC_RESET, 90 91 OB, 92 SEQ_DATA_PORT, 93 END_SYNC_RESET_VALUE, 94 95 OW, // unprotect crtc 0-7 96 CRTC_ADDRESS_PORT_COLOR, 97 0x511, 98 99 METAOUT+INDXOUT, // program crtc registers 100 CRTC_ADDRESS_PORT_COLOR, 101 VGA_NUM_CRTC_PORTS,0, // count, startindex 102 0x5F,0x4F,0x50,0x82,0x54,0x80,0x0B,0x3E,0x00,0x40,0x0,0x0,0x0,0x0,0x0,0x0, 103 0xEA,0x8C,0xDF,0x28,0x0,0xE7,0x4,0xE3,0xFF, 104 105 IB, // prepare atc for writing 106 INPUT_STATUS_1_COLOR, 107 108 METAOUT+ATCOUT, // program atc registers 109 ATT_ADDRESS_PORT, 110 VGA_NUM_ATTRIB_CONT_PORTS,0, // count, startindex 111 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 112 0x17, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 113 0x3D, 0x3E, 0x3F, 0x3F, 0x01, 0x00, 114 0x0F, 0x00, 0x00, 115 116 METAOUT+INDXOUT, // program gdc registers 117 GRAPH_ADDRESS_PORT, 118 VGA_NUM_GRAPH_CONT_PORTS,0, // count, startindex 119 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 120 0x05, 0x0F, 0xFF, 121 122 OB, 123 DAC_PIXEL_MASK_PORT, 124 0xFF, 125 126 IB, // prepare atc for writing 127 INPUT_STATUS_1_COLOR, 128 129 OB, // turn video on. 130 ATT_ADDRESS_PORT, 131 VIDEO_ENABLE, 132 133 EOD 134 }; 135 136 // 137 // 720x400 color text mode (BIOS mode 3) set command string for 138 // VGA. 139 // 140 141 USHORT VGA_TEXT_0[] = { 142 OWM, // begin setmode 143 SEQ_ADDRESS_PORT, 144 5, // count 145 0x100, // start sync reset 146 0x0101,0x0302,0x0003,0x0204, // program up sequencer 147 148 OB, // misc. register 149 MISC_OUTPUT_REG_WRITE_PORT, 150 0x67, 151 152 OW, // text/graphics bit 153 GRAPH_ADDRESS_PORT, 154 0x0e06, 155 156 OW, // end sync reset 157 SEQ_ADDRESS_PORT, 158 IND_SYNC_RESET, 159 160 OB, 161 SEQ_DATA_PORT, 162 END_SYNC_RESET_VALUE, 163 164 OW, // unprotect crtc 0-7 165 CRTC_ADDRESS_PORT_COLOR, 166 0xE11, 167 168 METAOUT+INDXOUT, // program crtc registers 169 CRTC_ADDRESS_PORT_COLOR, 170 VGA_NUM_CRTC_PORTS,0, // count, startindex 171 0x5F,0x4F,0x50,0x82,0x55,0x81,0xBF,0x1F,0x00,0x4F,0xD,0xE,0x0,0x0,0x0,0x0, 172 0x9c,0x8E,0x8F,0x28,0x1F,0x96,0xB9,0xA3,0xFF, 173 174 IB, // prepare atc for writing 175 INPUT_STATUS_1_COLOR, 176 177 METAOUT+ATCOUT, // program atc registers 178 ATT_ADDRESS_PORT, 179 VGA_NUM_ATTRIB_CONT_PORTS,0, // count, startindex 180 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 181 0x17, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 182 0x3D, 0x3E, 0x3F, 0x3F, 0x04, 0x00, 183 0x0F, 0x08, 0x00, 184 185 METAOUT+INDXOUT, // program gdc registers 186 GRAPH_ADDRESS_PORT, 187 VGA_NUM_GRAPH_CONT_PORTS,0, // count, startindex 188 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 189 0x0E, 0x00, 0xFF, 190 191 OB, 192 DAC_PIXEL_MASK_PORT, 193 0xFF, 194 195 IB, // prepare atc for writing 196 INPUT_STATUS_1_COLOR, 197 198 OB, // turn video on. 199 ATT_ADDRESS_PORT, 200 VIDEO_ENABLE, 201 202 EOD 203 }; 204 205 // 206 // 640x400 color text mode (BIOS mode 3) set command string for 207 // VGA. 208 // 209 210 USHORT VGA_TEXT_1[] = { 211 OWM, // begin setmode 212 SEQ_ADDRESS_PORT, 213 5, // count 214 0x100, // start sync reset 215 0x0101,0x0302,0x0003,0x0204, // program up sequencer 216 217 OB, // misc. register 218 MISC_OUTPUT_REG_WRITE_PORT, 219 0xA3, 220 221 OW, // text/graphics bit 222 GRAPH_ADDRESS_PORT, 223 0x0e06, 224 225 OW, // end sync reset 226 SEQ_ADDRESS_PORT, 227 IND_SYNC_RESET, 228 229 OB, 230 SEQ_DATA_PORT, 231 END_SYNC_RESET_VALUE, 232 233 OW, // unprotect crtc 0-7 234 CRTC_ADDRESS_PORT_COLOR, 235 0x511, 236 237 METAOUT+INDXOUT, // program crtc registers 238 CRTC_ADDRESS_PORT_COLOR, 239 VGA_NUM_CRTC_PORTS,0, // count, startindex 240 0x5F,0x4F,0x50,0x82,0x55,0x81,0xBF,0x1F,0x00,0x4D,0xB,0xC,0x0,0x0,0x0,0x0, 241 0x83,0x85,0x5D,0x28,0x1F,0x63,0xBA,0xA3,0xFF, 242 243 IB, // prepare atc for writing 244 INPUT_STATUS_1_COLOR, 245 246 METAOUT+ATCOUT, // program atc registers 247 ATT_ADDRESS_PORT, 248 VGA_NUM_ATTRIB_CONT_PORTS,0, // count, startindex 249 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 250 0x17, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 251 0x3D, 0x3E, 0x3F, 0x3F, 0x04, 0x00, 252 0x0F, 0x00, 0x00, 253 254 METAOUT+INDXOUT, // program gdc registers 255 GRAPH_ADDRESS_PORT, 256 VGA_NUM_GRAPH_CONT_PORTS,0, // count, startindex 257 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 258 0x0E, 0x00, 0xFF, 259 260 OB, 261 DAC_PIXEL_MASK_PORT, 262 0xFF, 263 264 IB, // prepare atc for writing 265 INPUT_STATUS_1_COLOR, 266 267 OB, // turn video on. 268 ATT_ADDRESS_PORT, 269 VIDEO_ENABLE, 270 271 EOD 272 }; 273 // eVb: 4.2 [END] 274 // 275 // Video mode table - contains information and commands for initializing each 276 // mode. These entries must correspond with those in VIDEO_MODE_VGA. The first 277 // entry is commented; the rest follow the same format, but are not so 278 // heavily commented. 279 // 280 // eVb: 4.3 [VGA] - Add VGA, ModeX and SVGA mode instead of Cirrus Modes 281 VIDEOMODE ModesVGA[] = 282 { 283 // Color text mode 3, 720x400, 9x16 char cell (VGA). 284 // 285 { 286 VIDEO_MODE_BANKED | VIDEO_MODE_COLOR, // flags that this mode is a color mode, but not graphics 287 4, // four planes 288 1, // one bit of colour per plane 289 80, 25, // 80x25 text resolution 290 720, 400, // 720x400 pixels on screen 291 1, // only support one frequency, non-interlaced 292 160, 0x10000, // 160 bytes per scan line, 64K of CPU-addressable bitmap 293 FALSE, 294 0x3, VGA_TEXT_0, // Mode 3, I/O initialization stream 295 0xA0000, // Physical address at 0xA0000 296 0x18000, 0x8000, 297 0x20000, // 2 banks of 64K, 128KB total memory 298 720, // 720 pixels per scan line 299 FALSE, 300 0 301 }, 302 303 // 304 // Color text mode 3, 640x350, 8x14 char cell (EGA). 305 // 306 { 307 VIDEO_MODE_BANKED | VIDEO_MODE_COLOR, 308 4, 1, 309 80, 25, 310 640, 350, 311 1, 312 160, 0x10000, 313 FALSE, 314 0x3, VGA_TEXT_1, 315 0xA0000, 316 0x18000, 0x8000, 317 0x20000, 318 640, 319 FALSE, 320 0 321 }, 322 323 // 324 // 325 // Standard VGA Color graphics mode 0x12, 640x480 16 colors. 326 // 327 { 328 VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, 329 4, 1, 330 80, 30, 331 640, 480, 332 1, 333 80, 0x10000, 334 FALSE, 335 0x12, VGA_640x480, 336 0xA0000, 337 0, 0x20000, 338 0x20000, 339 640, 340 FALSE, 341 0 342 }, 343 344 { 345 VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, 346 8, 1, 347 0, 0, 348 320, 200, 349 70, 350 80, 0x10000, 351 FALSE, 352 0x3, NULL, 353 0xA0000, 354 0, 0x20000, 355 0x20000, 356 320, 357 FALSE, 358 0 359 }, 360 361 { 362 VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, 363 8, 1, 364 0, 0, 365 320, 240, 366 60, 367 80, 0x10000, 368 FALSE, 369 0x3, NULL, 370 0xA0000, 371 0, 0x20000, 372 0x20000, 373 320, 374 FALSE, 375 0 376 }, 377 378 { 379 VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, 380 8, 1, 381 0, 0, 382 320, 400, 383 70, 384 80, 0x10000, 385 FALSE, 386 0x3, NULL, 387 0xA0000, 388 0, 0x20000, 389 0x20000, 390 320, 391 FALSE, 392 0 393 }, 394 395 { 396 VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, 397 8, 1, 398 0, 0, 399 320, 480, 400 60, 401 80, 0x10000, 402 FALSE, 403 0x3, NULL, 404 0xA0000, 405 0, 0x20000, 406 0x20000, 407 320, 408 FALSE, 409 0 410 }, 411 412 // 413 // 800x600 16 colors. 414 // 415 { 416 VIDEO_MODE_BANKED | VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS, 417 4, 1, 418 100, 37, 419 800, 600, 420 1, 421 100, 0x10000, 422 FALSE, 423 (0x102 << 16) | VBE_SET_VBE_MODE, NULL, 424 0xA0000, 425 0, 0x20000, 426 0x20000, 427 800, 428 FALSE, 429 0 430 }, 431 }; 432 433 ULONG NumVideoModes = sizeof(ModesVGA) / sizeof(VIDEOMODE); 434 PVIDEOMODE VgaModeList; 435 // eVb: 4.3 [END] 436 437 // 438 // 439 // Data used to set the Graphics and Sequence Controllers to put the 440 // VGA into a planar state at A0000 for 64K, with plane 2 enabled for 441 // reads and writes, so that a font can be loaded, and to disable that mode. 442 // 443 444 // Settings to enable planar mode with plane 2 enabled. 445 // 446 447 USHORT EnableA000Data[] = { 448 OWM, 449 SEQ_ADDRESS_PORT, 450 1, 451 0x0100, 452 453 OWM, 454 GRAPH_ADDRESS_PORT, 455 3, 456 0x0204, // Read Map = plane 2 457 0x0005, // Graphics Mode = read mode 0, write mode 0 458 0x0406, // Graphics Miscellaneous register = A0000 for 64K, not odd/even, 459 // graphics mode 460 OWM, 461 SEQ_ADDRESS_PORT, 462 3, 463 0x0402, // Map Mask = write to plane 2 only 464 0x0404, // Memory Mode = not odd/even, not full memory, graphics mode 465 0x0300, // end sync reset 466 EOD 467 }; 468 469 // 470 // Settings to disable the font-loading planar mode. 471 // 472 473 USHORT DisableA000Color[] = { 474 OWM, 475 SEQ_ADDRESS_PORT, 476 1, 477 0x0100, 478 479 OWM, 480 GRAPH_ADDRESS_PORT, 481 3, 482 0x0004, 0x1005, 0x0E06, 483 484 OWM, 485 SEQ_ADDRESS_PORT, 486 3, 487 0x0302, 0x0204, 0x0300, // end sync reset 488 EOD 489 490 }; 491