1 // The local APIC manages internal (non-I/O) interrupts. 2 // See Chapter 8 & Appendix C of Intel processor manual volume 3. 3 4 #include "types.h" 5 #include "defs.h" 6 #include "traps.h" 7 #include "mmu.h" 8 #include "x86.h" 9 10 // Local APIC registers, divided by 4 for use as uint[] indices. 11 #define ID (0x0020/4) // ID 12 #define VER (0x0030/4) // Version 13 #define TPR (0x0080/4) // Task Priority 14 #define EOI (0x00B0/4) // EOI 15 #define SVR (0x00F0/4) // Spurious Interrupt Vector 16 #define ENABLE 0x00000100 // Unit Enable 17 #define ESR (0x0280/4) // Error Status 18 #define ICRLO (0x0300/4) // Interrupt Command 19 #define INIT 0x00000500 // INIT/RESET 20 #define STARTUP 0x00000600 // Startup IPI 21 #define DELIVS 0x00001000 // Delivery status 22 #define ASSERT 0x00004000 // Assert interrupt (vs deassert) 23 #define LEVEL 0x00008000 // Level triggered 24 #define BCAST 0x00080000 // Send to all APICs, including self. 25 #define ICRHI (0x0310/4) // Interrupt Command [63:32] 26 #define TIMER (0x0320/4) // Local Vector Table 0 (TIMER) 27 #define X1 0x0000000B // divide counts by 1 28 #define PERIODIC 0x00020000 // Periodic 29 #define PCINT (0x0340/4) // Performance Counter LVT 30 #define LINT0 (0x0350/4) // Local Vector Table 1 (LINT0) 31 #define LINT1 (0x0360/4) // Local Vector Table 2 (LINT1) 32 #define ERROR (0x0370/4) // Local Vector Table 3 (ERROR) 33 #define MASKED 0x00010000 // Interrupt masked 34 #define TICR (0x0380/4) // Timer Initial Count 35 #define TCCR (0x0390/4) // Timer Current Count 36 #define TDCR (0x03E0/4) // Timer Divide Configuration 37 38 volatile uint *lapic; // Initialized in mp.c 39 40 static void 41 lapicw(int index, int value) 42 { 43 lapic[index] = value; 44 lapic[ID]; // wait for write to finish, by reading 45 } 46 47 //PAGEBREAK! 48 void 49 lapicinit(int c) 50 { 51 if(!lapic) 52 return; 53 54 // Enable local APIC; set spurious interrupt vector. 55 lapicw(SVR, ENABLE | (IRQ_OFFSET+IRQ_SPURIOUS)); 56 57 // The timer repeatedly counts down at bus frequency 58 // from lapic[TICR] and then issues an interrupt. 59 // If xv6 cared more about precise timekeeping, 60 // TICR would be calibrated using an external time source. 61 lapicw(TDCR, X1); 62 lapicw(TIMER, PERIODIC | (IRQ_OFFSET + IRQ_TIMER)); 63 lapicw(TICR, 10000000); 64 65 // Disable logical interrupt lines. 66 lapicw(LINT0, MASKED); 67 lapicw(LINT1, MASKED); 68 69 // Disable performance counter overflow interrupts 70 // on machines that provide that interrupt entry. 71 if(((lapic[VER]>>16) & 0xFF) >= 4) 72 lapicw(PCINT, MASKED); 73 74 // Map error interrupt to IRQ_ERROR. 75 lapicw(ERROR, IRQ_OFFSET+IRQ_ERROR); 76 77 // Clear error status register (requires back-to-back writes). 78 lapicw(ESR, 0); 79 lapicw(ESR, 0); 80 81 // Ack any outstanding interrupts. 82 lapicw(EOI, 0); 83 84 // Send an Init Level De-Assert to synchronise arbitration ID's. 85 lapicw(ICRHI, 0); 86 lapicw(ICRLO, BCAST | INIT | LEVEL); 87 while(lapic[ICRLO] & DELIVS) 88 ; 89 90 // Enable interrupts on the APIC (but not on the processor). 91 lapicw(TPR, 0); 92 } 93 94 int 95 cpu(void) 96 { 97 // Cannot call cpu when interrupts are enabled: 98 // result not guaranteed to last long enough to be used! 99 // Would prefer to panic but even printing is chancy here: 100 // almost everything, including cprintf and panic, calls cpu, 101 // often indirectly through acquire and release. 102 if(readeflags()&FL_IF){ 103 static int n; 104 if(n++ == 0) 105 cprintf("cpu called from %x with interrupts enabled\n", 106 __builtin_return_address(0)); 107 } 108 109 if(lapic) 110 return lapic[ID]>>24; 111 return 0; 112 } 113 114 // Acknowledge interrupt. 115 void 116 lapiceoi(void) 117 { 118 if(lapic) 119 lapicw(EOI, 0); 120 } 121 122 // Spin for a given number of microseconds. 123 // On real hardware would want to tune this dynamically. 124 void 125 microdelay(int us) 126 { 127 volatile int j = 0; 128 129 while(us-- > 0) 130 for(j=0; j<10000; j++); 131 } 132 133 134 #define IO_RTC 0x70 135 136 // Start additional processor running bootstrap code at addr. 137 // See Appendix B of MultiProcessor Specification. 138 void 139 lapicstartap(uchar apicid, uint addr) 140 { 141 int i; 142 ushort *wrv; 143 144 // "The BSP must initialize CMOS shutdown code to 0AH 145 // and the warm reset vector (DWORD based at 40:67) to point at 146 // the AP startup code prior to the [universal startup algorithm]." 147 outb(IO_RTC, 0xF); // offset 0xF is shutdown code 148 outb(IO_RTC+1, 0x0A); 149 wrv = (ushort*)(0x40<<4 | 0x67); // Warm reset vector 150 wrv[0] = 0; 151 wrv[1] = addr >> 4; 152 153 // "Universal startup algorithm." 154 // Send INIT (level-triggered) interrupt to reset other CPU. 155 lapicw(ICRHI, apicid<<24); 156 lapicw(ICRLO, INIT | LEVEL | ASSERT); 157 microdelay(200); 158 lapicw(ICRLO, INIT | LEVEL); 159 microdelay(100); // should be 10ms, but too slow in Bochs! 160 161 // Send startup IPI (twice!) to enter bootstrap code. 162 // Regular hardware is supposed to only accept a STARTUP 163 // when it is in the halted state due to an INIT. So the second 164 // should be ignored, but it is part of the official Intel algorithm. 165 // Bochs complains about the second one. Too bad for Bochs. 166 for(i = 0; i < 2; i++){ 167 lapicw(ICRHI, apicid<<24); 168 lapicw(ICRLO, STARTUP | (addr>>12)); 169 microdelay(200); 170 } 171 } 172