1 // The local APIC manages internal (non-I/O) interrupts. 2 // See Chapter 8 & Appendix C of Intel processor manual volume 3. 3 4 #include "types.h" 5 #include "defs.h" 6 #include "traps.h" 7 #include "mmu.h" 8 #include "x86.h" 9 10 // Local APIC registers, divided by 4 for use as uint[] indices. 11 #define ID (0x0020/4) // ID 12 #define VER (0x0030/4) // Version 13 #define TPR (0x0080/4) // Task Priority 14 #define EOI (0x00B0/4) // EOI 15 #define SVR (0x00F0/4) // Spurious Interrupt Vector 16 #define ENABLE 0x00000100 // Unit Enable 17 #define ESR (0x0280/4) // Error Status 18 #define ICRLO (0x0300/4) // Interrupt Command 19 #define INIT 0x00000500 // INIT/RESET 20 #define STARTUP 0x00000600 // Startup IPI 21 #define DELIVS 0x00001000 // Delivery status 22 #define ASSERT 0x00004000 // Assert interrupt (vs deassert) 23 #define LEVEL 0x00008000 // Level triggered 24 #define BCAST 0x00080000 // Send to all APICs, including self. 25 #define ICRHI (0x0310/4) // Interrupt Command [63:32] 26 #define TIMER (0x0320/4) // Local Vector Table 0 (TIMER) 27 #define X1 0x0000000B // divide counts by 1 28 #define PERIODIC 0x00020000 // Periodic 29 #define PCINT (0x0340/4) // Performance Counter LVT 30 #define LINT0 (0x0350/4) // Local Vector Table 1 (LINT0) 31 #define LINT1 (0x0360/4) // Local Vector Table 2 (LINT1) 32 #define ERROR (0x0370/4) // Local Vector Table 3 (ERROR) 33 #define MASKED 0x00010000 // Interrupt masked 34 #define TICR (0x0380/4) // Timer Initial Count 35 #define TCCR (0x0390/4) // Timer Current Count 36 #define TDCR (0x03E0/4) // Timer Divide Configuration 37 38 volatile uint *lapic; // Initialized in mp.c 39 40 static void 41 lapicw(int index, int value) 42 { 43 lapic[index] = value; 44 lapic[ID]; // wait for write to finish, by reading 45 } 46 47 //PAGEBREAK! 48 void 49 lapicinit(int c) 50 { 51 cprintf("lapicinit: %d 0x%x\n", c, lapic); 52 if(!lapic) 53 return; 54 55 // Enable local APIC; set spurious interrupt vector. 56 lapicw(SVR, ENABLE | (T_IRQ0 + IRQ_SPURIOUS)); 57 58 // The timer repeatedly counts down at bus frequency 59 // from lapic[TICR] and then issues an interrupt. 60 // If xv6 cared more about precise timekeeping, 61 // TICR would be calibrated using an external time source. 62 lapicw(TDCR, X1); 63 lapicw(TIMER, PERIODIC | (T_IRQ0 + IRQ_TIMER)); 64 lapicw(TICR, 10000000); 65 66 // Disable logical interrupt lines. 67 lapicw(LINT0, MASKED); 68 lapicw(LINT1, MASKED); 69 70 // Disable performance counter overflow interrupts 71 // on machines that provide that interrupt entry. 72 if(((lapic[VER]>>16) & 0xFF) >= 4) 73 lapicw(PCINT, MASKED); 74 75 // Map error interrupt to IRQ_ERROR. 76 lapicw(ERROR, T_IRQ0 + IRQ_ERROR); 77 78 // Clear error status register (requires back-to-back writes). 79 lapicw(ESR, 0); 80 lapicw(ESR, 0); 81 82 // Ack any outstanding interrupts. 83 lapicw(EOI, 0); 84 85 // Send an Init Level De-Assert to synchronise arbitration ID's. 86 lapicw(ICRHI, 0); 87 lapicw(ICRLO, BCAST | INIT | LEVEL); 88 while(lapic[ICRLO] & DELIVS) 89 ; 90 91 // Enable interrupts on the APIC (but not on the processor). 92 lapicw(TPR, 0); 93 } 94 95 int 96 cpunum(void) 97 { 98 // Cannot call cpu when interrupts are enabled: 99 // result not guaranteed to last long enough to be used! 100 // Would prefer to panic but even printing is chancy here: 101 // almost everything, including cprintf and panic, calls cpu, 102 // often indirectly through acquire and release. 103 if(readeflags()&FL_IF){ 104 static int n; 105 if(n++ == 0) 106 cprintf("cpu called from %x with interrupts enabled\n", 107 __builtin_return_address(0)); 108 } 109 110 if(lapic) 111 return lapic[ID]>>24; 112 return 0; 113 } 114 115 // Acknowledge interrupt. 116 void 117 lapiceoi(void) 118 { 119 if(lapic) 120 lapicw(EOI, 0); 121 } 122 123 // Spin for a given number of microseconds. 124 // On real hardware would want to tune this dynamically. 125 void 126 microdelay(int us) 127 { 128 } 129 130 131 #define IO_RTC 0x70 132 133 // Start additional processor running bootstrap code at addr. 134 // See Appendix B of MultiProcessor Specification. 135 void 136 lapicstartap(uchar apicid, uint addr) 137 { 138 int i; 139 ushort *wrv; 140 141 // "The BSP must initialize CMOS shutdown code to 0AH 142 // and the warm reset vector (DWORD based at 40:67) to point at 143 // the AP startup code prior to the [universal startup algorithm]." 144 outb(IO_RTC, 0xF); // offset 0xF is shutdown code 145 outb(IO_RTC+1, 0x0A); 146 wrv = (ushort*)(0x40<<4 | 0x67); // Warm reset vector 147 wrv[0] = 0; 148 wrv[1] = addr >> 4; 149 150 // "Universal startup algorithm." 151 // Send INIT (level-triggered) interrupt to reset other CPU. 152 lapicw(ICRHI, apicid<<24); 153 lapicw(ICRLO, INIT | LEVEL | ASSERT); 154 microdelay(200); 155 lapicw(ICRLO, INIT | LEVEL); 156 microdelay(100); // should be 10ms, but too slow in Bochs! 157 158 // Send startup IPI (twice!) to enter bootstrap code. 159 // Regular hardware is supposed to only accept a STARTUP 160 // when it is in the halted state due to an INIT. So the second 161 // should be ignored, but it is part of the official Intel algorithm. 162 // Bochs complains about the second one. Too bad for Bochs. 163 for(i = 0; i < 2; i++){ 164 lapicw(ICRHI, apicid<<24); 165 lapicw(ICRLO, STARTUP | (addr>>12)); 166 microdelay(200); 167 } 168 } 169