10cfc7290Srsc // This file contains definitions for the 20cfc7290Srsc // x86 memory management unit (MMU). 355e95b16Srtm 455e95b16Srtm // Eflags register 53c821bf9Srsc #define FL_IF 0x00000200 // Interrupt Enable 655e95b16Srtm 77914ab72SAustin Clements // Control Register flags 87914ab72SAustin Clements #define CR0_PE 0x00000001 // Protection Enable 97914ab72SAustin Clements #define CR0_WP 0x00010000 // Write Protect 107914ab72SAustin Clements #define CR0_PG 0x80000000 // Paging 117914ab72SAustin Clements 1294496468SFrans Kaashoek #define CR4_PSE 0x00000010 // Page size extension 1394496468SFrans Kaashoek 14858475e4SRobert Morris // various segment selectors. 15a56c8d60SFrans Kaashoek #define SEG_KCODE 1 // kernel code 16a56c8d60SFrans Kaashoek #define SEG_KDATA 2 // kernel data+stack 17ed396c06SFrans Kaashoek #define SEG_UCODE 3 // user code 18ed396c06SFrans Kaashoek #define SEG_UDATA 4 // user data+stack 19ed396c06SFrans Kaashoek #define SEG_TSS 5 // this process's task state 20a56c8d60SFrans Kaashoek 21858475e4SRobert Morris // cpu->gdt[NSEGS] holds the above segments. 22ed396c06SFrans Kaashoek #define NSEGS 6 23858475e4SRobert Morris 24a56c8d60SFrans Kaashoek #ifndef __ASSEMBLER__ 25dfcc5b99Srtm // Segment Descriptor 26b5f17007Srsc struct segdesc { 27b5ee5165Srsc uint lim_15_0 : 16; // Low bits of segment limit 28b5ee5165Srsc uint base_15_0 : 16; // Low bits of segment base address 29b5ee5165Srsc uint base_23_16 : 8; // Middle bits of segment base address 30b5ee5165Srsc uint type : 4; // Segment type (see STS_ constants) 31b5ee5165Srsc uint s : 1; // 0 = system, 1 = application 32b5ee5165Srsc uint dpl : 2; // Descriptor Privilege Level 33b5ee5165Srsc uint p : 1; // Present 34b5ee5165Srsc uint lim_19_16 : 4; // High bits of segment limit 35b5ee5165Srsc uint avl : 1; // Unused (available for software use) 36b5ee5165Srsc uint rsv1 : 1; // Reserved 37b5ee5165Srsc uint db : 1; // 0 = 16-bit segment, 1 = 32-bit segment 38b5ee5165Srsc uint g : 1; // Granularity: limit scaled by 4K when set 39b5ee5165Srsc uint base_31_24 : 8; // High bits of segment base address 4055e95b16Srtm }; 41dfcc5b99Srtm 4255e95b16Srtm // Normal segment 43b5f17007Srsc #define SEG(type, base, lim, dpl) (struct segdesc) \ 4448755214SRuss Cox { ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff, \ 4548755214SRuss Cox ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 4648755214SRuss Cox (uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 } 47b5f17007Srsc #define SEG16(type, base, lim, dpl) (struct segdesc) \ 4848755214SRuss Cox { (lim) & 0xffff, (uint)(base) & 0xffff, \ 4948755214SRuss Cox ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 5048755214SRuss Cox (uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 } 51a56c8d60SFrans Kaashoek #endif 5255e95b16Srtm 53b6dc6187Srsc #define DPL_USER 0x3 // User DPL 54b6dc6187Srsc 5555e95b16Srtm // Application segment type bits 5655e95b16Srtm #define STA_X 0x8 // Executable segment 5755e95b16Srtm #define STA_W 0x2 // Writeable (non-executable segments) 5855e95b16Srtm #define STA_R 0x2 // Readable (executable segments) 5955e95b16Srtm 6055e95b16Srtm // System segment type bits 6155e95b16Srtm #define STS_T32A 0x9 // Available 32-bit TSS 6255e95b16Srtm #define STS_IG32 0xE // 32-bit Interrupt Gate 6355e95b16Srtm #define STS_TG32 0xF // 32-bit Trap Gate 6455e95b16Srtm 65c3dcf479SFrans Kaashoek // A virtual address 'la' has a three-part structure as follows: 6640889627SFrans Kaashoek // 6740889627SFrans Kaashoek // +--------10------+-------10-------+---------12----------+ 6840889627SFrans Kaashoek // | Page Directory | Page Table | Offset within Page | 6940889627SFrans Kaashoek // | Index | Index | | 7040889627SFrans Kaashoek // +----------------+----------------+---------------------+ 71c3dcf479SFrans Kaashoek // \--- PDX(va) --/ \--- PTX(va) --/ 7240889627SFrans Kaashoek 7340889627SFrans Kaashoek // page directory index 74c3dcf479SFrans Kaashoek #define PDX(va) (((uint)(va) >> PDXSHIFT) & 0x3FF) 7540889627SFrans Kaashoek 7640889627SFrans Kaashoek // page table index 77c3dcf479SFrans Kaashoek #define PTX(va) (((uint)(va) >> PTXSHIFT) & 0x3FF) 7840889627SFrans Kaashoek 79c3dcf479SFrans Kaashoek // construct virtual address from indexes and offset 8040889627SFrans Kaashoek #define PGADDR(d, t, o) ((uint)((d) << PDXSHIFT | (t) << PTXSHIFT | (o))) 8140889627SFrans Kaashoek 8240889627SFrans Kaashoek // Page directory and page table constants. 83e25b74caSFrans Kaashoek #define NPDENTRIES 1024 // # directory entries per page directory 84e25b74caSFrans Kaashoek #define NPTENTRIES 1024 // # PTEs per page table 85c3dcf479SFrans Kaashoek #define PGSIZE 4096 // bytes mapped by a page 8640889627SFrans Kaashoek 8740889627SFrans Kaashoek #define PTXSHIFT 12 // offset of PTX in a linear address 8840889627SFrans Kaashoek #define PDXSHIFT 22 // offset of PDX in a linear address 8940889627SFrans Kaashoek 90eb18645fSRobert Morris #define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1)) 91c3dcf479SFrans Kaashoek #define PGROUNDDOWN(a) (((a)) & ~(PGSIZE-1)) 92eb18645fSRobert Morris 9340889627SFrans Kaashoek // Page table/directory entry flags. 9440889627SFrans Kaashoek #define PTE_P 0x001 // Present 9540889627SFrans Kaashoek #define PTE_W 0x002 // Writeable 9640889627SFrans Kaashoek #define PTE_U 0x004 // User 9740889627SFrans Kaashoek #define PTE_PS 0x080 // Page Size 9840889627SFrans Kaashoek 9940889627SFrans Kaashoek // Address in page table or page directory entry 10040889627SFrans Kaashoek #define PTE_ADDR(pte) ((uint)(pte) & ~0xFFF) 101ff278344SStephen Tu #define PTE_FLAGS(pte) ((uint)(pte) & 0xFFF) 10240889627SFrans Kaashoek 103a56c8d60SFrans Kaashoek #ifndef __ASSEMBLER__ 10440889627SFrans Kaashoek typedef uint pte_t; 10540889627SFrans Kaashoek 106dfcc5b99Srtm // Task state segment format 107b5f17007Srsc struct taskstate { 10829270816Srtm uint link; // Old ts selector 10911a9947fSrtm uint esp0; // Stack pointers and segment selectors 11029270816Srtm ushort ss0; // after an increase in privilege level 11129270816Srtm ushort padding1; 11229270816Srtm uint *esp1; 11329270816Srtm ushort ss1; 11429270816Srtm ushort padding2; 11529270816Srtm uint *esp2; 11629270816Srtm ushort ss2; 11729270816Srtm ushort padding3; 11829270816Srtm void *cr3; // Page directory base 11929270816Srtm uint *eip; // Saved state from last task switch 12029270816Srtm uint eflags; 12129270816Srtm uint eax; // More saved state (registers) 12229270816Srtm uint ecx; 12329270816Srtm uint edx; 12429270816Srtm uint ebx; 12529270816Srtm uint *esp; 12629270816Srtm uint *ebp; 12729270816Srtm uint esi; 12829270816Srtm uint edi; 12929270816Srtm ushort es; // Even more saved state (segment selectors) 13029270816Srtm ushort padding4; 13129270816Srtm ushort cs; 13229270816Srtm ushort padding5; 13329270816Srtm ushort ss; 13429270816Srtm ushort padding6; 13529270816Srtm ushort ds; 13629270816Srtm ushort padding7; 13729270816Srtm ushort fs; 13829270816Srtm ushort padding8; 13929270816Srtm ushort gs; 14029270816Srtm ushort padding9; 14129270816Srtm ushort ldt; 14229270816Srtm ushort padding10; 14329270816Srtm ushort t; // Trap on task switch 14429270816Srtm ushort iomb; // I/O map base address 14555e95b16Srtm }; 14655e95b16Srtm 14755e95b16Srtm // Gate descriptors for interrupts and traps 148b5f17007Srsc struct gatedesc { 149b5ee5165Srsc uint off_15_0 : 16; // low 16 bits of offset in segment 1500fe118f3Srsc uint cs : 16; // code segment selector 151b5ee5165Srsc uint args : 5; // # args, 0 for interrupt/trap gates 152b5ee5165Srsc uint rsv1 : 3; // reserved(should be zero I guess) 153*210a0f0bSFrans Kaashoek uint type : 4; // type(STS_{IG32,TG32}) 154b5ee5165Srsc uint s : 1; // must be 0 (system) 155b5ee5165Srsc uint dpl : 2; // descriptor(meaning new) privilege level 156b5ee5165Srsc uint p : 1; // Present 157b5ee5165Srsc uint off_31_16 : 16; // high bits of offset in segment 15855e95b16Srtm }; 15955e95b16Srtm 16055e95b16Srtm // Set up a normal interrupt/trap gate descriptor. 16155e95b16Srtm // - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate. 1625be0039cSrtm // interrupt gate clears FL_IF, trap gate leaves FL_IF alone 16355e95b16Srtm // - sel: Code segment selector for interrupt/trap handler 16455e95b16Srtm // - off: Offset in code segment for interrupt/trap handler 16555e95b16Srtm // - dpl: Descriptor Privilege Level - 16655e95b16Srtm // the privilege level required for software to invoke 16755e95b16Srtm // this interrupt/trap gate explicitly using an int instruction. 168ef2bd07aSrsc #define SETGATE(gate, istrap, sel, off, d) \ 16955e95b16Srtm { \ 17029270816Srtm (gate).off_15_0 = (uint)(off) & 0xffff; \ 1710fe118f3Srsc (gate).cs = (sel); \ 172ef2bd07aSrsc (gate).args = 0; \ 173ef2bd07aSrsc (gate).rsv1 = 0; \ 174ef2bd07aSrsc (gate).type = (istrap) ? STS_TG32 : STS_IG32; \ 175ef2bd07aSrsc (gate).s = 0; \ 176ef2bd07aSrsc (gate).dpl = (d); \ 177ef2bd07aSrsc (gate).p = 1; \ 17829270816Srtm (gate).off_31_16 = (uint)(off) >> 16; \ 17955e95b16Srtm } 18055e95b16Srtm 181a56c8d60SFrans Kaashoek #endif 182