10cfc7290Srsc // This file contains definitions for the 20cfc7290Srsc // x86 memory management unit (MMU). 355e95b16Srtm 455e95b16Srtm // Eflags register 555e95b16Srtm #define FL_CF 0x00000001 // Carry Flag 655e95b16Srtm #define FL_PF 0x00000004 // Parity Flag 755e95b16Srtm #define FL_AF 0x00000010 // Auxiliary carry Flag 855e95b16Srtm #define FL_ZF 0x00000040 // Zero Flag 955e95b16Srtm #define FL_SF 0x00000080 // Sign Flag 1055e95b16Srtm #define FL_TF 0x00000100 // Trap Flag 113c821bf9Srsc #define FL_IF 0x00000200 // Interrupt Enable 1255e95b16Srtm #define FL_DF 0x00000400 // Direction Flag 1355e95b16Srtm #define FL_OF 0x00000800 // Overflow Flag 1455e95b16Srtm #define FL_IOPL_MASK 0x00003000 // I/O Privilege Level bitmask 1555e95b16Srtm #define FL_IOPL_0 0x00000000 // IOPL == 0 1655e95b16Srtm #define FL_IOPL_1 0x00001000 // IOPL == 1 1755e95b16Srtm #define FL_IOPL_2 0x00002000 // IOPL == 2 1855e95b16Srtm #define FL_IOPL_3 0x00003000 // IOPL == 3 1955e95b16Srtm #define FL_NT 0x00004000 // Nested Task 2055e95b16Srtm #define FL_RF 0x00010000 // Resume Flag 2155e95b16Srtm #define FL_VM 0x00020000 // Virtual 8086 mode 2255e95b16Srtm #define FL_AC 0x00040000 // Alignment Check 2355e95b16Srtm #define FL_VIF 0x00080000 // Virtual Interrupt Flag 2455e95b16Srtm #define FL_VIP 0x00100000 // Virtual Interrupt Pending 2555e95b16Srtm #define FL_ID 0x00200000 // ID flag 2655e95b16Srtm 27dfcc5b99Srtm // Segment Descriptor 28b5f17007Srsc struct segdesc { 29b5ee5165Srsc uint lim_15_0 : 16; // Low bits of segment limit 30b5ee5165Srsc uint base_15_0 : 16; // Low bits of segment base address 31b5ee5165Srsc uint base_23_16 : 8; // Middle bits of segment base address 32b5ee5165Srsc uint type : 4; // Segment type (see STS_ constants) 33b5ee5165Srsc uint s : 1; // 0 = system, 1 = application 34b5ee5165Srsc uint dpl : 2; // Descriptor Privilege Level 35b5ee5165Srsc uint p : 1; // Present 36b5ee5165Srsc uint lim_19_16 : 4; // High bits of segment limit 37b5ee5165Srsc uint avl : 1; // Unused (available for software use) 38b5ee5165Srsc uint rsv1 : 1; // Reserved 39b5ee5165Srsc uint db : 1; // 0 = 16-bit segment, 1 = 32-bit segment 40b5ee5165Srsc uint g : 1; // Granularity: limit scaled by 4K when set 41b5ee5165Srsc uint base_31_24 : 8; // High bits of segment base address 4255e95b16Srtm }; 43dfcc5b99Srtm 4455e95b16Srtm // Normal segment 45b5f17007Srsc #define SEG(type, base, lim, dpl) (struct segdesc) \ 4648755214SRuss Cox { ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff, \ 4748755214SRuss Cox ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 4848755214SRuss Cox (uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 } 49dfcc5b99Srtm 50b5f17007Srsc #define SEG16(type, base, lim, dpl) (struct segdesc) \ 5148755214SRuss Cox { (lim) & 0xffff, (uint)(base) & 0xffff, \ 5248755214SRuss Cox ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 5348755214SRuss Cox (uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 } 5455e95b16Srtm 55b6dc6187Srsc #define DPL_USER 0x3 // User DPL 56b6dc6187Srsc 5755e95b16Srtm // Application segment type bits 5855e95b16Srtm #define STA_X 0x8 // Executable segment 5955e95b16Srtm #define STA_E 0x4 // Expand down (non-executable segments) 6055e95b16Srtm #define STA_C 0x4 // Conforming code segment (executable only) 6155e95b16Srtm #define STA_W 0x2 // Writeable (non-executable segments) 6255e95b16Srtm #define STA_R 0x2 // Readable (executable segments) 6355e95b16Srtm #define STA_A 0x1 // Accessed 6455e95b16Srtm 65*40889627SFrans Kaashoek // 66*40889627SFrans Kaashoek 6755e95b16Srtm // System segment type bits 6855e95b16Srtm #define STS_T16A 0x1 // Available 16-bit TSS 6955e95b16Srtm #define STS_LDT 0x2 // Local Descriptor Table 7055e95b16Srtm #define STS_T16B 0x3 // Busy 16-bit TSS 7155e95b16Srtm #define STS_CG16 0x4 // 16-bit Call Gate 7255e95b16Srtm #define STS_TG 0x5 // Task Gate / Coum Transmitions 7355e95b16Srtm #define STS_IG16 0x6 // 16-bit Interrupt Gate 7455e95b16Srtm #define STS_TG16 0x7 // 16-bit Trap Gate 7555e95b16Srtm #define STS_T32A 0x9 // Available 32-bit TSS 7655e95b16Srtm #define STS_T32B 0xB // Busy 32-bit TSS 7755e95b16Srtm #define STS_CG32 0xC // 32-bit Call Gate 7855e95b16Srtm #define STS_IG32 0xE // 32-bit Interrupt Gate 7955e95b16Srtm #define STS_TG32 0xF // 32-bit Trap Gate 8055e95b16Srtm 81*40889627SFrans Kaashoek 82*40889627SFrans Kaashoek // A linear address 'la' has a three-part structure as follows: 83*40889627SFrans Kaashoek // 84*40889627SFrans Kaashoek // +--------10------+-------10-------+---------12----------+ 85*40889627SFrans Kaashoek // | Page Directory | Page Table | Offset within Page | 86*40889627SFrans Kaashoek // | Index | Index | | 87*40889627SFrans Kaashoek // +----------------+----------------+---------------------+ 88*40889627SFrans Kaashoek // \--- PDX(la) --/ \--- PTX(la) --/ \---- PGOFF(la) ----/ 89*40889627SFrans Kaashoek // \----------- PPN(la) -----------/ 90*40889627SFrans Kaashoek // 91*40889627SFrans Kaashoek // The PDX, PTX, PGOFF, and PPN macros decompose linear addresses as shown. 92*40889627SFrans Kaashoek // To construct a linear address la from PDX(la), PTX(la), and PGOFF(la), 93*40889627SFrans Kaashoek // use PGADDR(PDX(la), PTX(la), PGOFF(la)). 94*40889627SFrans Kaashoek 95*40889627SFrans Kaashoek // page number field of address 96*40889627SFrans Kaashoek #define PPN(la) (((uint) (la)) >> PTXSHIFT) 97*40889627SFrans Kaashoek #define VPN(la) PPN(la) // used to index into vpt[] 98*40889627SFrans Kaashoek 99*40889627SFrans Kaashoek // page directory index 100*40889627SFrans Kaashoek #define PDX(la) ((((uint) (la)) >> PDXSHIFT) & 0x3FF) 101*40889627SFrans Kaashoek #define VPD(la) PDX(la) // used to index into vpd[] 102*40889627SFrans Kaashoek 103*40889627SFrans Kaashoek // page table index 104*40889627SFrans Kaashoek #define PTX(la) ((((uint) (la)) >> PTXSHIFT) & 0x3FF) 105*40889627SFrans Kaashoek 106*40889627SFrans Kaashoek // offset in page 107*40889627SFrans Kaashoek #define PGOFF(la) (((uint) (la)) & 0xFFF) 108*40889627SFrans Kaashoek 109*40889627SFrans Kaashoek // construct linear address from indexes and offset 110*40889627SFrans Kaashoek #define PGADDR(d, t, o) ((uint) ((d) << PDXSHIFT | (t) << PTXSHIFT | (o))) 111*40889627SFrans Kaashoek 112*40889627SFrans Kaashoek // mapping from physical addresses to virtual addresses is the identity one 113*40889627SFrans Kaashoek // (really linear addresses, but we map linear to physical also directly) 114*40889627SFrans Kaashoek #define PADDR(a) ((uint) a) 115*40889627SFrans Kaashoek 116*40889627SFrans Kaashoek // Page directory and page table constants. 117*40889627SFrans Kaashoek #define NPDENTRIES 1024 // page directory entries per page directory 118*40889627SFrans Kaashoek #define NPTENTRIES 1024 // page table entries per page table 119*40889627SFrans Kaashoek 120*40889627SFrans Kaashoek #define PGSIZE 4096 // bytes mapped by a page 121*40889627SFrans Kaashoek #define PGSHIFT 12 // log2(PGSIZE) 122*40889627SFrans Kaashoek 123*40889627SFrans Kaashoek #define PTSIZE (PGSIZE*NPTENTRIES) // bytes mapped by a page directory entry 124*40889627SFrans Kaashoek #define PTSHIFT 22 // log2(PTSIZE) 125*40889627SFrans Kaashoek 126*40889627SFrans Kaashoek #define PTXSHIFT 12 // offset of PTX in a linear address 127*40889627SFrans Kaashoek #define PDXSHIFT 22 // offset of PDX in a linear address 128*40889627SFrans Kaashoek 129*40889627SFrans Kaashoek // Page table/directory entry flags. 130*40889627SFrans Kaashoek #define PTE_P 0x001 // Present 131*40889627SFrans Kaashoek #define PTE_W 0x002 // Writeable 132*40889627SFrans Kaashoek #define PTE_U 0x004 // User 133*40889627SFrans Kaashoek #define PTE_PWT 0x008 // Write-Through 134*40889627SFrans Kaashoek #define PTE_PCD 0x010 // Cache-Disable 135*40889627SFrans Kaashoek #define PTE_A 0x020 // Accessed 136*40889627SFrans Kaashoek #define PTE_D 0x040 // Dirty 137*40889627SFrans Kaashoek #define PTE_PS 0x080 // Page Size 138*40889627SFrans Kaashoek #define PTE_MBZ 0x180 // Bits must be zero 139*40889627SFrans Kaashoek 140*40889627SFrans Kaashoek // The PTE_AVAIL bits aren't used by the kernel or interpreted by the 141*40889627SFrans Kaashoek // hardware, so user processes are allowed to set them arbitrarily. 142*40889627SFrans Kaashoek #define PTE_AVAIL 0xE00 // Available for software use 143*40889627SFrans Kaashoek 144*40889627SFrans Kaashoek // Only flags in PTE_USER may be used in system calls. 145*40889627SFrans Kaashoek #define PTE_USER (PTE_AVAIL | PTE_P | PTE_W | PTE_U) 146*40889627SFrans Kaashoek 147*40889627SFrans Kaashoek // Address in page table or page directory entry 148*40889627SFrans Kaashoek #define PTE_ADDR(pte) ((uint) (pte) & ~0xFFF) 149*40889627SFrans Kaashoek 150*40889627SFrans Kaashoek typedef uint pte_t; 151*40889627SFrans Kaashoek typedef uint pde_t; 152*40889627SFrans Kaashoek 153*40889627SFrans Kaashoek // Control Register flags 154*40889627SFrans Kaashoek #define CR0_PE 0x00000001 // Protection Enable 155*40889627SFrans Kaashoek #define CR0_MP 0x00000002 // Monitor coProcessor 156*40889627SFrans Kaashoek #define CR0_EM 0x00000004 // Emulation 157*40889627SFrans Kaashoek #define CR0_TS 0x00000008 // Task Switched 158*40889627SFrans Kaashoek #define CR0_ET 0x00000010 // Extension Type 159*40889627SFrans Kaashoek #define CR0_NE 0x00000020 // Numeric Errror 160*40889627SFrans Kaashoek #define CR0_WP 0x00010000 // Write Protect 161*40889627SFrans Kaashoek #define CR0_AM 0x00040000 // Alignment Mask 162*40889627SFrans Kaashoek #define CR0_NW 0x20000000 // Not Writethrough 163*40889627SFrans Kaashoek #define CR0_CD 0x40000000 // Cache Disable 164*40889627SFrans Kaashoek #define CR0_PG 0x80000000 // Paging 165*40889627SFrans Kaashoek 166*40889627SFrans Kaashoek 167cce27ba9Srsc // PAGEBREAK: 40 168dfcc5b99Srtm // Task state segment format 169b5f17007Srsc struct taskstate { 17029270816Srtm uint link; // Old ts selector 17111a9947fSrtm uint esp0; // Stack pointers and segment selectors 17229270816Srtm ushort ss0; // after an increase in privilege level 17329270816Srtm ushort padding1; 17429270816Srtm uint *esp1; 17529270816Srtm ushort ss1; 17629270816Srtm ushort padding2; 17729270816Srtm uint *esp2; 17829270816Srtm ushort ss2; 17929270816Srtm ushort padding3; 18029270816Srtm void *cr3; // Page directory base 18129270816Srtm uint *eip; // Saved state from last task switch 18229270816Srtm uint eflags; 18329270816Srtm uint eax; // More saved state (registers) 18429270816Srtm uint ecx; 18529270816Srtm uint edx; 18629270816Srtm uint ebx; 18729270816Srtm uint *esp; 18829270816Srtm uint *ebp; 18929270816Srtm uint esi; 19029270816Srtm uint edi; 19129270816Srtm ushort es; // Even more saved state (segment selectors) 19229270816Srtm ushort padding4; 19329270816Srtm ushort cs; 19429270816Srtm ushort padding5; 19529270816Srtm ushort ss; 19629270816Srtm ushort padding6; 19729270816Srtm ushort ds; 19829270816Srtm ushort padding7; 19929270816Srtm ushort fs; 20029270816Srtm ushort padding8; 20129270816Srtm ushort gs; 20229270816Srtm ushort padding9; 20329270816Srtm ushort ldt; 20429270816Srtm ushort padding10; 20529270816Srtm ushort t; // Trap on task switch 20629270816Srtm ushort iomb; // I/O map base address 20755e95b16Srtm }; 20855e95b16Srtm 209cce27ba9Srsc // PAGEBREAK: 12 21055e95b16Srtm // Gate descriptors for interrupts and traps 211b5f17007Srsc struct gatedesc { 212b5ee5165Srsc uint off_15_0 : 16; // low 16 bits of offset in segment 2130fe118f3Srsc uint cs : 16; // code segment selector 214b5ee5165Srsc uint args : 5; // # args, 0 for interrupt/trap gates 215b5ee5165Srsc uint rsv1 : 3; // reserved(should be zero I guess) 216b5ee5165Srsc uint type : 4; // type(STS_{TG,IG32,TG32}) 217b5ee5165Srsc uint s : 1; // must be 0 (system) 218b5ee5165Srsc uint dpl : 2; // descriptor(meaning new) privilege level 219b5ee5165Srsc uint p : 1; // Present 220b5ee5165Srsc uint off_31_16 : 16; // high bits of offset in segment 22155e95b16Srtm }; 22255e95b16Srtm 22355e95b16Srtm // Set up a normal interrupt/trap gate descriptor. 22455e95b16Srtm // - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate. 2255be0039cSrtm // interrupt gate clears FL_IF, trap gate leaves FL_IF alone 22655e95b16Srtm // - sel: Code segment selector for interrupt/trap handler 22755e95b16Srtm // - off: Offset in code segment for interrupt/trap handler 22855e95b16Srtm // - dpl: Descriptor Privilege Level - 22955e95b16Srtm // the privilege level required for software to invoke 23055e95b16Srtm // this interrupt/trap gate explicitly using an int instruction. 231ef2bd07aSrsc #define SETGATE(gate, istrap, sel, off, d) \ 23255e95b16Srtm { \ 23329270816Srtm (gate).off_15_0 = (uint) (off) & 0xffff; \ 2340fe118f3Srsc (gate).cs = (sel); \ 235ef2bd07aSrsc (gate).args = 0; \ 236ef2bd07aSrsc (gate).rsv1 = 0; \ 237ef2bd07aSrsc (gate).type = (istrap) ? STS_TG32 : STS_IG32; \ 238ef2bd07aSrsc (gate).s = 0; \ 239ef2bd07aSrsc (gate).dpl = (d); \ 240ef2bd07aSrsc (gate).p = 1; \ 24129270816Srtm (gate).off_31_16 = (uint) (off) >> 16; \ 24255e95b16Srtm } 24355e95b16Srtm 244