10cfc7290Srsc // This file contains definitions for the 20cfc7290Srsc // x86 memory management unit (MMU). 355e95b16Srtm 455e95b16Srtm // Eflags register 555e95b16Srtm #define FL_CF 0x00000001 // Carry Flag 655e95b16Srtm #define FL_PF 0x00000004 // Parity Flag 755e95b16Srtm #define FL_AF 0x00000010 // Auxiliary carry Flag 855e95b16Srtm #define FL_ZF 0x00000040 // Zero Flag 955e95b16Srtm #define FL_SF 0x00000080 // Sign Flag 1055e95b16Srtm #define FL_TF 0x00000100 // Trap Flag 113c821bf9Srsc #define FL_IF 0x00000200 // Interrupt Enable 1255e95b16Srtm #define FL_DF 0x00000400 // Direction Flag 1355e95b16Srtm #define FL_OF 0x00000800 // Overflow Flag 1455e95b16Srtm #define FL_IOPL_MASK 0x00003000 // I/O Privilege Level bitmask 1555e95b16Srtm #define FL_IOPL_0 0x00000000 // IOPL == 0 1655e95b16Srtm #define FL_IOPL_1 0x00001000 // IOPL == 1 1755e95b16Srtm #define FL_IOPL_2 0x00002000 // IOPL == 2 1855e95b16Srtm #define FL_IOPL_3 0x00003000 // IOPL == 3 1955e95b16Srtm #define FL_NT 0x00004000 // Nested Task 2055e95b16Srtm #define FL_RF 0x00010000 // Resume Flag 2155e95b16Srtm #define FL_VM 0x00020000 // Virtual 8086 mode 2255e95b16Srtm #define FL_AC 0x00040000 // Alignment Check 2355e95b16Srtm #define FL_VIF 0x00080000 // Virtual Interrupt Flag 2455e95b16Srtm #define FL_VIP 0x00100000 // Virtual Interrupt Pending 2555e95b16Srtm #define FL_ID 0x00200000 // ID flag 2655e95b16Srtm 27*7914ab72SAustin Clements // Control Register flags 28*7914ab72SAustin Clements #define CR0_PE 0x00000001 // Protection Enable 29*7914ab72SAustin Clements #define CR0_MP 0x00000002 // Monitor coProcessor 30*7914ab72SAustin Clements #define CR0_EM 0x00000004 // Emulation 31*7914ab72SAustin Clements #define CR0_TS 0x00000008 // Task Switched 32*7914ab72SAustin Clements #define CR0_ET 0x00000010 // Extension Type 33*7914ab72SAustin Clements #define CR0_NE 0x00000020 // Numeric Errror 34*7914ab72SAustin Clements #define CR0_WP 0x00010000 // Write Protect 35*7914ab72SAustin Clements #define CR0_AM 0x00040000 // Alignment Mask 36*7914ab72SAustin Clements #define CR0_NW 0x20000000 // Not Writethrough 37*7914ab72SAustin Clements #define CR0_CD 0x40000000 // Cache Disable 38*7914ab72SAustin Clements #define CR0_PG 0x80000000 // Paging 39*7914ab72SAustin Clements 40*7914ab72SAustin Clements //PAGEBREAK! 41dfcc5b99Srtm // Segment Descriptor 42b5f17007Srsc struct segdesc { 43b5ee5165Srsc uint lim_15_0 : 16; // Low bits of segment limit 44b5ee5165Srsc uint base_15_0 : 16; // Low bits of segment base address 45b5ee5165Srsc uint base_23_16 : 8; // Middle bits of segment base address 46b5ee5165Srsc uint type : 4; // Segment type (see STS_ constants) 47b5ee5165Srsc uint s : 1; // 0 = system, 1 = application 48b5ee5165Srsc uint dpl : 2; // Descriptor Privilege Level 49b5ee5165Srsc uint p : 1; // Present 50b5ee5165Srsc uint lim_19_16 : 4; // High bits of segment limit 51b5ee5165Srsc uint avl : 1; // Unused (available for software use) 52b5ee5165Srsc uint rsv1 : 1; // Reserved 53b5ee5165Srsc uint db : 1; // 0 = 16-bit segment, 1 = 32-bit segment 54b5ee5165Srsc uint g : 1; // Granularity: limit scaled by 4K when set 55b5ee5165Srsc uint base_31_24 : 8; // High bits of segment base address 5655e95b16Srtm }; 57dfcc5b99Srtm 5855e95b16Srtm // Normal segment 59b5f17007Srsc #define SEG(type, base, lim, dpl) (struct segdesc) \ 6048755214SRuss Cox { ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff, \ 6148755214SRuss Cox ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 6248755214SRuss Cox (uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 } 63b5f17007Srsc #define SEG16(type, base, lim, dpl) (struct segdesc) \ 6448755214SRuss Cox { (lim) & 0xffff, (uint)(base) & 0xffff, \ 6548755214SRuss Cox ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 6648755214SRuss Cox (uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 } 6755e95b16Srtm 68b6dc6187Srsc #define DPL_USER 0x3 // User DPL 69b6dc6187Srsc 7055e95b16Srtm // Application segment type bits 7155e95b16Srtm #define STA_X 0x8 // Executable segment 7255e95b16Srtm #define STA_E 0x4 // Expand down (non-executable segments) 7355e95b16Srtm #define STA_C 0x4 // Conforming code segment (executable only) 7455e95b16Srtm #define STA_W 0x2 // Writeable (non-executable segments) 7555e95b16Srtm #define STA_R 0x2 // Readable (executable segments) 7655e95b16Srtm #define STA_A 0x1 // Accessed 7755e95b16Srtm 7855e95b16Srtm // System segment type bits 7955e95b16Srtm #define STS_T16A 0x1 // Available 16-bit TSS 8055e95b16Srtm #define STS_LDT 0x2 // Local Descriptor Table 8155e95b16Srtm #define STS_T16B 0x3 // Busy 16-bit TSS 8255e95b16Srtm #define STS_CG16 0x4 // 16-bit Call Gate 8355e95b16Srtm #define STS_TG 0x5 // Task Gate / Coum Transmitions 8455e95b16Srtm #define STS_IG16 0x6 // 16-bit Interrupt Gate 8555e95b16Srtm #define STS_TG16 0x7 // 16-bit Trap Gate 8655e95b16Srtm #define STS_T32A 0x9 // Available 32-bit TSS 8755e95b16Srtm #define STS_T32B 0xB // Busy 32-bit TSS 8855e95b16Srtm #define STS_CG32 0xC // 32-bit Call Gate 8955e95b16Srtm #define STS_IG32 0xE // 32-bit Interrupt Gate 9055e95b16Srtm #define STS_TG32 0xF // 32-bit Trap Gate 9155e95b16Srtm 9240889627SFrans Kaashoek // A linear address 'la' has a three-part structure as follows: 9340889627SFrans Kaashoek // 9440889627SFrans Kaashoek // +--------10------+-------10-------+---------12----------+ 9540889627SFrans Kaashoek // | Page Directory | Page Table | Offset within Page | 9640889627SFrans Kaashoek // | Index | Index | | 9740889627SFrans Kaashoek // +----------------+----------------+---------------------+ 98c9959978SRobert Morris // \--- PDX(la) --/ \--- PTX(la) --/ 9940889627SFrans Kaashoek 10040889627SFrans Kaashoek // page directory index 10140889627SFrans Kaashoek #define PDX(la) ((((uint) (la)) >> PDXSHIFT) & 0x3FF) 10240889627SFrans Kaashoek 10340889627SFrans Kaashoek // page table index 10440889627SFrans Kaashoek #define PTX(la) ((((uint) (la)) >> PTXSHIFT) & 0x3FF) 10540889627SFrans Kaashoek 10640889627SFrans Kaashoek // construct linear address from indexes and offset 10740889627SFrans Kaashoek #define PGADDR(d, t, o) ((uint) ((d) << PDXSHIFT | (t) << PTXSHIFT | (o))) 10840889627SFrans Kaashoek 109c9959978SRobert Morris // turn a kernel linear address into a physical address. 110c9959978SRobert Morris // all of the kernel data structures have linear and 111c9959978SRobert Morris // physical addresses that are equal. 11240889627SFrans Kaashoek #define PADDR(a) ((uint) a) 11340889627SFrans Kaashoek 11440889627SFrans Kaashoek // Page directory and page table constants. 11540889627SFrans Kaashoek #define NPDENTRIES 1024 // page directory entries per page directory 11640889627SFrans Kaashoek #define NPTENTRIES 1024 // page table entries per page table 11740889627SFrans Kaashoek 11840889627SFrans Kaashoek #define PGSIZE 4096 // bytes mapped by a page 11940889627SFrans Kaashoek #define PGSHIFT 12 // log2(PGSIZE) 12040889627SFrans Kaashoek 12140889627SFrans Kaashoek #define PTXSHIFT 12 // offset of PTX in a linear address 12240889627SFrans Kaashoek #define PDXSHIFT 22 // offset of PDX in a linear address 12340889627SFrans Kaashoek 124eb18645fSRobert Morris #define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1)) 1257d7dc933SRobert Morris #define PGROUNDDOWN(a) ((char*)((((unsigned int)(a)) & ~(PGSIZE-1)))) 126eb18645fSRobert Morris 12740889627SFrans Kaashoek // Page table/directory entry flags. 12840889627SFrans Kaashoek #define PTE_P 0x001 // Present 12940889627SFrans Kaashoek #define PTE_W 0x002 // Writeable 13040889627SFrans Kaashoek #define PTE_U 0x004 // User 13140889627SFrans Kaashoek #define PTE_PWT 0x008 // Write-Through 13240889627SFrans Kaashoek #define PTE_PCD 0x010 // Cache-Disable 13340889627SFrans Kaashoek #define PTE_A 0x020 // Accessed 13440889627SFrans Kaashoek #define PTE_D 0x040 // Dirty 13540889627SFrans Kaashoek #define PTE_PS 0x080 // Page Size 13640889627SFrans Kaashoek #define PTE_MBZ 0x180 // Bits must be zero 13740889627SFrans Kaashoek 13840889627SFrans Kaashoek // Address in page table or page directory entry 13940889627SFrans Kaashoek #define PTE_ADDR(pte) ((uint) (pte) & ~0xFFF) 14040889627SFrans Kaashoek 14140889627SFrans Kaashoek typedef uint pte_t; 14240889627SFrans Kaashoek 143dfcc5b99Srtm // Task state segment format 144b5f17007Srsc struct taskstate { 14529270816Srtm uint link; // Old ts selector 14611a9947fSrtm uint esp0; // Stack pointers and segment selectors 14729270816Srtm ushort ss0; // after an increase in privilege level 14829270816Srtm ushort padding1; 14929270816Srtm uint *esp1; 15029270816Srtm ushort ss1; 15129270816Srtm ushort padding2; 15229270816Srtm uint *esp2; 15329270816Srtm ushort ss2; 15429270816Srtm ushort padding3; 15529270816Srtm void *cr3; // Page directory base 15629270816Srtm uint *eip; // Saved state from last task switch 15729270816Srtm uint eflags; 15829270816Srtm uint eax; // More saved state (registers) 15929270816Srtm uint ecx; 16029270816Srtm uint edx; 16129270816Srtm uint ebx; 16229270816Srtm uint *esp; 16329270816Srtm uint *ebp; 16429270816Srtm uint esi; 16529270816Srtm uint edi; 16629270816Srtm ushort es; // Even more saved state (segment selectors) 16729270816Srtm ushort padding4; 16829270816Srtm ushort cs; 16929270816Srtm ushort padding5; 17029270816Srtm ushort ss; 17129270816Srtm ushort padding6; 17229270816Srtm ushort ds; 17329270816Srtm ushort padding7; 17429270816Srtm ushort fs; 17529270816Srtm ushort padding8; 17629270816Srtm ushort gs; 17729270816Srtm ushort padding9; 17829270816Srtm ushort ldt; 17929270816Srtm ushort padding10; 18029270816Srtm ushort t; // Trap on task switch 18129270816Srtm ushort iomb; // I/O map base address 18255e95b16Srtm }; 18355e95b16Srtm 184cce27ba9Srsc // PAGEBREAK: 12 18555e95b16Srtm // Gate descriptors for interrupts and traps 186b5f17007Srsc struct gatedesc { 187b5ee5165Srsc uint off_15_0 : 16; // low 16 bits of offset in segment 1880fe118f3Srsc uint cs : 16; // code segment selector 189b5ee5165Srsc uint args : 5; // # args, 0 for interrupt/trap gates 190b5ee5165Srsc uint rsv1 : 3; // reserved(should be zero I guess) 191b5ee5165Srsc uint type : 4; // type(STS_{TG,IG32,TG32}) 192b5ee5165Srsc uint s : 1; // must be 0 (system) 193b5ee5165Srsc uint dpl : 2; // descriptor(meaning new) privilege level 194b5ee5165Srsc uint p : 1; // Present 195b5ee5165Srsc uint off_31_16 : 16; // high bits of offset in segment 19655e95b16Srtm }; 19755e95b16Srtm 19855e95b16Srtm // Set up a normal interrupt/trap gate descriptor. 19955e95b16Srtm // - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate. 2005be0039cSrtm // interrupt gate clears FL_IF, trap gate leaves FL_IF alone 20155e95b16Srtm // - sel: Code segment selector for interrupt/trap handler 20255e95b16Srtm // - off: Offset in code segment for interrupt/trap handler 20355e95b16Srtm // - dpl: Descriptor Privilege Level - 20455e95b16Srtm // the privilege level required for software to invoke 20555e95b16Srtm // this interrupt/trap gate explicitly using an int instruction. 206ef2bd07aSrsc #define SETGATE(gate, istrap, sel, off, d) \ 20755e95b16Srtm { \ 20829270816Srtm (gate).off_15_0 = (uint) (off) & 0xffff; \ 2090fe118f3Srsc (gate).cs = (sel); \ 210ef2bd07aSrsc (gate).args = 0; \ 211ef2bd07aSrsc (gate).rsv1 = 0; \ 212ef2bd07aSrsc (gate).type = (istrap) ? STS_TG32 : STS_IG32; \ 213ef2bd07aSrsc (gate).s = 0; \ 214ef2bd07aSrsc (gate).dpl = (d); \ 215ef2bd07aSrsc (gate).p = 1; \ 21629270816Srtm (gate).off_31_16 = (uint) (off) >> 16; \ 21755e95b16Srtm } 21855e95b16Srtm 219