xref: /xv6-public/mmu.h (revision dfcc5b99)
155e95b16Srtm /*
2*dfcc5b99Srtm  * This file contains definitions for the x86 memory management unit (MMU).
3*dfcc5b99Srtm  * from JOS.
455e95b16Srtm  */
555e95b16Srtm 
655e95b16Srtm // Eflags register
755e95b16Srtm #define FL_CF		0x00000001	// Carry Flag
855e95b16Srtm #define FL_PF		0x00000004	// Parity Flag
955e95b16Srtm #define FL_AF		0x00000010	// Auxiliary carry Flag
1055e95b16Srtm #define FL_ZF		0x00000040	// Zero Flag
1155e95b16Srtm #define FL_SF		0x00000080	// Sign Flag
1255e95b16Srtm #define FL_TF		0x00000100	// Trap Flag
1355e95b16Srtm #define FL_IF		0x00000200	// Interrupt Flag
1455e95b16Srtm #define FL_DF		0x00000400	// Direction Flag
1555e95b16Srtm #define FL_OF		0x00000800	// Overflow Flag
1655e95b16Srtm #define FL_IOPL_MASK	0x00003000	// I/O Privilege Level bitmask
1755e95b16Srtm #define FL_IOPL_0	0x00000000	//   IOPL == 0
1855e95b16Srtm #define FL_IOPL_1	0x00001000	//   IOPL == 1
1955e95b16Srtm #define FL_IOPL_2	0x00002000	//   IOPL == 2
2055e95b16Srtm #define FL_IOPL_3	0x00003000	//   IOPL == 3
2155e95b16Srtm #define FL_NT		0x00004000	// Nested Task
2255e95b16Srtm #define FL_RF		0x00010000	// Resume Flag
2355e95b16Srtm #define FL_VM		0x00020000	// Virtual 8086 mode
2455e95b16Srtm #define FL_AC		0x00040000	// Alignment Check
2555e95b16Srtm #define FL_VIF		0x00080000	// Virtual Interrupt Flag
2655e95b16Srtm #define FL_VIP		0x00100000	// Virtual Interrupt Pending
2755e95b16Srtm #define FL_ID		0x00200000	// ID flag
2855e95b16Srtm 
29*dfcc5b99Srtm // Segment Descriptor
30b5f17007Srsc struct segdesc {
31b5ee5165Srsc 	uint lim_15_0 : 16;  // Low bits of segment limit
32b5ee5165Srsc 	uint base_15_0 : 16; // Low bits of segment base address
33b5ee5165Srsc 	uint base_23_16 : 8; // Middle bits of segment base address
34b5ee5165Srsc 	uint type : 4;       // Segment type (see STS_ constants)
35b5ee5165Srsc 	uint s : 1;          // 0 = system, 1 = application
36b5ee5165Srsc 	uint dpl : 2;        // Descriptor Privilege Level
37b5ee5165Srsc 	uint p : 1;          // Present
38b5ee5165Srsc 	uint lim_19_16 : 4;  // High bits of segment limit
39b5ee5165Srsc 	uint avl : 1;        // Unused (available for software use)
40b5ee5165Srsc 	uint rsv1 : 1;       // Reserved
41b5ee5165Srsc 	uint db : 1;         // 0 = 16-bit segment, 1 = 32-bit segment
42b5ee5165Srsc 	uint g : 1;          // Granularity: limit scaled by 4K when set
43b5ee5165Srsc 	uint base_31_24 : 8; // High bits of segment base address
4455e95b16Srtm };
45*dfcc5b99Srtm 
4655e95b16Srtm // Null segment
47b5f17007Srsc #define SEG_NULL	(struct segdesc){ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
48*dfcc5b99Srtm 
4955e95b16Srtm // Normal segment
50b5f17007Srsc #define SEG(type, base, lim, dpl) (struct segdesc)			\
5155e95b16Srtm { ((lim) >> 12) & 0xffff, (base) & 0xffff, ((base) >> 16) & 0xff,	\
52b5ee5165Srsc     type, 1, dpl, 1, (uint) (lim) >> 28, 0, 0, 1, 1,		\
53b5ee5165Srsc     (uint) (base) >> 24 }
54*dfcc5b99Srtm 
55b5f17007Srsc #define SEG16(type, base, lim, dpl) (struct segdesc)			\
5655e95b16Srtm { (lim) & 0xffff, (base) & 0xffff, ((base) >> 16) & 0xff,		\
57b5ee5165Srsc     type, 1, dpl, 1, (uint) (lim) >> 16, 0, 0, 1, 0,		\
58b5ee5165Srsc     (uint) (base) >> 24 }
5955e95b16Srtm 
6055e95b16Srtm // Application segment type bits
6155e95b16Srtm #define STA_X		0x8	    // Executable segment
6255e95b16Srtm #define STA_E		0x4	    // Expand down (non-executable segments)
6355e95b16Srtm #define STA_C		0x4	    // Conforming code segment (executable only)
6455e95b16Srtm #define STA_W		0x2	    // Writeable (non-executable segments)
6555e95b16Srtm #define STA_R		0x2	    // Readable (executable segments)
6655e95b16Srtm #define STA_A		0x1	    // Accessed
6755e95b16Srtm 
6855e95b16Srtm // System segment type bits
6955e95b16Srtm #define STS_T16A	0x1	    // Available 16-bit TSS
7055e95b16Srtm #define STS_LDT		0x2	    // Local Descriptor Table
7155e95b16Srtm #define STS_T16B	0x3	    // Busy 16-bit TSS
7255e95b16Srtm #define STS_CG16	0x4	    // 16-bit Call Gate
7355e95b16Srtm #define STS_TG		0x5	    // Task Gate / Coum Transmitions
7455e95b16Srtm #define STS_IG16	0x6	    // 16-bit Interrupt Gate
7555e95b16Srtm #define STS_TG16	0x7	    // 16-bit Trap Gate
7655e95b16Srtm #define STS_T32A	0x9	    // Available 32-bit TSS
7755e95b16Srtm #define STS_T32B	0xB	    // Busy 32-bit TSS
7855e95b16Srtm #define STS_CG32	0xC	    // 32-bit Call Gate
7955e95b16Srtm #define STS_IG32	0xE	    // 32-bit Interrupt Gate
8055e95b16Srtm #define STS_TG32	0xF	    // 32-bit Trap Gate
8155e95b16Srtm 
82*dfcc5b99Srtm // Task state segment format
83b5f17007Srsc struct taskstate {
8429270816Srtm 	uint link;	// Old ts selector
8511a9947fSrtm 	uint esp0;	// Stack pointers and segment selectors
8629270816Srtm 	ushort ss0;	//   after an increase in privilege level
8729270816Srtm 	ushort padding1;
8829270816Srtm 	uint * esp1;
8929270816Srtm 	ushort ss1;
9029270816Srtm 	ushort padding2;
9129270816Srtm 	uint * esp2;
9229270816Srtm 	ushort ss2;
9329270816Srtm 	ushort padding3;
9429270816Srtm 	void * cr3;	// Page directory base
9529270816Srtm 	uint * eip;	// Saved state from last task switch
9629270816Srtm 	uint eflags;
9729270816Srtm 	uint eax;	// More saved state (registers)
9829270816Srtm 	uint ecx;
9929270816Srtm 	uint edx;
10029270816Srtm 	uint ebx;
10129270816Srtm 	uint * esp;
10229270816Srtm 	uint * ebp;
10329270816Srtm 	uint esi;
10429270816Srtm 	uint edi;
10529270816Srtm 	ushort es;		// Even more saved state (segment selectors)
10629270816Srtm 	ushort padding4;
10729270816Srtm 	ushort cs;
10829270816Srtm 	ushort padding5;
10929270816Srtm 	ushort ss;
11029270816Srtm 	ushort padding6;
11129270816Srtm 	ushort ds;
11229270816Srtm 	ushort padding7;
11329270816Srtm 	ushort fs;
11429270816Srtm 	ushort padding8;
11529270816Srtm 	ushort gs;
11629270816Srtm 	ushort padding9;
11729270816Srtm 	ushort ldt;
11829270816Srtm 	ushort padding10;
11929270816Srtm 	ushort t;		// Trap on task switch
12029270816Srtm 	ushort iomb;	// I/O map base address
12155e95b16Srtm };
12255e95b16Srtm 
12355e95b16Srtm // Gate descriptors for interrupts and traps
124b5f17007Srsc struct gatedesc {
125b5ee5165Srsc 	uint off_15_0 : 16;   // low 16 bits of offset in segment
126b5ee5165Srsc 	uint ss : 16;         // segment selector
127b5ee5165Srsc 	uint args : 5;        // # args, 0 for interrupt/trap gates
128b5ee5165Srsc 	uint rsv1 : 3;        // reserved(should be zero I guess)
129b5ee5165Srsc 	uint type : 4;        // type(STS_{TG,IG32,TG32})
130b5ee5165Srsc 	uint s : 1;           // must be 0 (system)
131b5ee5165Srsc 	uint dpl : 2;         // descriptor(meaning new) privilege level
132b5ee5165Srsc 	uint p : 1;           // Present
133b5ee5165Srsc 	uint off_31_16 : 16;  // high bits of offset in segment
13455e95b16Srtm };
13555e95b16Srtm 
13655e95b16Srtm // Set up a normal interrupt/trap gate descriptor.
13755e95b16Srtm // - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate.
1385be0039cSrtm //   interrupt gate clears FL_IF, trap gate leaves FL_IF alone
13955e95b16Srtm // - sel: Code segment selector for interrupt/trap handler
14055e95b16Srtm // - off: Offset in code segment for interrupt/trap handler
14155e95b16Srtm // - dpl: Descriptor Privilege Level -
14255e95b16Srtm //	  the privilege level required for software to invoke
14355e95b16Srtm //	  this interrupt/trap gate explicitly using an int instruction.
144ef2bd07aSrsc #define SETGATE(gate, istrap, sel, off, d)			\
14555e95b16Srtm {								\
14629270816Srtm 	(gate).off_15_0 = (uint) (off) & 0xffff;		\
147ef2bd07aSrsc 	(gate).ss = (sel);					\
148ef2bd07aSrsc 	(gate).args = 0;					\
149ef2bd07aSrsc 	(gate).rsv1 = 0;					\
150ef2bd07aSrsc 	(gate).type = (istrap) ? STS_TG32 : STS_IG32;	\
151ef2bd07aSrsc 	(gate).s = 0;					\
152ef2bd07aSrsc 	(gate).dpl = (d);					\
153ef2bd07aSrsc 	(gate).p = 1;					\
15429270816Srtm 	(gate).off_31_16 = (uint) (off) >> 16;		\
15555e95b16Srtm }
15655e95b16Srtm 
157