1 // This file contains definitions for the 2 // x86 memory management unit (MMU). 3 4 // Eflags register 5 #define FL_CF 0x00000001 // Carry Flag 6 #define FL_PF 0x00000004 // Parity Flag 7 #define FL_AF 0x00000010 // Auxiliary carry Flag 8 #define FL_ZF 0x00000040 // Zero Flag 9 #define FL_SF 0x00000080 // Sign Flag 10 #define FL_TF 0x00000100 // Trap Flag 11 #define FL_IF 0x00000200 // Interrupt Enable 12 #define FL_DF 0x00000400 // Direction Flag 13 #define FL_OF 0x00000800 // Overflow Flag 14 #define FL_IOPL_MASK 0x00003000 // I/O Privilege Level bitmask 15 #define FL_IOPL_0 0x00000000 // IOPL == 0 16 #define FL_IOPL_1 0x00001000 // IOPL == 1 17 #define FL_IOPL_2 0x00002000 // IOPL == 2 18 #define FL_IOPL_3 0x00003000 // IOPL == 3 19 #define FL_NT 0x00004000 // Nested Task 20 #define FL_RF 0x00010000 // Resume Flag 21 #define FL_VM 0x00020000 // Virtual 8086 mode 22 #define FL_AC 0x00040000 // Alignment Check 23 #define FL_VIF 0x00080000 // Virtual Interrupt Flag 24 #define FL_VIP 0x00100000 // Virtual Interrupt Pending 25 #define FL_ID 0x00200000 // ID flag 26 27 // Control Register flags 28 #define CR0_PE 0x00000001 // Protection Enable 29 #define CR0_MP 0x00000002 // Monitor coProcessor 30 #define CR0_EM 0x00000004 // Emulation 31 #define CR0_TS 0x00000008 // Task Switched 32 #define CR0_ET 0x00000010 // Extension Type 33 #define CR0_NE 0x00000020 // Numeric Errror 34 #define CR0_WP 0x00010000 // Write Protect 35 #define CR0_AM 0x00040000 // Alignment Mask 36 #define CR0_NW 0x20000000 // Not Writethrough 37 #define CR0_CD 0x40000000 // Cache Disable 38 #define CR0_PG 0x80000000 // Paging 39 40 //PAGEBREAK! 41 // Segment Descriptor 42 struct segdesc { 43 uint lim_15_0 : 16; // Low bits of segment limit 44 uint base_15_0 : 16; // Low bits of segment base address 45 uint base_23_16 : 8; // Middle bits of segment base address 46 uint type : 4; // Segment type (see STS_ constants) 47 uint s : 1; // 0 = system, 1 = application 48 uint dpl : 2; // Descriptor Privilege Level 49 uint p : 1; // Present 50 uint lim_19_16 : 4; // High bits of segment limit 51 uint avl : 1; // Unused (available for software use) 52 uint rsv1 : 1; // Reserved 53 uint db : 1; // 0 = 16-bit segment, 1 = 32-bit segment 54 uint g : 1; // Granularity: limit scaled by 4K when set 55 uint base_31_24 : 8; // High bits of segment base address 56 }; 57 58 // Normal segment 59 #define SEG(type, base, lim, dpl) (struct segdesc) \ 60 { ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff, \ 61 ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 62 (uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 } 63 #define SEG16(type, base, lim, dpl) (struct segdesc) \ 64 { (lim) & 0xffff, (uint)(base) & 0xffff, \ 65 ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 66 (uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 } 67 68 #define DPL_USER 0x3 // User DPL 69 70 // Application segment type bits 71 #define STA_X 0x8 // Executable segment 72 #define STA_E 0x4 // Expand down (non-executable segments) 73 #define STA_C 0x4 // Conforming code segment (executable only) 74 #define STA_W 0x2 // Writeable (non-executable segments) 75 #define STA_R 0x2 // Readable (executable segments) 76 #define STA_A 0x1 // Accessed 77 78 // System segment type bits 79 #define STS_T16A 0x1 // Available 16-bit TSS 80 #define STS_LDT 0x2 // Local Descriptor Table 81 #define STS_T16B 0x3 // Busy 16-bit TSS 82 #define STS_CG16 0x4 // 16-bit Call Gate 83 #define STS_TG 0x5 // Task Gate / Coum Transmitions 84 #define STS_IG16 0x6 // 16-bit Interrupt Gate 85 #define STS_TG16 0x7 // 16-bit Trap Gate 86 #define STS_T32A 0x9 // Available 32-bit TSS 87 #define STS_T32B 0xB // Busy 32-bit TSS 88 #define STS_CG32 0xC // 32-bit Call Gate 89 #define STS_IG32 0xE // 32-bit Interrupt Gate 90 #define STS_TG32 0xF // 32-bit Trap Gate 91 92 // A linear address 'la' has a three-part structure as follows: 93 // 94 // +--------10------+-------10-------+---------12----------+ 95 // | Page Directory | Page Table | Offset within Page | 96 // | Index | Index | | 97 // +----------------+----------------+---------------------+ 98 // \--- PDX(la) --/ \--- PTX(la) --/ 99 100 // page directory index 101 #define PDX(la) (((uint)(la) >> PDXSHIFT) & 0x3FF) 102 103 // page table index 104 #define PTX(la) (((uint)(la) >> PTXSHIFT) & 0x3FF) 105 106 // construct linear address from indexes and offset 107 #define PGADDR(d, t, o) ((uint)((d) << PDXSHIFT | (t) << PTXSHIFT | (o))) 108 109 // turn a kernel linear address into a physical address. 110 // all of the kernel data structures have linear and 111 // physical addresses that are equal. 112 #define PADDR(a) ((uint)(a)) 113 114 // Page directory and page table constants. 115 #define NPDENTRIES 1024 // page directory entries per page directory 116 #define NPTENTRIES 1024 // page table entries per page table 117 118 #define PGSIZE 4096 // bytes mapped by a page 119 #define PGSHIFT 12 // log2(PGSIZE) 120 121 #define PTXSHIFT 12 // offset of PTX in a linear address 122 #define PDXSHIFT 22 // offset of PDX in a linear address 123 124 #define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1)) 125 #define PGROUNDDOWN(a) ((char*)((((unsigned int)(a)) & ~(PGSIZE-1)))) 126 127 // Page table/directory entry flags. 128 #define PTE_P 0x001 // Present 129 #define PTE_W 0x002 // Writeable 130 #define PTE_U 0x004 // User 131 #define PTE_PWT 0x008 // Write-Through 132 #define PTE_PCD 0x010 // Cache-Disable 133 #define PTE_A 0x020 // Accessed 134 #define PTE_D 0x040 // Dirty 135 #define PTE_PS 0x080 // Page Size 136 #define PTE_MBZ 0x180 // Bits must be zero 137 138 // Address in page table or page directory entry 139 #define PTE_ADDR(pte) ((uint)(pte) & ~0xFFF) 140 141 typedef uint pte_t; 142 143 // Task state segment format 144 struct taskstate { 145 uint link; // Old ts selector 146 uint esp0; // Stack pointers and segment selectors 147 ushort ss0; // after an increase in privilege level 148 ushort padding1; 149 uint *esp1; 150 ushort ss1; 151 ushort padding2; 152 uint *esp2; 153 ushort ss2; 154 ushort padding3; 155 void *cr3; // Page directory base 156 uint *eip; // Saved state from last task switch 157 uint eflags; 158 uint eax; // More saved state (registers) 159 uint ecx; 160 uint edx; 161 uint ebx; 162 uint *esp; 163 uint *ebp; 164 uint esi; 165 uint edi; 166 ushort es; // Even more saved state (segment selectors) 167 ushort padding4; 168 ushort cs; 169 ushort padding5; 170 ushort ss; 171 ushort padding6; 172 ushort ds; 173 ushort padding7; 174 ushort fs; 175 ushort padding8; 176 ushort gs; 177 ushort padding9; 178 ushort ldt; 179 ushort padding10; 180 ushort t; // Trap on task switch 181 ushort iomb; // I/O map base address 182 }; 183 184 // PAGEBREAK: 12 185 // Gate descriptors for interrupts and traps 186 struct gatedesc { 187 uint off_15_0 : 16; // low 16 bits of offset in segment 188 uint cs : 16; // code segment selector 189 uint args : 5; // # args, 0 for interrupt/trap gates 190 uint rsv1 : 3; // reserved(should be zero I guess) 191 uint type : 4; // type(STS_{TG,IG32,TG32}) 192 uint s : 1; // must be 0 (system) 193 uint dpl : 2; // descriptor(meaning new) privilege level 194 uint p : 1; // Present 195 uint off_31_16 : 16; // high bits of offset in segment 196 }; 197 198 // Set up a normal interrupt/trap gate descriptor. 199 // - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate. 200 // interrupt gate clears FL_IF, trap gate leaves FL_IF alone 201 // - sel: Code segment selector for interrupt/trap handler 202 // - off: Offset in code segment for interrupt/trap handler 203 // - dpl: Descriptor Privilege Level - 204 // the privilege level required for software to invoke 205 // this interrupt/trap gate explicitly using an int instruction. 206 #define SETGATE(gate, istrap, sel, off, d) \ 207 { \ 208 (gate).off_15_0 = (uint)(off) & 0xffff; \ 209 (gate).cs = (sel); \ 210 (gate).args = 0; \ 211 (gate).rsv1 = 0; \ 212 (gate).type = (istrap) ? STS_TG32 : STS_IG32; \ 213 (gate).s = 0; \ 214 (gate).dpl = (d); \ 215 (gate).p = 1; \ 216 (gate).off_31_16 = (uint)(off) >> 16; \ 217 } 218 219