1 // This file contains definitions for the 2 // x86 memory management unit (MMU). 3 4 // Eflags register 5 #define FL_CF 0x00000001 // Carry Flag 6 #define FL_PF 0x00000004 // Parity Flag 7 #define FL_AF 0x00000010 // Auxiliary carry Flag 8 #define FL_ZF 0x00000040 // Zero Flag 9 #define FL_SF 0x00000080 // Sign Flag 10 #define FL_TF 0x00000100 // Trap Flag 11 #define FL_IF 0x00000200 // Interrupt Enable 12 #define FL_DF 0x00000400 // Direction Flag 13 #define FL_OF 0x00000800 // Overflow Flag 14 #define FL_IOPL_MASK 0x00003000 // I/O Privilege Level bitmask 15 #define FL_IOPL_0 0x00000000 // IOPL == 0 16 #define FL_IOPL_1 0x00001000 // IOPL == 1 17 #define FL_IOPL_2 0x00002000 // IOPL == 2 18 #define FL_IOPL_3 0x00003000 // IOPL == 3 19 #define FL_NT 0x00004000 // Nested Task 20 #define FL_RF 0x00010000 // Resume Flag 21 #define FL_VM 0x00020000 // Virtual 8086 mode 22 #define FL_AC 0x00040000 // Alignment Check 23 #define FL_VIF 0x00080000 // Virtual Interrupt Flag 24 #define FL_VIP 0x00100000 // Virtual Interrupt Pending 25 #define FL_ID 0x00200000 // ID flag 26 27 // Segment Descriptor 28 struct segdesc { 29 uint lim_15_0 : 16; // Low bits of segment limit 30 uint base_15_0 : 16; // Low bits of segment base address 31 uint base_23_16 : 8; // Middle bits of segment base address 32 uint type : 4; // Segment type (see STS_ constants) 33 uint s : 1; // 0 = system, 1 = application 34 uint dpl : 2; // Descriptor Privilege Level 35 uint p : 1; // Present 36 uint lim_19_16 : 4; // High bits of segment limit 37 uint avl : 1; // Unused (available for software use) 38 uint rsv1 : 1; // Reserved 39 uint db : 1; // 0 = 16-bit segment, 1 = 32-bit segment 40 uint g : 1; // Granularity: limit scaled by 4K when set 41 uint base_31_24 : 8; // High bits of segment base address 42 }; 43 44 // Normal segment 45 #define SEG(type, base, lim, dpl) (struct segdesc) \ 46 { ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff, \ 47 ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 48 (uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 } 49 50 #define SEG16(type, base, lim, dpl) (struct segdesc) \ 51 { (lim) & 0xffff, (uint)(base) & 0xffff, \ 52 ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 53 (uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 } 54 55 #define DPL_USER 0x3 // User DPL 56 57 // Application segment type bits 58 #define STA_X 0x8 // Executable segment 59 #define STA_E 0x4 // Expand down (non-executable segments) 60 #define STA_C 0x4 // Conforming code segment (executable only) 61 #define STA_W 0x2 // Writeable (non-executable segments) 62 #define STA_R 0x2 // Readable (executable segments) 63 #define STA_A 0x1 // Accessed 64 65 // 66 67 // System segment type bits 68 #define STS_T16A 0x1 // Available 16-bit TSS 69 #define STS_LDT 0x2 // Local Descriptor Table 70 #define STS_T16B 0x3 // Busy 16-bit TSS 71 #define STS_CG16 0x4 // 16-bit Call Gate 72 #define STS_TG 0x5 // Task Gate / Coum Transmitions 73 #define STS_IG16 0x6 // 16-bit Interrupt Gate 74 #define STS_TG16 0x7 // 16-bit Trap Gate 75 #define STS_T32A 0x9 // Available 32-bit TSS 76 #define STS_T32B 0xB // Busy 32-bit TSS 77 #define STS_CG32 0xC // 32-bit Call Gate 78 #define STS_IG32 0xE // 32-bit Interrupt Gate 79 #define STS_TG32 0xF // 32-bit Trap Gate 80 81 82 // A linear address 'la' has a three-part structure as follows: 83 // 84 // +--------10------+-------10-------+---------12----------+ 85 // | Page Directory | Page Table | Offset within Page | 86 // | Index | Index | | 87 // +----------------+----------------+---------------------+ 88 // \--- PDX(la) --/ \--- PTX(la) --/ 89 90 // page directory index 91 #define PDX(la) ((((uint) (la)) >> PDXSHIFT) & 0x3FF) 92 93 // page table index 94 #define PTX(la) ((((uint) (la)) >> PTXSHIFT) & 0x3FF) 95 96 // construct linear address from indexes and offset 97 #define PGADDR(d, t, o) ((uint) ((d) << PDXSHIFT | (t) << PTXSHIFT | (o))) 98 99 // turn a kernel linear address into a physical address. 100 // all of the kernel data structures have linear and 101 // physical addresses that are equal. 102 #define PADDR(a) ((uint) a) 103 104 // Page directory and page table constants. 105 #define NPDENTRIES 1024 // page directory entries per page directory 106 #define NPTENTRIES 1024 // page table entries per page table 107 108 #define PGSIZE 4096 // bytes mapped by a page 109 #define PGSHIFT 12 // log2(PGSIZE) 110 111 #define PTXSHIFT 12 // offset of PTX in a linear address 112 #define PDXSHIFT 22 // offset of PDX in a linear address 113 114 #define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1)) 115 #define PGROUNDDOWN(a) ((char*)((((unsigned int)(a)) & ~(PGSIZE-1)))) 116 117 // Page table/directory entry flags. 118 #define PTE_P 0x001 // Present 119 #define PTE_W 0x002 // Writeable 120 #define PTE_U 0x004 // User 121 #define PTE_PWT 0x008 // Write-Through 122 #define PTE_PCD 0x010 // Cache-Disable 123 #define PTE_A 0x020 // Accessed 124 #define PTE_D 0x040 // Dirty 125 #define PTE_PS 0x080 // Page Size 126 #define PTE_MBZ 0x180 // Bits must be zero 127 128 // Address in page table or page directory entry 129 #define PTE_ADDR(pte) ((uint) (pte) & ~0xFFF) 130 131 typedef uint pte_t; 132 133 // Control Register flags 134 #define CR0_PE 0x00000001 // Protection Enable 135 #define CR0_MP 0x00000002 // Monitor coProcessor 136 #define CR0_EM 0x00000004 // Emulation 137 #define CR0_TS 0x00000008 // Task Switched 138 #define CR0_ET 0x00000010 // Extension Type 139 #define CR0_NE 0x00000020 // Numeric Errror 140 #define CR0_WP 0x00010000 // Write Protect 141 #define CR0_AM 0x00040000 // Alignment Mask 142 #define CR0_NW 0x20000000 // Not Writethrough 143 #define CR0_CD 0x40000000 // Cache Disable 144 #define CR0_PG 0x80000000 // Paging 145 146 147 // PAGEBREAK: 40 148 // Task state segment format 149 struct taskstate { 150 uint link; // Old ts selector 151 uint esp0; // Stack pointers and segment selectors 152 ushort ss0; // after an increase in privilege level 153 ushort padding1; 154 uint *esp1; 155 ushort ss1; 156 ushort padding2; 157 uint *esp2; 158 ushort ss2; 159 ushort padding3; 160 void *cr3; // Page directory base 161 uint *eip; // Saved state from last task switch 162 uint eflags; 163 uint eax; // More saved state (registers) 164 uint ecx; 165 uint edx; 166 uint ebx; 167 uint *esp; 168 uint *ebp; 169 uint esi; 170 uint edi; 171 ushort es; // Even more saved state (segment selectors) 172 ushort padding4; 173 ushort cs; 174 ushort padding5; 175 ushort ss; 176 ushort padding6; 177 ushort ds; 178 ushort padding7; 179 ushort fs; 180 ushort padding8; 181 ushort gs; 182 ushort padding9; 183 ushort ldt; 184 ushort padding10; 185 ushort t; // Trap on task switch 186 ushort iomb; // I/O map base address 187 }; 188 189 // PAGEBREAK: 12 190 // Gate descriptors for interrupts and traps 191 struct gatedesc { 192 uint off_15_0 : 16; // low 16 bits of offset in segment 193 uint cs : 16; // code segment selector 194 uint args : 5; // # args, 0 for interrupt/trap gates 195 uint rsv1 : 3; // reserved(should be zero I guess) 196 uint type : 4; // type(STS_{TG,IG32,TG32}) 197 uint s : 1; // must be 0 (system) 198 uint dpl : 2; // descriptor(meaning new) privilege level 199 uint p : 1; // Present 200 uint off_31_16 : 16; // high bits of offset in segment 201 }; 202 203 // Set up a normal interrupt/trap gate descriptor. 204 // - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate. 205 // interrupt gate clears FL_IF, trap gate leaves FL_IF alone 206 // - sel: Code segment selector for interrupt/trap handler 207 // - off: Offset in code segment for interrupt/trap handler 208 // - dpl: Descriptor Privilege Level - 209 // the privilege level required for software to invoke 210 // this interrupt/trap gate explicitly using an int instruction. 211 #define SETGATE(gate, istrap, sel, off, d) \ 212 { \ 213 (gate).off_15_0 = (uint) (off) & 0xffff; \ 214 (gate).cs = (sel); \ 215 (gate).args = 0; \ 216 (gate).rsv1 = 0; \ 217 (gate).type = (istrap) ? STS_TG32 : STS_IG32; \ 218 (gate).s = 0; \ 219 (gate).dpl = (d); \ 220 (gate).p = 1; \ 221 (gate).off_31_16 = (uint) (off) >> 16; \ 222 } 223 224