1 // This file contains definitions for the 2 // x86 memory management unit (MMU). 3 4 // Eflags register 5 #define FL_CF 0x00000001 // Carry Flag 6 #define FL_PF 0x00000004 // Parity Flag 7 #define FL_AF 0x00000010 // Auxiliary carry Flag 8 #define FL_ZF 0x00000040 // Zero Flag 9 #define FL_SF 0x00000080 // Sign Flag 10 #define FL_TF 0x00000100 // Trap Flag 11 #define FL_IF 0x00000200 // Interrupt Enable 12 #define FL_DF 0x00000400 // Direction Flag 13 #define FL_OF 0x00000800 // Overflow Flag 14 #define FL_IOPL_MASK 0x00003000 // I/O Privilege Level bitmask 15 #define FL_IOPL_0 0x00000000 // IOPL == 0 16 #define FL_IOPL_1 0x00001000 // IOPL == 1 17 #define FL_IOPL_2 0x00002000 // IOPL == 2 18 #define FL_IOPL_3 0x00003000 // IOPL == 3 19 #define FL_NT 0x00004000 // Nested Task 20 #define FL_RF 0x00010000 // Resume Flag 21 #define FL_VM 0x00020000 // Virtual 8086 mode 22 #define FL_AC 0x00040000 // Alignment Check 23 #define FL_VIF 0x00080000 // Virtual Interrupt Flag 24 #define FL_VIP 0x00100000 // Virtual Interrupt Pending 25 #define FL_ID 0x00200000 // ID flag 26 27 // Control Register flags 28 #define CR0_PE 0x00000001 // Protection Enable 29 #define CR0_MP 0x00000002 // Monitor coProcessor 30 #define CR0_EM 0x00000004 // Emulation 31 #define CR0_TS 0x00000008 // Task Switched 32 #define CR0_ET 0x00000010 // Extension Type 33 #define CR0_NE 0x00000020 // Numeric Errror 34 #define CR0_WP 0x00010000 // Write Protect 35 #define CR0_AM 0x00040000 // Alignment Mask 36 #define CR0_NW 0x20000000 // Not Writethrough 37 #define CR0_CD 0x40000000 // Cache Disable 38 #define CR0_PG 0x80000000 // Paging 39 40 #define CR4_PSE 0x00000010 // Page size extension 41 42 #define SEG_KCODE 1 // kernel code 43 #define SEG_KDATA 2 // kernel data+stack 44 #define SEG_KCPU 3 // kernel per-cpu data 45 #define SEG_UCODE 4 // user code 46 #define SEG_UDATA 5 // user data+stack 47 #define SEG_TSS 6 // this process's task state 48 49 //PAGEBREAK! 50 #ifndef __ASSEMBLER__ 51 // Segment Descriptor 52 struct segdesc { 53 uint lim_15_0 : 16; // Low bits of segment limit 54 uint base_15_0 : 16; // Low bits of segment base address 55 uint base_23_16 : 8; // Middle bits of segment base address 56 uint type : 4; // Segment type (see STS_ constants) 57 uint s : 1; // 0 = system, 1 = application 58 uint dpl : 2; // Descriptor Privilege Level 59 uint p : 1; // Present 60 uint lim_19_16 : 4; // High bits of segment limit 61 uint avl : 1; // Unused (available for software use) 62 uint rsv1 : 1; // Reserved 63 uint db : 1; // 0 = 16-bit segment, 1 = 32-bit segment 64 uint g : 1; // Granularity: limit scaled by 4K when set 65 uint base_31_24 : 8; // High bits of segment base address 66 }; 67 68 // Normal segment 69 #define SEG(type, base, lim, dpl) (struct segdesc) \ 70 { ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff, \ 71 ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 72 (uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 } 73 #define SEG16(type, base, lim, dpl) (struct segdesc) \ 74 { (lim) & 0xffff, (uint)(base) & 0xffff, \ 75 ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \ 76 (uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 } 77 #endif 78 79 #define DPL_USER 0x3 // User DPL 80 81 // Application segment type bits 82 #define STA_X 0x8 // Executable segment 83 #define STA_E 0x4 // Expand down (non-executable segments) 84 #define STA_C 0x4 // Conforming code segment (executable only) 85 #define STA_W 0x2 // Writeable (non-executable segments) 86 #define STA_R 0x2 // Readable (executable segments) 87 #define STA_A 0x1 // Accessed 88 89 // System segment type bits 90 #define STS_T16A 0x1 // Available 16-bit TSS 91 #define STS_LDT 0x2 // Local Descriptor Table 92 #define STS_T16B 0x3 // Busy 16-bit TSS 93 #define STS_CG16 0x4 // 16-bit Call Gate 94 #define STS_TG 0x5 // Task Gate / Coum Transmitions 95 #define STS_IG16 0x6 // 16-bit Interrupt Gate 96 #define STS_TG16 0x7 // 16-bit Trap Gate 97 #define STS_T32A 0x9 // Available 32-bit TSS 98 #define STS_T32B 0xB // Busy 32-bit TSS 99 #define STS_CG32 0xC // 32-bit Call Gate 100 #define STS_IG32 0xE // 32-bit Interrupt Gate 101 #define STS_TG32 0xF // 32-bit Trap Gate 102 103 // A linear address 'la' has a three-part structure as follows: 104 // 105 // +--------10------+-------10-------+---------12----------+ 106 // | Page Directory | Page Table | Offset within Page | 107 // | Index | Index | | 108 // +----------------+----------------+---------------------+ 109 // \--- PDX(la) --/ \--- PTX(la) --/ 110 111 // page directory index 112 #define PDX(la) (((uint)(la) >> PDXSHIFT) & 0x3FF) 113 114 // page table index 115 #define PTX(la) (((uint)(la) >> PTXSHIFT) & 0x3FF) 116 117 // construct linear address from indexes and offset 118 #define PGADDR(d, t, o) ((uint)((d) << PDXSHIFT | (t) << PTXSHIFT | (o))) 119 120 // Page directory and page table constants. 121 #define NPDENTRIES 1024 // page directory entries per page directory 122 #define NPTENTRIES 1024 // page table entries per page table 123 124 #define PTXSHIFT 12 // offset of PTX in a linear address 125 #define PDXSHIFT 22 // offset of PDX in a linear address 126 127 #define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1)) 128 #define PGROUNDDOWN(a) ((char*)((((unsigned int)(a)) & ~(PGSIZE-1)))) 129 130 // Page table/directory entry flags. 131 #define PTE_P 0x001 // Present 132 #define PTE_W 0x002 // Writeable 133 #define PTE_U 0x004 // User 134 #define PTE_PWT 0x008 // Write-Through 135 #define PTE_PCD 0x010 // Cache-Disable 136 #define PTE_A 0x020 // Accessed 137 #define PTE_D 0x040 // Dirty 138 #define PTE_PS 0x080 // Page Size 139 #define PTE_MBZ 0x180 // Bits must be zero 140 141 // Address in page table or page directory entry 142 #define PTE_ADDR(pte) ((uint)(pte) & ~0xFFF) 143 144 #ifndef __ASSEMBLER__ 145 typedef uint pte_t; 146 147 // Task state segment format 148 struct taskstate { 149 uint link; // Old ts selector 150 uint esp0; // Stack pointers and segment selectors 151 ushort ss0; // after an increase in privilege level 152 ushort padding1; 153 uint *esp1; 154 ushort ss1; 155 ushort padding2; 156 uint *esp2; 157 ushort ss2; 158 ushort padding3; 159 void *cr3; // Page directory base 160 uint *eip; // Saved state from last task switch 161 uint eflags; 162 uint eax; // More saved state (registers) 163 uint ecx; 164 uint edx; 165 uint ebx; 166 uint *esp; 167 uint *ebp; 168 uint esi; 169 uint edi; 170 ushort es; // Even more saved state (segment selectors) 171 ushort padding4; 172 ushort cs; 173 ushort padding5; 174 ushort ss; 175 ushort padding6; 176 ushort ds; 177 ushort padding7; 178 ushort fs; 179 ushort padding8; 180 ushort gs; 181 ushort padding9; 182 ushort ldt; 183 ushort padding10; 184 ushort t; // Trap on task switch 185 ushort iomb; // I/O map base address 186 }; 187 188 // PAGEBREAK: 12 189 // Gate descriptors for interrupts and traps 190 struct gatedesc { 191 uint off_15_0 : 16; // low 16 bits of offset in segment 192 uint cs : 16; // code segment selector 193 uint args : 5; // # args, 0 for interrupt/trap gates 194 uint rsv1 : 3; // reserved(should be zero I guess) 195 uint type : 4; // type(STS_{TG,IG32,TG32}) 196 uint s : 1; // must be 0 (system) 197 uint dpl : 2; // descriptor(meaning new) privilege level 198 uint p : 1; // Present 199 uint off_31_16 : 16; // high bits of offset in segment 200 }; 201 202 // Set up a normal interrupt/trap gate descriptor. 203 // - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate. 204 // interrupt gate clears FL_IF, trap gate leaves FL_IF alone 205 // - sel: Code segment selector for interrupt/trap handler 206 // - off: Offset in code segment for interrupt/trap handler 207 // - dpl: Descriptor Privilege Level - 208 // the privilege level required for software to invoke 209 // this interrupt/trap gate explicitly using an int instruction. 210 #define SETGATE(gate, istrap, sel, off, d) \ 211 { \ 212 (gate).off_15_0 = (uint)(off) & 0xffff; \ 213 (gate).cs = (sel); \ 214 (gate).args = 0; \ 215 (gate).rsv1 = 0; \ 216 (gate).type = (istrap) ? STS_TG32 : STS_IG32; \ 217 (gate).s = 0; \ 218 (gate).dpl = (d); \ 219 (gate).p = 1; \ 220 (gate).off_31_16 = (uint)(off) >> 16; \ 221 } 222 223 #endif 224