1*f5527388Srsc // See MultiProcessor Specification Version 1.[14]. 221a88fd4Skaashoek 3*f5527388Srsc struct mp { // floating pointer 4*f5527388Srsc uchar signature[4]; // "_MP_" 5*f5527388Srsc void *physaddr; // physical address of MP configuration table 6*f5527388Srsc uchar length; // 1 7*f5527388Srsc uchar specrev; // [14] 8*f5527388Srsc uchar checksum; // all bytes must add up to 0 9*f5527388Srsc uchar type; // MP system configuration type 1029270816Srtm uchar imcrp; 1129270816Srtm uchar reserved[3]; 127baa34a4Skaashoek }; 137baa34a4Skaashoek 14*f5527388Srsc struct mpctb { // configuration table header 15*f5527388Srsc uchar signature[4]; // "PCMP" 16*f5527388Srsc ushort length; // total table length 17*f5527388Srsc uchar version; // [14] 18*f5527388Srsc uchar checksum; // all bytes must add up to 0 19*f5527388Srsc uchar product[20]; // product id 20*f5527388Srsc uint *oemtable; // OEM table pointer 21*f5527388Srsc ushort oemlength; // OEM table length 22*f5527388Srsc ushort entry; // entry count 23*f5527388Srsc uint *lapicaddr; // address of local APIC 24*f5527388Srsc ushort xlength; // extended table length 25*f5527388Srsc uchar xchecksum; // extended table checksum 2629270816Srtm uchar reserved; 277baa34a4Skaashoek }; 287baa34a4Skaashoek 29*f5527388Srsc struct mppe { // processor table entry 30*f5527388Srsc uchar type; // entry type (0) 31*f5527388Srsc uchar apicid; // local APIC id 32*f5527388Srsc uchar version; // local APIC verison 33*f5527388Srsc uchar flags; // CPU flags 34*f5527388Srsc uchar signature[4]; // CPU signature 35*f5527388Srsc uint feature; // feature flags from CPUID instruction 3629270816Srtm uchar reserved[8]; 377baa34a4Skaashoek }; 387baa34a4Skaashoek 39*f5527388Srsc struct mpbe { // bus table entry 40*f5527388Srsc uchar type; // entry type (1) 41*f5527388Srsc uchar busno; // bus id 42*f5527388Srsc char string[6]; // bus type string 437baa34a4Skaashoek }; 447baa34a4Skaashoek 45*f5527388Srsc struct mpioapic { // I/O APIC table entry 46*f5527388Srsc uchar type; // entry type (2) 47*f5527388Srsc uchar apicno; // I/O APIC id 48*f5527388Srsc uchar version; // I/O APIC version 49*f5527388Srsc uchar flags; // I/O APIC flags 50*f5527388Srsc uint *addr; // I/O APIC address 517baa34a4Skaashoek }; 527baa34a4Skaashoek 53*f5527388Srsc struct mpie { // interrupt table entry 54*f5527388Srsc uchar type; // entry type ([34]) 55*f5527388Srsc uchar intr; // interrupt type 56*f5527388Srsc ushort flags; // interrupt flag 57*f5527388Srsc uchar busno; // source bus id 58*f5527388Srsc uchar irq; // source bus irq 59*f5527388Srsc uchar apicno; // destination APIC id 60*f5527388Srsc uchar intin; // destination APIC [L]INTIN# 617baa34a4Skaashoek }; 627baa34a4Skaashoek 63*f5527388Srsc enum { // table entry types 64*f5527388Srsc MPPROCESSOR = 0x00, // one entry per processor 65*f5527388Srsc MPBUS = 0x01, // one entry per bus 66*f5527388Srsc MPIOAPIC = 0x02, // one entry per I/O APIC 67*f5527388Srsc MPIOINTR = 0x03, // one entry per bus interrupt source 68*f5527388Srsc MPLINTR = 0x04, // one entry per system interrupt source 697baa34a4Skaashoek 7021a88fd4Skaashoek MPSASM = 0x80, 7121a88fd4Skaashoek MPHIERARCHY = 0x81, 7221a88fd4Skaashoek MPCBASM = 0x82, 737baa34a4Skaashoek 74*f5527388Srsc // PCMPprocessor and PCMPioapic flags 75*f5527388Srsc MPEN = 0x01, // enabled 76*f5527388Srsc MPBP = 0x02, // bootstrap processor 777baa34a4Skaashoek 78*f5527388Srsc // PCMPiointr and PCMPlintr flags 79*f5527388Srsc MPPOMASK = 0x03, // polarity conforms to specifications of bus 80*f5527388Srsc MPHIGH = 0x01, // active high 81*f5527388Srsc MPLOW = 0x03, // active low 82*f5527388Srsc MPELMASK = 0x0C, // trigger mode of APIC input signals 83*f5527388Srsc MPEDGE = 0x04, // edge-triggered 84*f5527388Srsc MPLEVEL = 0x0C, // level-triggered 857baa34a4Skaashoek 86*f5527388Srsc // PCMPiointr and PCMPlintr interrupt type 87*f5527388Srsc MPINT = 0x00, // vectored interrupt from APIC Rdt 88*f5527388Srsc MPNMI = 0x01, // non-maskable interrupt 89*f5527388Srsc MPSMI = 0x02, // system management interrupt 90*f5527388Srsc MPExtINT = 0x03, // vectored interrupt from external PIC 917baa34a4Skaashoek }; 927baa34a4Skaashoek 93*f5527388Srsc // Common bits for 94*f5527388Srsc // I/O APIC Redirection Table Entry; 95*f5527388Srsc // Local APIC Local Interrupt Vector Table; 96*f5527388Srsc // Local APIC Inter-Processor Interrupt; 97*f5527388Srsc // Local APIC Timer Vector Table. 987baa34a4Skaashoek enum { 99*f5527388Srsc APIC_FIXED = 0x00000000, // [10:8] Delivery Mode 100*f5527388Srsc APIC_LOWEST = 0x00000100, // Lowest priority 101*f5527388Srsc APIC_SMI = 0x00000200, // System Management Interrupt 102*f5527388Srsc APIC_RR = 0x00000300, // Remote Read 10321a88fd4Skaashoek APIC_NMI = 0x00000400, 104*f5527388Srsc APIC_INIT = 0x00000500, // INIT/RESET 105*f5527388Srsc APIC_STARTUP = 0x00000600, // Startup IPI 106bd303ed0Skaashoek APIC_EXTINT = 0x00000700, 1077baa34a4Skaashoek 108*f5527388Srsc APIC_PHYSICAL = 0x00000000, // [11] Destination Mode (RW) 10921a88fd4Skaashoek APIC_LOGICAL = 0x00000800, 1107baa34a4Skaashoek 111*f5527388Srsc APIC_DELIVS = 0x00001000, // [12] Delivery Status (RO) 112*f5527388Srsc APIC_HIGH = 0x00000000, // [13] Interrupt Input Pin Polarity (RW) 11321a88fd4Skaashoek APIC_LOW = 0x00002000, 114*f5527388Srsc APIC_REMOTEIRR = 0x00004000, // [14] Remote IRR (RO) 115*f5527388Srsc APIC_EDGE = 0x00000000, // [15] Trigger Mode (RW) 11621a88fd4Skaashoek APIC_LEVEL = 0x00008000, 117*f5527388Srsc APIC_IMASK = 0x00010000, // [16] Interrupt Mask 1187baa34a4Skaashoek }; 119