1 /* 2 * MultiProcessor Specification Version 1.[14]. 3 * 4 * Credit: Plan 9 sources 5 */ 6 7 struct MP { /* floating pointer */ 8 uint8_t signature[4]; /* "_MP_" */ 9 physaddr_t physaddr; /* physical address of MP configuration table */ 10 uint8_t length; /* 1 */ 11 uint8_t specrev; /* [14] */ 12 uint8_t checksum; /* all bytes must add up to 0 */ 13 uint8_t type; /* MP system configuration type */ 14 uint8_t imcrp; 15 uint8_t reserved[3]; 16 }; 17 18 struct MPCTB { /* configuration table header */ 19 uint8_t signature[4]; /* "PCMP" */ 20 uint16_t length; /* total table length */ 21 uint8_t version; /* [14] */ 22 uint8_t checksum; /* all bytes must add up to 0 */ 23 uint8_t product[20]; /* product id */ 24 uintptr_t oemtable; /* OEM table pointer */ 25 uint16_t oemlength; /* OEM table length */ 26 uint16_t entry; /* entry count */ 27 uintptr_t lapicaddr; /* address of local APIC */ 28 uint16_t xlength; /* extended table length */ 29 uint8_t xchecksum; /* extended table checksum */ 30 uint8_t reserved; 31 }; 32 33 struct MPPE { /* processor table entry */ 34 uint8_t type; /* entry type (0) */ 35 uint8_t apicid; /* local APIC id */ 36 uint8_t version; /* local APIC verison */ 37 uint8_t flags; /* CPU flags */ 38 uint8_t signature[4]; /* CPU signature */ 39 uint32_t feature; /* feature flags from CPUID instruction */ 40 uint8_t reserved[8]; 41 }; 42 43 struct MPBE { /* bus table entry */ 44 uint8_t type; /* entry type (1) */ 45 uint8_t busno; /* bus id */ 46 char string[6]; /* bus type string */ 47 }; 48 49 struct MPIOAPIC { /* I/O APIC table entry */ 50 uint8_t type; /* entry type (2) */ 51 uint8_t apicno; /* I/O APIC id */ 52 uint8_t version; /* I/O APIC version */ 53 uint8_t flags; /* I/O APIC flags */ 54 uintptr_t addr; /* I/O APIC address */ 55 }; 56 57 struct MPIE { /* interrupt table entry */ 58 uint8_t type; /* entry type ([34]) */ 59 uint8_t intr; /* interrupt type */ 60 uint16_t flags; /* interrupt flag */ 61 uint8_t busno; /* source bus id */ 62 uint8_t irq; /* source bus irq */ 63 uint8_t apicno; /* destination APIC id */ 64 uint8_t intin; /* destination APIC [L]INTIN# */ 65 }; 66 67 enum { /* table entry types */ 68 MPPROCESSOR = 0x00, /* one entry per processor */ 69 MPBUS = 0x01, /* one entry per bus */ 70 MPIOAPIC = 0x02, /* one entry per I/O APIC */ 71 MPIOINTR = 0x03, /* one entry per bus interrupt source */ 72 MPLINTR = 0x04, /* one entry per system interrupt source */ 73 74 MPSASM = 0x80, 75 MPHIERARCHY = 0x81, 76 MPCBASM = 0x82, 77 78 /* PCMPprocessor and PCMPioapic flags */ 79 MPEN = 0x01, /* enabled */ 80 MPBP = 0x02, /* bootstrap processor */ 81 82 /* PCMPiointr and PCMPlintr flags */ 83 MPPOMASK = 0x03, /* polarity conforms to specifications of bus */ 84 MPHIGH = 0x01, /* active high */ 85 MPLOW = 0x03, /* active low */ 86 MPELMASK = 0x0C, /* trigger mode of APIC input signals */ 87 MPEDGE = 0x04, /* edge-triggered */ 88 MPLEVEL = 0x0C, /* level-triggered */ 89 90 /* PCMPiointr and PCMPlintr interrupt type */ 91 MPINT = 0x00, /* vectored interrupt from APIC Rdt */ 92 MPNMI = 0x01, /* non-maskable interrupt */ 93 MPSMI = 0x02, /* system management interrupt */ 94 MPExtINT = 0x03, /* vectored interrupt from external PIC */ 95 }; 96 97 /* 98 * Common bits for 99 * I/O APIC Redirection Table Entry; 100 * Local APIC Local Interrupt Vector Table; 101 * Local APIC Inter-Processor Interrupt; 102 * Local APIC Timer Vector Table. 103 */ 104 enum { 105 APIC_FIXED = 0x00000000, /* [10:8] Delivery Mode */ 106 APIC_LOWEST = 0x00000100, /* Lowest priority */ 107 APIC_SMI = 0x00000200, /* System Management Interrupt */ 108 APIC_RR = 0x00000300, /* Remote Read */ 109 APIC_NMI = 0x00000400, 110 APIC_INIT = 0x00000500, /* INIT/RESET */ 111 APIC_STARTUP = 0x00000600, /* Startup IPI */ 112 APIC_ExtINT = 0x00000700, 113 114 APIC_PHYSICAL = 0x00000000, /* [11] Destination Mode (RW) */ 115 APIC_LOGICAL = 0x00000800, 116 117 APIC_DELIVS = 0x00001000, /* [12] Delivery Status (RO) */ 118 APIC_HIGH = 0x00000000, /* [13] Interrupt Input Pin Polarity (RW) */ 119 APIC_LOW = 0x00002000, 120 APIC_RemoteIRR = 0x00004000, /* [14] Remote IRR (RO) */ 121 APIC_EDGE = 0x00000000, /* [15] Trigger Mode (RW) */ 122 APIC_LEVEL = 0x00008000, 123 APIC_IMASK = 0x00010000, /* [16] Interrupt Mask */ 124 }; 125