131085bb4Srsc // Mutual exclusion spin locks. 231085bb4Srsc 321a88fd4Skaashoek #include "types.h" 421a88fd4Skaashoek #include "defs.h" 5558ab49fSrsc #include "param.h" 621a88fd4Skaashoek #include "x86.h" 77837c71bSkaashoek #include "mmu.h" 84e8f237bSrtm #include "proc.h" 94e8f237bSrtm #include "spinlock.h" 1021a88fd4Skaashoek 110e84a0ecSrtm void 12b121486cSRuss Cox initlock(struct spinlock *lk, char *name) 135be0039cSrtm { 14b121486cSRuss Cox lk->name = name; 15b121486cSRuss Cox lk->locked = 0; 16*48755214SRuss Cox lk->cpu = 0; 175be0039cSrtm } 185be0039cSrtm 1931085bb4Srsc // Acquire the lock. 2031085bb4Srsc // Loops (spins) until the lock is acquired. 21ab4cedb5Srtm // Holding a lock for a long time may cause 22ab4cedb5Srtm // other CPUs to waste time spinning to acquire it. 2321a88fd4Skaashoek void 24b121486cSRuss Cox acquire(struct spinlock *lk) 2521a88fd4Skaashoek { 263807c1f2Srsc pushcli(); 27b121486cSRuss Cox if(holding(lk)) 280dd42537Srsc panic("acquire"); 290dd42537Srsc 30943fd378Srsc // The xchg is atomic. 31943fd378Srsc // It also serializes, so that reads after acquire are not 32943fd378Srsc // reordered before it. 33b121486cSRuss Cox while(xchg(&lk->locked, 1) != 0) 3465bd8e13Srsc ; 35e7a5b3c5Srsc 3631085bb4Srsc // Record info about lock acquisition for debugging. 37*48755214SRuss Cox lk->cpu = cpu; 38b121486cSRuss Cox getcallerpcs(&lk, lk->pcs); 3921a88fd4Skaashoek } 4021a88fd4Skaashoek 4131085bb4Srsc // Release the lock. 4221a88fd4Skaashoek void 43b121486cSRuss Cox release(struct spinlock *lk) 4421a88fd4Skaashoek { 45b121486cSRuss Cox if(!holding(lk)) 460dd42537Srsc panic("release"); 470dd42537Srsc 48b121486cSRuss Cox lk->pcs[0] = 0; 49*48755214SRuss Cox lk->cpu = 0; 50e7a5b3c5Srsc 51943fd378Srsc // The xchg serializes, so that reads before release are 52be38c841Srtm // not reordered after it. The 1996 PentiumPro manual (Volume 3, 53be38c841Srtm // 7.2) says reads can be carried out speculatively and in 54be38c841Srtm // any order, which implies we need to serialize here. 55be38c841Srtm // But the 2007 Intel 64 Architecture Memory Ordering White 56be38c841Srtm // Paper says that Intel 64 and IA-32 will not move a load 57be38c841Srtm // after a store. So lock->locked = 0 would work here. 58be38c841Srtm // The xchg being asm volatile ensures gcc emits it after 59be38c841Srtm // the above assignments (and after the critical section). 60b121486cSRuss Cox xchg(&lk->locked, 0); 619fd9f804Srsc 623807c1f2Srsc popcli(); 6321a88fd4Skaashoek } 645af5f6aaSrsc 655af5f6aaSrsc // Record the current call stack in pcs[] by following the %ebp chain. 665af5f6aaSrsc void 675af5f6aaSrsc getcallerpcs(void *v, uint pcs[]) 685af5f6aaSrsc { 695af5f6aaSrsc uint *ebp; 705af5f6aaSrsc int i; 715af5f6aaSrsc 725af5f6aaSrsc ebp = (uint*)v - 2; 735af5f6aaSrsc for(i = 0; i < 10; i++){ 745af5f6aaSrsc if(ebp == 0 || ebp == (uint*)0xffffffff) 755af5f6aaSrsc break; 765af5f6aaSrsc pcs[i] = ebp[1]; // saved %eip 775af5f6aaSrsc ebp = (uint*)ebp[0]; // saved %ebp 785af5f6aaSrsc } 795af5f6aaSrsc for(; i < 10; i++) 805af5f6aaSrsc pcs[i] = 0; 815af5f6aaSrsc } 825af5f6aaSrsc 835af5f6aaSrsc // Check whether this cpu is holding the lock. 845af5f6aaSrsc int 855af5f6aaSrsc holding(struct spinlock *lock) 865af5f6aaSrsc { 87*48755214SRuss Cox return lock->locked && lock->cpu == cpu; 885af5f6aaSrsc } 895af5f6aaSrsc 90c8919e65Srsc 91ab08960fSrsc // Pushcli/popcli are like cli/sti except that they are matched: 92ab08960fSrsc // it takes two popcli to undo two pushcli. Also, if interrupts 93ab08960fSrsc // are off, then pushcli, popcli leaves them off. 94c8919e65Srsc 95c8919e65Srsc void 963807c1f2Srsc pushcli(void) 97c8919e65Srsc { 98ab08960fSrsc int eflags; 99ab08960fSrsc 10021575761Srsc eflags = readeflags(); 101c8919e65Srsc cli(); 102*48755214SRuss Cox if(cpu->ncli++ == 0) 103*48755214SRuss Cox cpu->intena = eflags & FL_IF; 104c8919e65Srsc } 105c8919e65Srsc 106c8919e65Srsc void 1073807c1f2Srsc popcli(void) 108c8919e65Srsc { 10921575761Srsc if(readeflags()&FL_IF) 1103807c1f2Srsc panic("popcli - interruptible"); 111*48755214SRuss Cox if(--cpu->ncli < 0) 1123807c1f2Srsc panic("popcli"); 113*48755214SRuss Cox if(cpu->ncli == 0 && cpu->intena) 114c8919e65Srsc sti(); 115c8919e65Srsc } 116c8919e65Srsc 117