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Revision tags: v6.2.1, v6.2.0, v6.3.0, v6.0.1, v6.0.0, v6.0.0rc1, v6.1.0, v5.8.3, v5.8.2, v5.8.1, v5.8.0, v5.9.0, v5.8.0rc1, v5.6.3, v5.6.2, v5.6.1, v5.6.0, v5.6.0rc1, v5.7.0, v5.4.3, v5.4.2, v5.4.1, v5.4.0, v5.5.0, v5.4.0rc1, v5.2.2, v5.2.1, v5.2.0, v5.3.0, v5.2.0rc, v5.0.2, v5.0.1, v5.0.0, v5.0.0rc2, v5.1.0, v5.0.0rc1, v4.8.1 |
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85ccd313 |
| 21-May-2017 |
Imre Vadász <imre@vdsz.com> |
A step to correctly handling command timeouts in the MMC layer.
- Now that properly issuing CMD6 is crucial (so data isn't written to
the wrong partition for example), make a step into the
A step to correctly handling command timeouts in the MMC layer.
- Now that properly issuing CMD6 is crucial (so data isn't written to
the wrong partition for example), make a step into the direction of
correctly handling the timeout for these commands in the MMC layer.
Also, do a SEND_STATUS when CMD6 is invoked with an R1B response as
recommended by relevant specifications. However, quite some work is
left to be done in this regard; all other R1B-type commands done by
the MMC layer also should be followed by a SEND_STATUS (CMD13), the
erase timeout calculations/handling as documented in specifications
are entirely ignored so far, the MMC layer doesn't provide timeouts
applicable up to the bridge drivers and at least sdhci(4) currently
is hardcoding 1 s as timeout for all command types unconditionally.
Let alone already available return codes often not being checked in
the MMC layer ...
- For devices following the eMMC specification v4.41 or later, year 0
is 2013 rather than 1997; so correct this for assembling the device
ID string properly.
* This omits all the parts specific to eMMC "partitions" from the FreeBSD
change.
* Add the Intel sdhci controller ids to sdhci_pci.c to set the
SDHCI_QUIRK_WAIT_WHILE_BUSY quirk there.
This also disables DMA on apollo lake sdhci, while there and whitelists
ADMA2 on Bay Trail and Braswell sdhci controllers.
Taken-From: FreeBSD (svn r315430)
show more ...
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