2ad04be3 | 26-Jun-2021 |
Aaron LI <aly@aaronly.me> |
npx: Fix XMM register count issue in 'savexmm64' struct
On 64-bit systems, there are 16 XMM registers (XMM0 - XMM15). And FXSAVE64/FXRSTOR64 instructions save/restore them to/from the 512-byte data
npx: Fix XMM register count issue in 'savexmm64' struct
On 64-bit systems, there are 16 XMM registers (XMM0 - XMM15). And FXSAVE64/FXRSTOR64 instructions save/restore them to/from the 512-byte data area.
So fix the 'savexmm64' structure to say 'struct xmmacc sv_xmm[16]', i.e., 16 XMM registers. The padding area is shrunk accordingly.
This issue is minor and has never caused any problems (because of the padding area), but still fix it.
While there, adjust various whitespace to look much better.
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357acec7 | 26-Jun-2021 |
Aaron LI <aly@aaronly.me> |
npx: Adjust the 'envxmm64' structure
* Replace 'en_rip' and 'en_rdp' fields with union equivalents, for accessing break-downs of these 64-bit fields.
* The break-down representation 'union fp_add
npx: Adjust the 'envxmm64' structure
* Replace 'en_rip' and 'en_rdp' fields with union equivalents, for accessing break-downs of these 64-bit fields.
* The break-down representation 'union fp_addr' is obtained from NetBSD.
* This helps adapt the NVMM backend code in QEMU to DragonFly.
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13fa9066 | 26-Jun-2021 |
Aaron LI <aly@aaronly.me> |
x86_64/pmap.h: Adjust Intel EPT defines
According to Intel SDM (Section 28.2.2: EPT Translation Mechanism), bit 10 indicates the execute access for user-mode linear addresses when the "mode-based ex
x86_64/pmap.h: Adjust Intel EPT defines
According to Intel SDM (Section 28.2.2: EPT Translation Mechanism), bit 10 indicates the execute access for user-mode linear addresses when the "mode-based execute control for EPT" VM-execution control is enabled, otherwise, it's ignored.
So to be future-proof, don't define bit 10 as EPT_PG_AVAIL1, which is use as the "wired" bit. Instead, use the ignored bit 11 for this purpose.
In addition, use ignored bits 59:52 for other EPT_PG_AVAIL* bits.
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a69b35e0 | 03-Jun-2021 |
Aaron LI <aly@aaronly.me> |
x86_64/pmap.h: Move Intel EPT defines from <vmm/ept.h>
Renamed 'EPT_IGNORE_PAT' to 'EPT_PG_IGNORE_PAT' for better naming consistency. Fixes to the vmm/ept code will follow.
While there, minor styl
x86_64/pmap.h: Move Intel EPT defines from <vmm/ept.h>
Renamed 'EPT_IGNORE_PAT' to 'EPT_PG_IGNORE_PAT' for better naming consistency. Fixes to the vmm/ept code will follow.
While there, minor style adjustments.
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60625a4d | 26-May-2021 |
Aaron LI <aly@aaronly.me> |
x86_64/specialreg.h: Deprecate old defines of Spectre mitigation
Migrate the old defines of Spectre mitigation to the new ones obtained from NetBSD and FreeBSD. Specifically, apply the following ch
x86_64/specialreg.h: Deprecate old defines of Spectre mitigation
Migrate the old defines of Spectre mitigation to the new ones obtained from NetBSD and FreeBSD. Specifically, apply the following changes:
* CPUID_7_0_I3_* -> CPUID_STDEXT3_* * CPUID_SEF_* -> CPUID_STDEXT3_* * CPUID_*_80000008_I1_* -> CPUID_CAPEX_*
In addition, merge the comments to the relevant code.
No functional changes.
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96abf295 | 11-May-2021 |
Aaron LI <aly@aaronly.me> |
x86_64/specialreg.h: Add several MSR defines for NVMM
* Add MSR_IA32_FLUSH_CMD define, together with one bit define. * Add various bit defines for MSR_IA32_MISC_ENABLE. * Add MSR_AMD_NB_CFG, MSR_AMD
x86_64/specialreg.h: Add several MSR defines for NVMM
* Add MSR_IA32_FLUSH_CMD define, together with one bit define. * Add various bit defines for MSR_IA32_MISC_ENABLE. * Add MSR_AMD_NB_CFG, MSR_AMD_PATCH_LEVEL, MSR_AMD_LS_CFG, and MSR_AMD_IC_CFG defines. * Rename MSR_K8_UCODE_UPDATE -> MSR_AMD_PATCH_LOADER, for naming consistency.
Taken from NetBSD and referred to FreeBSD.
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