Revision tags: v6.2.1, v6.2.0, v6.3.0, v6.0.1, v6.0.0, v6.0.0rc1, v6.1.0, v5.8.3, v5.8.2, v5.8.1, v5.8.0, v5.9.0, v5.8.0rc1, v5.6.3, v5.6.2, v5.6.1, v5.6.0, v5.6.0rc1, v5.7.0, v5.4.3, v5.4.2, v5.4.1, v5.4.0, v5.5.0, v5.4.0rc1, v5.2.2, v5.2.1, v5.2.0, v5.3.0, v5.2.0rc, v5.0.2, v5.0.1, v5.0.0, v5.0.0rc2, v5.1.0, v5.0.0rc1, v4.8.1, v4.8.0, v4.6.2, v4.9.0, v4.8.0rc, v4.6.1, v4.6.0, v4.6.0rc2, v4.6.0rc, v4.7.0, v4.4.3, v4.4.2, v4.4.1, v4.4.0, v4.5.0, v4.4.0rc, v4.2.4, v4.3.1, v4.2.3, v4.2.1, v4.2.0, v4.0.6, v4.3.0, v4.2.0rc, v4.0.5, v4.0.4 |
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d9902073 |
| 12-Feb-2015 |
Sepherosa Ziehau <sephe@dragonflybsd.org> |
memtemp: Add support for Intel Core Haswell and E3 v3 cpus
Tested-by: dillon@ (no sensors available though)
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f7409137 |
| 11-Feb-2015 |
Sepherosa Ziehau <sephe@dragonflybsd.org> |
ecc/e3: Split it into two drivers, coremctl(4) and ecc(4)
coremctl(4), which maps the MCHBAR, is now the parent of ecc(4) for Intel E3 cpus. This paves way to add Intel Core/E3 support to memtemp(4
ecc/e3: Split it into two drivers, coremctl(4) and ecc(4)
coremctl(4), which maps the MCHBAR, is now the parent of ecc(4) for Intel E3 cpus. This paves way to add Intel Core/E3 support to memtemp(4).
Tested-by: dillon@ on i3/Haswell and E3/v3
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