bce: Use ringmap to do MSI-X cpu assignment and fill redirect table.

kernel: Use the new auto-created sysctl ctx/tree in various drivers.

Everywhere where we formerly rolled a hw.fooX.* per-device ctx/tree
ourselves.

This commit switches it to dev.foo.X.*

ifnet: Simplify ifnet_serialize_array function interface

It is no longer used to hold RX or TX serializers, so the RX/TX
serializer offset function arguments are not necessary at all.

bce: Pack RX/TX mbuf related fields into struct

Mainly to improve cache utilization.

bce: Implement multiple TX/RX rings and MSI-X support for 5709/5716

5709/5716 support 9 RX rings, 9 TX rings and 9 MSI-X vectors; each
MSI-X vector has its own interrupt moderation parameters.

(N +

bce: Implement multiple TX/RX rings and MSI-X support for 5709/5716

5709/5716 support 9 RX rings, 9 TX rings and 9 MSI-X vectors; each
MSI-X vector has its own interrupt moderation parameters.

(N + 1) RX rings, N TX rings and (N + 1) MSI-X vectors will be enabled;
N is ncpus2, if ncpus2 is less than 8, else N will be 8.

The extra RX ring is enabled mainly because:
The first RX ring is only used for packets whose RSS hash could not
be calculated, so it is actually _not_ involved in RSS. This extra RX
ring is used for the packets whose masked RSS hash equal 0.

An extra MSI-X vector is allocated for this extra RX ring; there is no
correponding TX ring for this extra RX ring. In polling(4), this extra
RX ring is polled along with the first RX ring in the first RX polling
handler, in which the packets whose RSS hash equal 0 should be processed.

Hardware provided RSS hash and packet type are not utilized yet; they will
be supported in the upcoming commits.

Related hardware registers and hardware initialization order are infered
from Linux's bnx2 (*); NetXtremeII-PG203-R.pdf provided on Broadcom's
website does not contain enough information for multiple rings and MSI-X
to function.

(*) Unlike Linux's bnx2, which limits number of RX rings to 8, DragonFly
limits number of RX rings to 9 and 9 RX rings actually work quite well.

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bce: Move status index's location and cached status index into RX ring

bce: Cache TX/RX consumer indices' location

Using the them to access TX/RX consumer indices instead of directly
accessing status block; prepare for the MSI-X support

bce: Save CID into related TX/RX ring struct

bce: Fix tick/pulse callout target CPU setting

bce: RX and TX ring counts are not required to be same

However, in Dragonfly, RX ring count must be great than TX ring count.

Clue-from: Linux bnx2

bce: Switch to IFQ subqueue functions and use per-TX queue watchdog

bce: Reimplement polling in non-compat mode

Take advantage of the independent TX/RX serializers.

bce: Split TX/RX serializer

bce: Put RX related fields into bce_rx_ring

bce: Put TX related fields into bce_tx_ring

bce: Remove debug stuffs

opt_bce.h is still kept, which will be needed for multiple RX/TX queues
debugging options.

bce: Improve tiny packets transmission performance on low frequency CPU

Update TX HOST_IDX and HOST_BSEQ registers a little bit often; mainly to
improve timeliness of packets transmission:
The TX HO

bce: Improve tiny packets transmission performance on low frequency CPU

Update TX HOST_IDX and HOST_BSEQ registers a little bit often; mainly to
improve timeliness of packets transmission:
The TX HOST_IDX and HOST_BSEQ registers are updated after certain amount
of TX descriptors are added to the hardware TX ring. The default value
of the amount of TX descriptors are 8. This value could be further
tuned by per-device sysctl node hw.bceX.tx_wreg.

The default value greatly improves tiny packets transmission performance
w/ 5709C on AMD970@800Mhz (513Kpps -> 1Mpps) and it does not increase CPU
usage on AMD970@3500Mhz (CPU usage stays @24%, 5709C could only do 1Mpps).

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bce: Switch from device_polling to ifpoll

bce: Rework MSI checkout for 5706 and 5708

bce: Add TSO support

Obatined-from: FreeBSD

With following modification:
These chips can handle ip.ip_len and tcphdr.th_sum, if they are setup
according to Microsoft LSO specification, so ip.ip_len

bce: Add TSO support

Obatined-from: FreeBSD

With following modification:
These chips can handle ip.ip_len and tcphdr.th_sum, if they are setup
according to Microsoft LSO specification, so ip.ip_len should not be
cleared and tcphdr.th_sum should be left as it is.

According-to: bnx2

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bce: Don't loop in the interrupt handler to drain TX/RX

bce: Configuable number of TX/RX descriptor pages

bce: Add workaround for the lost of MSI on 5706/5708

While I'm here use ramn_get_cpuid to extract interrupt's target CPU

Obtained-from: bnx2

bce: Split out frontend for interrupt handler

For non-oneshot MSI, we don't need to make sure that status block has
been updated and we don't need extra register read to flush the ACK_CMD;
MSI has a

bce: Split out frontend for interrupt handler

For non-oneshot MSI, we don't need to make sure that status block has
been updated and we don't need extra register read to flush the ACK_CMD;
MSI has already made sure about those.

For oneshot MSI, we don't even need to ACK the interrupt

Obtaied-from: bnx2

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pci: Factor out pci_alloc_1intr()

This function will properly setup rid and flags for "legacy" interrupt.
If MSI is enabled, then this function will try allocate 1 MSI message
and setup rid and flag

pci: Factor out pci_alloc_1intr()

This function will properly setup rid and flags for "legacy" interrupt.
If MSI is enabled, then this function will try allocate 1 MSI message
and setup rid and flags properly for MSI based interrupt resource.

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