sys: Automated cleanup of cdefs and other formatting

Apply the following automated changes to try to eliminate
no-longer-needed sys/cdefs.h includes as well as now-empty
blank lines in a row.

Remov

sys: Automated cleanup of cdefs and other formatting

Apply the following automated changes to try to eliminate
no-longer-needed sys/cdefs.h includes as well as now-empty
blank lines in a row.

Remove /^#if.*\n#endif.*\n#include\s+<sys/cdefs.h>.*\n/
Remove /\n+#include\s+<sys/cdefs.h>.*\n+#if.*\n#endif.*\n+/
Remove /\n+#if.*\n#endif.*\n+/
Remove /^#if.*\n#endif.*\n/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/types.h>/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/param.h>/
Remove /\n+#include\s+<sys/cdefs.h>\n#include\s+<sys/capsicum.h>/

Sponsored by: Netflix

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sys: Remove $FreeBSD$: one-line .c pattern

Remove /^[\s*]*__FBSDID\("\$FreeBSD\$"\);?\s*\n/

arm/arm: Remove unused devclass arguments to DRIVER_MODULE.

arm: clean up empty lines in .c and .h files

Revert r339421 due to unintended files included to commit.

Reported by: ian
Approved by: re (gjb)
Sponsored by: DARPA, AFRL

Support RISC-V implementations that do not manage the A and D bits
(e.g. RocketChip, lowRISC and derivatives).

RISC-V page table entries support A (accessed) and D (dirty) bits. The
spec makes hardw

Support RISC-V implementations that do not manage the A and D bits
(e.g. RocketChip, lowRISC and derivatives).

RISC-V page table entries support A (accessed) and D (dirty) bits. The
spec makes hardware support for these bits optional. Implementations that
do not manage these bits in hardware raise page faults for accesses to a
valid page without A set and writes to a writable page without D set.
Check for these types of faults when handling a page fault and fixup the
PTE without calling vm_fault if they occur.

Reviewed by: jhb, markj
Approved by: re (gjb)
Sponsored by: DARPA, AFRL
Differential Revision: https://reviews.freebsd.org/D17424

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sys/arm: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error

sys/arm: further adoption of SPDX licensing ID tags.

Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

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Add external PLATFORM access on arm, and use it in the pl310 driver.

This allows multiple instances of SoCs that use the pl310 driver to be
built within the same kernel:

* Add access to the platfo

Add external PLATFORM access on arm, and use it in the pl310 driver.

This allows multiple instances of SoCs that use the pl310 driver to be
built within the same kernel:

* Add access to the platform_t object from outside platform.c
* Use this with the pl310 driver

There is a new platform_pl310 interface to replace the existing code. SoCs
need to implement the init method, and if they have special requirements to
write to the two registers we care about will also need to implement the
write_ctrl and write_debug methods.

Differential Revision: https://reviews.freebsd.org/D11546

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Disable PL310 outer cache sync for IO coherent platforms

When a PL310 cache is used on a system that provides hardware
coherency, the outer cache sync operation is useless, and can be
skipped. Moreo

Disable PL310 outer cache sync for IO coherent platforms

When a PL310 cache is used on a system that provides hardware
coherency, the outer cache sync operation is useless, and can be
skipped. Moreover, on some systems, it is harmful as it causes
deadlocks between the Marvell coherency mechanism, the Marvell PCIe
or Crypto controllers and the Cortex-A9.

To avoid this, this commit introduces a new Device Tree property
'arm,io-coherent' for the L2 cache controller node, valid only for the
PL310 cache. It identifies the usage of the PL310 cache in an I/O
coherent configuration. Internally, it makes the driver disable the
outer cache sync operation.

Note, that other outer-cache operations are not removed, as they may
be needed for certain situations, such as booting secondary CPUs.
Moreover, in order to enable IO coherent operation, the decision
whether to use L2 cache maintenance callbacks is done in busdma
layer, which was enabled in one of the previous commits.

Submitted by: Michal Mazur <mkm@semihalf.com>
Marcin Wojtas <mw@semihalf.com>
Reviewed by: mmel
Obtained from: Semihalf
Differential revision: https://reviews.freebsd.org/D11245

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Execute PL310_ERRATA_727915 only for related revisions

Part of PL310 erratum 727915 in pl310_wbinv_range() was
executed uncoditionally for all possible controllers'
revisions. This patch adds approp

Execute PL310_ERRATA_727915 only for related revisions

Part of PL310 erratum 727915 in pl310_wbinv_range() was
executed uncoditionally for all possible controllers'
revisions. This patch adds appropriate condition, since
extra operations are required only for revisions between
r2p0 and r3p0.

Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: meloun-miracle-cz
Differential revision: https://reviews.freebsd.org/D10221

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Stop including fdt_common.h from the arm code when it's unneeded.

Sponsored by: ABT Systems Ltd

Make pl310_print_config static, it's not called out of pl310.c

Sponsored by: ABT Systems Ltd

Remove trailing whitespace from sys/arm/arm

- Make interrupt resource optional: some upstream FDT blobs (e.g. TI's) do
not have interupt property in pl310 node. Interrupt is used only to
detect cache activity when L2 cache is disabled,

- Make interrupt resource optional: some upstream FDT blobs (e.g. TI's) do
not have interupt property in pl310 node. Interrupt is used only to
detect cache activity when L2 cache is disabled, it's not vital for
normal operations.
- Fix intrhook allocation/initialization

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Accept the documented FDT compatible string for the PL310 cache controller
as well as the non-standard string we've been using for a couple years.

Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU.
Because that's earlier than interrupts are available, set up deferred
configuration of interrupts (which are used only for d

Set the pl310 L2 cache driver to attach during the middle of BUS_PASS_CPU.
Because that's earlier than interrupts are available, set up deferred
configuration of interrupts (which are used only for debugging).

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Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().

On modern ARM SoCs the L2 cache controller sits between the CPU and the
AXI bus, and most on-chip memory-mapped devices ar

Add cpu_l2cache_drain_writebuf(), use it to implement generic_bs_barrier().

On modern ARM SoCs the L2 cache controller sits between the CPU and the
AXI bus, and most on-chip memory-mapped devices are on the AXI bus. We
map the device registers using the 'Device' memory attribute, which means
the memory is not cached, but writes to it are buffered. Ensuring that a
write has made it all the way to a device may require that the L2
controller take some action.

There is currently only one implementation of the new function, for the
PL310 cache controller. It invokes a function that the controller
manual calls "cache sync" but it actually has nothing to do with cache at
all, it triggers a drain of all pending store buffer writes and it blocks
until they complete.

The sheeva and xscale L2 controllers (which predate the concept of Device
memory) don't seem to have a corresponding function. It appears that the
standard armv5 drain_writebuf function includes draining all the way
through the L2 controller.

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Add a public routine to set the L2 cache ram latencies. This can be
called by platform init routines to fine-tune cache performance.

Call platform_pl310_init() before enabling the controller, and handle the
case where the controller is already enabled.

Some of the pl310 configuration registers cannot be changed while the
controll

Call platform_pl310_init() before enabling the controller, and handle the
case where the controller is already enabled.

Some of the pl310 configuration registers cannot be changed while the
controller is active, so if there is any platform-specific init to be done
it must happen before enabling the controller.

The controller should not be enabled upon entry to the kernel, but u-boot
has recently developed the bad habit of leaving caches enabled when
launching the kernel, and since we have no control over that source code
we have to do our best to cope with it. The PL310 manual doesn't document
a safe sequence for disabling the controller, but the sequence used here
(force write-through mode and disable linefill allocations, then clean and
invalidate the current contents before disabling the hardware) appears to
be sound both by analysis and empirical testing.

These changes were developed and tested in collaboration with
Svatopluk Kraus <onwahe@gmail.com>.

Reviewed by: cognet@

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Break out the code that figures out the L2 cache geometry to its own
routine, so that it can be called from multiple places in upcoming changes.

Move the pl310.enabled tunable to hw.pl310.enabled. Clean up a few minor
style(9) nits. Use DEVMETHOD_END.

Move duplicated code to print l2 cache config into the common code.

Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.

Simplebus used to only instantiate its children whose status="okay"
but t

Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.

Simplebus used to only instantiate its children whose status="okay"
but that was improper behavior, fixed in r261352. Now that it doesn't
check anymore and probes all its children; the children all have to
do the check because really only the children know how to properly
interpret their status property strings.

Right now all existing drivers only understand "okay" versus something-
that's-not-okay, so they all use the new ofw_bus_status_okay() helper.

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Invalidate the entire L2 cache before enabling it. Say whether it
has been enabled or disabled.

The errata 727915 requires a different workaround for r2p0, we have to
explicitely clean/invalidate every cache line using way/set operations.