#
41b3a96c |
| 24-Oct-2023 |
Hsiao Chien Sung <shawn.sung@mediatek.com> |
dt-bindings: arm: mediatek: Add compatible for MT8188
Add compatible name for MediaTek MT8188 VDOSYS1.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Kr
dt-bindings: arm: mediatek: Add compatible for MT8188
Add compatible name for MediaTek MT8188 VDOSYS1.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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26bcd8a5 |
| 20-Nov-2023 |
yu-chang.lee <yu-chang.lee@mediatek.com> |
dt-bindings: arm: mediatek: mmsys: Add VPPSYS compatible for MT8188
For MT8188, VPPSYS0 and VPPSYS1 are 2 display pipes with hardware differences in power domains, clocks and subsystem counts, which
dt-bindings: arm: mediatek: mmsys: Add VPPSYS compatible for MT8188
For MT8188, VPPSYS0 and VPPSYS1 are 2 display pipes with hardware differences in power domains, clocks and subsystem counts, which should be probed from mtk-mmsys driver to populate device by platform_device_register_data then start its own clock driver.
Signed-off-by: yu-chang.lee <yu-chang.lee@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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4b71ed9f |
| 22-Mar-2023 |
Rob Herring <robh@kernel.org> |
dt-bindings: arm/soc: mediatek: Drop unneeded quotes
Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint.
Reviewed-by: Krzysztof Kozlow
dt-bindings: arm/soc: mediatek: Drop unneeded quotes
Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20230322173501.3970991-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
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1873da26 |
| 18-Jan-2023 |
Moudy Ho <moudy.ho@mediatek.com> |
dt-bindings: arm: mediatek: mmsys: Add support for MT8195 VPPSYS
For MT8195, VPPSYS0 and VPPSYS1 are 2 display pipes with hardware differences in power domains, clocks and subsystem counts, which sh
dt-bindings: arm: mediatek: mmsys: Add support for MT8195 VPPSYS
For MT8195, VPPSYS0 and VPPSYS1 are 2 display pipes with hardware differences in power domains, clocks and subsystem counts, which should be determined by compatible names.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230118031509.29834-3-moudy.ho@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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82219cfb |
| 13-Jan-2023 |
Nancy.Lin <nancy.lin@mediatek.com> |
dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
Add vdosys1 mmsys compatible for MT8195 platform.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 differ
dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195
Add vdosys1 mmsys compatible for MT8195 platform.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 different power domains, different clock drivers and different mediatek-drm drivers.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230113104434.28023-2-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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2433c716 |
| 06-Dec-2022 |
Nathan Lu <nathan.lu@mediatek.com> |
dt-bindings: mediatek: modify VDOSYS0 mmsys device tree Documentations for MT8188
modify VDOSYS0 mmsys device tree Documentations for MT8188.
Signed-off-by: Nathan Lu <nathan.lu@mediatek.com> Acked
dt-bindings: mediatek: modify VDOSYS0 mmsys device tree Documentations for MT8188
modify VDOSYS0 mmsys device tree Documentations for MT8188.
Signed-off-by: Nathan Lu <nathan.lu@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221206020046.11333-3-nathan.lu@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
b237efd4 |
| 27-Sep-2022 |
Jason-JH.Lin <jason-jh.lin@mediatek.com> |
dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
For previous MediaTek SoCs, such as MT8173, there are 2 display HW pipelines binding to 1 mmsys with the same power domain, the same c
dt-bindings: arm: mediatek: mmsys: change compatible for MT8195
For previous MediaTek SoCs, such as MT8173, there are 2 display HW pipelines binding to 1 mmsys with the same power domain, the same clock driver and the same mediatek-drm driver.
For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 different power domains, different clock drivers and different mediatek-drm drivers.
Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR, CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality) and they makes VDOSYS0 supports PQ function while they are not including in VDOSYS1.
Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related component). It makes VDOSYS1 supports the HDR function while it's not including in VDOSYS0.
To summarize0: Only VDOSYS0 can support PQ adjustment. Only VDOSYS1 can support HDR adjustment.
Therefore, we need to separate these two different mmsys hardwares to 2 different compatibles for MT8195.
Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding") Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220927152704.12018-2-jason-jh.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
cd425807 |
| 21-Sep-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
dt-bindings: mailbox: Convert mtk-gce to DT schema
Convert the mtk-gce mailbox binding to DT schema format.
During the conversion, the examples for client device/mutex nodes were removed, as these
dt-bindings: mailbox: Convert mtk-gce to DT schema
Convert the mtk-gce mailbox binding to DT schema format.
During the conversion, the examples for client device/mutex nodes were removed, as these are found in their respective bindings: arm/mediatek/mediatek,mmsys.yaml for "mediatek,mt8173-mmsys" soc/mediatek/mediatek,mutex.yaml for "mediatek,mt8173-disp-mutex"
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220921090006.37642-1-angelogioacchino.delregno@collabora.com Signed-off-by: Rob Herring <robh@kernel.org>
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d5099c95 |
| 21-Sep-2022 |
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> |
dt-bindings: mediatek: Document MT6795 system controllers bindings
Document the MediaTek Helio X10 (MT6795) bindings for the apmixedsys, infracfg, topckgen, pericfg and mmsys system controllers.
Si
dt-bindings: mediatek: Document MT6795 system controllers bindings
Document the MediaTek Helio X10 (MT6795) bindings for the apmixedsys, infracfg, topckgen, pericfg and mmsys system controllers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220921091455.41327-2-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
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#
81c5a41d |
| 19-Apr-2022 |
jason-jh.lin <jason-jh.lin@mediatek.com> |
dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
In the SoC before, such as mt8173, it has 2 pipelines binding to one mmsys with the same clock driver and the same power domain.
In mt8195,
dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
In the SoC before, such as mt8173, it has 2 pipelines binding to one mmsys with the same clock driver and the same power domain.
In mt8195, there are 4 pipelines binding to 4 different mmsys, such as vdosys0, vdosys1, vppsys0 and vppsys1. Each mmsys uses different clock drivers and different power domain.
Since each mmsys has its own mmio base address, they could be identified by their different address during probe time.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220419033237.23405-3-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
1da90b8a |
| 19-Apr-2022 |
jason-jh.lin <jason-jh.lin@mediatek.com> |
dt-bindings: arm: mediatek: mmsys: add power and gce properties
Power: 1. Add description for power-domains property.
GCE: 1. Add description for mboxes property. 2. Add description for mediatek,gc
dt-bindings: arm: mediatek: mmsys: add power and gce properties
Power: 1. Add description for power-domains property.
GCE: 1. Add description for mboxes property. 2. Add description for mediatek,gce-client-reg property.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Link: https://lore.kernel.org/r/20220419033237.23405-2-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
eb1b02be |
| 01-Mar-2022 |
Rex-BC Chen <rex-bc.chen@mediatek.com> |
dt-bindings: arm: mediatek: mmsys: add support for MT8186
Add "mediatek,mt8186-mmsys" to binding document.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Rob Herring <robh@kernel.o
dt-bindings: arm: mediatek: mmsys: add support for MT8186
Add "mediatek,mt8186-mmsys" to binding document.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220301080105.31323-2-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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6046ffc3 |
| 30-Sep-2021 |
Enric Balletbo i Serra <enric.balletbo@collabora.com> |
dt-bindings: mediatek: Add #reset-cells to mmsys system controller
The mmsys system controller exposes a set of memory client resets and needs to specify the #reset-cells property in order to advert
dt-bindings: mediatek: Add #reset-cells to mmsys system controller
The mmsys system controller exposes a set of memory client resets and needs to specify the #reset-cells property in order to advertise the number of cells needed to describe each of the resets.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210930103105.v4.2.I3f7f1c9a8e46be07d1757ddf4e0097535f3a7d41@changeid Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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#
75d6e7d9 |
| 02-Sep-2021 |
Linus Torvalds <torvalds@linux-foundation.org> |
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "Nothing changed in the clk framework core this time around. We did get so
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd: "Nothing changed in the clk framework core this time around. We did get some updates to the basic clk types to use determine_rate for the divider type and add a power of two fractional divider flag though.
Otherwise, this is a collection of clk driver updates. More than half the diffstat is in the Qualcomm clk driver where we add a bunch of data to describe clks on various SoCs and fix bugs. The other big new thing in here is the Mediatek MT8192 clk driver. That's been under review for a while and it's nice to see that it's finally upstream.
Beyond that it's the usual set of minor fixes and tweaks to clk drivers. There are some non-clk driver bits in here which have all been acked by the respective maintainers.
New Drivers: - Support video, gpu, display clks on qcom sc7280 SoCs - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs - Multimedia clks (MMCC) on qcom MSM8994/MSM8992 - RPMh clks on qcom SM6350 SoCs - Support for Mediatek MT8192 SoCs - Add display (DU and DSI) clocks on Renesas R-Car V3U - Add I2C, DMAC, USB, sound (SSIF-2), GPIO, CANFD, and ADC clocks and resets on Renesas RZ/G2L
Updates: - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators - Add power of two flag to fractional divider clk type - Migrate some clk drivers to clk_divider_ops.determine_rate - Migrate to clk_parent_data in gcc-sdm660 - Fix CLKOUT clocks on i.MX8MM and i.MX8MN by using imx_clk_hw_mux2 - Switch from .round_rate to .determine_rate in clk-divider-gate - Fix clock tree update for TF-A controlled clocks for all i.MX8M - Add missing M7 core clock for i.MX8MN - YAML conversion of rk3399 clock controller binding - Removal of GRF dependency for the rk3328/rk3036 pll types - Drop CLK_IS_CRITICAL flag from Tegra fuse clk - Make CLK_R9A06G032 Kconfig symbol invisible - Convert various DT bindings to YAML"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (128 commits) dt-bindings: clock: samsung: fix header path in example clk: tegra: fix old-style declaration clk: qcom: Add SM6350 GCC driver MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema dt-bindings: clock: samsung: convert Exynos AudSS to dtschema dt-bindings: clock: samsung: convert Exynos4 to dtschema dt-bindings: clock: samsung: convert Exynos3250 to dtschema dt-bindings: clock: samsung: convert Exynos542x to dtschema dt-bindings: clock: samsung: add bindings for Exynos external clock dt-bindings: clock: samsung: convert Exynos5250 to dtschema clk: vc5: Add properties for configuring SD/OE behavior clk: vc5: Use dev_err_probe dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin dt-bindings: clock: brcm,iproc-clocks: fix armpll properties clk: zynqmp: Fix kernel-doc format clk: at91: clk-generated: Limit the requested rate to our range clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates clk: zynqmp: Fix a memory leak clk: zynqmp: Check the return type ...
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#
f72999f5 |
| 19-May-2021 |
Fabien Parent <fparent@baylibre.com> |
dt-bindings: arm: mediatek: mmsys: add MT8365 SoC binding
Add the MMSYS binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Rob Herring <robh@
dt-bindings: arm: mediatek: mmsys: add MT8365 SoC binding
Add the MMSYS binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210519161847.3747352-2-fparent@baylibre.com
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cba3c40d |
| 19-May-2021 |
Fabien Parent <fparent@baylibre.com> |
dt-bindings: arm: mediatek: mmsys: convert to YAML format
Convert the mmsys bindings to the YAML format.
Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.or
dt-bindings: arm: mediatek: mmsys: convert to YAML format
Convert the mmsys bindings to the YAML format.
Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210519161847.3747352-1-fparent@baylibre.com
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