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049010c9 |
| 22-Jan-2024 |
Nishanth Menon <nm@ti.com> |
arm64: dts: ti: phycore*: Add MIT license along with GPL-2.0
Modify license to include dual licensing as GPL-2.0-only OR MIT license for device trees belonging to PHYTEC Messtechnik GmbH and PHYTEC
arm64: dts: ti: phycore*: Add MIT license along with GPL-2.0
Modify license to include dual licensing as GPL-2.0-only OR MIT license for device trees belonging to PHYTEC Messtechnik GmbH and PHYTEC America, LLC platforms. This allows for Linux kernel device tree to be used in other Operating System ecosystems such as Zephyr or FreeBSD.
While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated).
While at this, update the copyright year to sync with current year to indicate license change.
Cc: Garrett Giordano <ggiordano@phytec.com> Cc: Wadim Egorov <w.egorov@phytec.de>
Acked-by: Garrett Giordano <ggiordano@phytec.com> Acked-by: Wadim Egorov <w.egorov@phytec.de> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240122145539.194512-15-nm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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61fc6b43 |
| 01-Feb-2024 |
Nathan Morrisson <nmorrisson@phytec.com> |
arm64: dts: ti: phycore-am64: Add ADC
Add the ADC node to the phyCORE AM64x and enable the ADC.
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de
arm64: dts: ti: phycore-am64: Add ADC
Add the ADC node to the phyCORE AM64x and enable the ADC.
Signed-off-by: Nathan Morrisson <nmorrisson@phytec.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20240201001439.3259450-1-nmorrisson@phytec.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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5709a680 |
| 04-Dec-2023 |
Garrett Giordano <ggiordano@phytec.com> |
arm64: dts: ti: phycore-am64: Add R5F DMA Region and Mailboxes
Communication between the R5F subsystem and Linux takes place using DMA memory regions and mailboxes. Here we add DT nodes for the memo
arm64: dts: ti: phycore-am64: Add R5F DMA Region and Mailboxes
Communication between the R5F subsystem and Linux takes place using DMA memory regions and mailboxes. Here we add DT nodes for the memory regions and mailboxes to facilitate communication between the R5 clusters and Linux as remoteproc will fail to start if no memory regions or mailboxes are provided.
Fixes: c48ac0efe6d7 ("arm64: dts: ti: Add support for phyBOARD-Electra-AM642") Signed-off-by: Garrett Giordano <ggiordano@phytec.com> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20231204212304.1736306-1-ggiordano@phytec.com Signed-off-by: Nishanth Menon <nm@ti.com>
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3b6345e3 |
| 17-Nov-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable SDHCI nodes at the board level
SDHCI nodes defined in the top-level AM64 SoC dtsi files are incomplete and will not be functional unless they are extended.
As the at
arm64: dts: ti: k3-am64: Enable SDHCI nodes at the board level
SDHCI nodes defined in the top-level AM64 SoC dtsi files are incomplete and will not be functional unless they are extended.
As the attached SD/eMMC is only known about at the board integration level, these nodes should only be enabled when provided with this information.
Disable the SDHCI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20231117163339.89952-2-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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a1cd710f |
| 14-Sep-2023 |
Wadim Egorov <w.egorov@phytec.de> |
arm64: dts: ti: phycore-am64: Add RTC interrupt pin
Wth commit 16b26f602758 ("rtc: rv3028: Use IRQ flags obtained from device tree if available") we can now use the interrupt pin of the RTC. Let's a
arm64: dts: ti: phycore-am64: Add RTC interrupt pin
Wth commit 16b26f602758 ("rtc: rv3028: Use IRQ flags obtained from device tree if available") we can now use the interrupt pin of the RTC. Let's add interrupt pin definitions to the SoM RTC.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Link: https://lore.kernel.org/r/20230914093027.3901602-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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cd9f6b32 |
| 10-Aug-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable OSPI nodes at the board level
OSPI nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux an
arm64: dts: ti: k3-am64: Enable OSPI nodes at the board level
OSPI nodes defined in the top-level AM64 SoC dtsi files are incomplete and may not be functional unless they are extended with pinmux and device information.
As the attached OSPI device is only known about at the board integration level, these nodes should only be enabled when provided with this information.
Disable the OSPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Dhruva Gole <d-gole@ti.com> Link: https://lore.kernel.org/r/20230810003814.85450-8-afd@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
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a4956811 |
| 15-Jun-2023 |
Tony Lindgren <tony@atomide.com> |
arm64: dts: ti: Unify pin group node names for make dtbs checks
Prepare for pinctrl-single yaml binding and unify pin group node names.
Let's standardize on pin group node naming ending in -pins. A
arm64: dts: ti: Unify pin group node names for make dtbs checks
Prepare for pinctrl-single yaml binding and unify pin group node names.
Let's standardize on pin group node naming ending in -pins. As we don't necessarily have a SoC specific compatible property for pinctrl-single. I'd rather not add a pattern match for pins somewhere in the name for all the users.
Trying to add matches for pins-default will be futile as on the earlier SoCs we've already seen names like pins-sleep, pins-idle, pins-off and so on that would need to be matched.
And as the node is a pin group, let's prefer to use naming -pins rather than -pin as more pins may need to be added to the pin group later on.
Signed-off-by: Tony Lindgren <tony@atomide.com> [vigneshr@ti.com: Rebase onto latest ti/next and extend to new nodes] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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91f983ff |
| 15-May-2023 |
Andrew Davis <afd@ti.com> |
arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board level
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete and may not be functional unless they are extended with a
arm64: dts: ti: k3-am64: Enable Mailbox nodes at the board level
Mailbox nodes defined in the top-level AM64x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor.
As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information.
Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board.
Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20230515172137.474626-4-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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c48ac0ef |
| 04-Jan-2023 |
Wadim Egorov <w.egorov@phytec.de> |
arm64: dts: ti: Add support for phyBOARD-Electra-AM642
Add basic support for phyCORE-AM64x SoM & phyBOARD-Electra-AM642 CB.
The phyCORE-AM64x [1] is a SoM (System on Module) featuring TI's AM64x So
arm64: dts: ti: Add support for phyBOARD-Electra-AM642
Add basic support for phyCORE-AM64x SoM & phyBOARD-Electra-AM642 CB.
The phyCORE-AM64x [1] is a SoM (System on Module) featuring TI's AM64x SoC. It can be used in combination with different carrier boards. This module can come with different sizes and models for DDR, eMMC, SPI NOR Flash and various SoCs from the AM64x family.
A development Kit, called phyBOARD-Electra [2] is used as a carrier board reference design around the AM64x SoM.
Supported features: * Debug UART * Heartbeat LED * GPIO buttons & LEDs * SPI NOR flash * eMMC * CAN * Ethernet * Micro SD card * I2C EEPROM * I2C RTC * I2C LED Dimmer * USB
For more details, see:
[1] Product page SoM: https://www.phytec.com/product/phycore-am64x [2] Product page CB: https://www.phytec.com/product/phyboard-am64x
Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230104162927.1215033-2-w.egorov@phytec.de
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